Heterojunction bipolar transistor with counter-doped collector region and method of making same

Abstract

A bipolar transistor is supported by a single-crystal silicon substrate including a collector connection region. A first epitaxial region forms a collector region doped with a first conductivity type on the collector connection region. The collector region includes a counter-doped region of a second conductivity type. A second epitaxial region forms a base region of a second conductivity type on the first epitaxial region. Deposited semiconductor material forms an emitter region of the first conductivity type on the second epitaxial region. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

Claims

1. A method of manufacturing a bipolar transistor in a structure including a substrate of single-crystal silicon type including a collector connection region doped with a first conductivity type, the method comprising the steps of: a) coating the substrate in succession with a first insulating layer and a silicon layer; b) etching an opening through the silicon layer and the first insulating layer to expose a top surface of the substrate; c) in the opening, forming by selective epitaxy from the top surface of the substrate a collector region made of semiconductor material doped with the first conductivity type; d) forming a counter-doped region located inside the collector region and doped with both a dopant of the first conductivity type and a dopant of a second conductivity type opposite the first conductivity type; e) forming by selective epitaxy from a top surface of the collector region a base region made of semiconductor material doped with the second conductivity type; and f) forming by deposition on a top surface of the base region an emitter region made of semiconductor material doped with the first conductivity type.

2. The method of claim 1, wherein the first conductivity type is N type and the second conductivity type is P type.

3. The method of claim 1, further comprising laterally insulating the collector region from the silicon layer.

4. The method of claim 3, wherein laterally insulating comprises forming an insulating layer on side walls of the opening.

5. The method of claim 3, wherein laterally insulating comprising forming an air spacer between a side of the collector region and a side of the silicon layer.

6. The method of claim 1, further comprising: forming a stack of layers over the silicon layer, said stack of layers comprising a sacrificial layer made of a first material arranged between two insulating layers made of a second material selectively etchable over the first material; wherein a top surface of the collector region is at a level at least as high as an upper level of the sacrificial layer; etching said stack of layers to reach the sacrificial layer; removing the sacrificial layer to expose a side wall of the base region; and forming a first portion of a base contact region by epitaxy from the side wall of the base region exposed by the removal of the sacrificial layer.

7. The method of claim 6, further comprising: etching through said stack of layers to reach a top surface of the silicon layer, and forming a second portion of the base contact region by epitaxy from the top surface of the silicon layer.

8. The method of claim 6, further comprising: siliciding a top surface portion of each of the single-crystal silicon substrate, the base contact region and the emitter region; depositing a premetallization dielectric layer; and forming metal contacts extending through the premetallization dielectric layer to reach each silicided top surface portion.

9. The method of claim 6, wherein the first material is silicon nitride and the second material is silicon oxide.

10. The method of claim 1, wherein the single-crystal silicon substrate, first insulating layer and silicon layer form a silicon on insulator (SOI) type substrate.

11. The method of claim 1, wherein the silicon layer is a single-crystal silicon layer.

12. The method of claim 11, wherein the silicon layer is doped with the second conductivity type.

13. The method of claim 1, wherein the semiconductor material of the collector region is silicon.

14. The method of claim 1, wherein the semiconductor material of the base region is silicon-germanium.

15. The method of claim 1, wherein the semiconductor material of the emitter region is silicon.

16. The method of claim 1, wherein the base region made of semiconductor material includes a first portion doped with the second conductivity type and a second portion that is undoped.

17. The method of claim 1, wherein a maximum dopant concentration of the first conductivity type in the collector region is 10.sup.20 at/cm.sup.3 and a maximum dopant concentration of the second conductivity type in the counter-doped region is 10.sup.19 at/cm.sup.3.

18. The method of claim 1, wherein the counter-doped region located inside the collector region is bounded at least on top of and below by portions of the collector region.

19. The method of claim 1, wherein forming the counter-doped region located inside the collector region comprises burying the counter-doped region below an upper surface of the collector region.

20. A method of manufacturing a bipolar transistor, the method comprising the steps of: a) etching an opening through a stack of layers to expose a top surface of a semiconductor substrate; b) in the opening, forming by selective epitaxy from the top surface of the semiconductor substrate a collector region made of semiconductor material doped with a first conductivity type; c) implanting a dopant of a second conductivity type opposite the first conductivity type in the semiconductor collector region to form a counter-doped region that is buried below a top surface of the collector region; d) forming by selective epitaxy from a top surface of the collector region a base region made of semiconductor material doped with the second conductivity type; and e) forming by deposition on a top surface of the base region an emitter region made of semiconductor material doped with the first conductivity type.

21. The method of claim 20, wherein the counter-doped region is doped with both the dopant of the first conductivity type and the dopant of a second conductivity type.

22. The method of claim 20, wherein the first conductivity type is N type and the second conductivity type is P type.

23. The method of claim 20, further comprising laterally insulating the collector region from the stack of layers using an insulating layer on side walls of the opening.

24. The method of claim 23, wherein laterally insulating further comprises forming an air spacer between a side of the collector region and a side of a silicon layer of the stack of layers.

25. The method of claim 20, wherein the semiconductor substrate is part of a silicon on insulator (SOI) type substrate.

26. The method of claim 20, wherein the semiconductor material of the collector region is silicon.

27. The method of claim 20, wherein the semiconductor material of the base region is silicon-germanium.

28. The method of claim 20, wherein the semiconductor material of the emitter region is silicon.

29. The method of claim 20, wherein the base region made of semiconductor material includes a first portion doped with the second conductivity type and a second portion that is undoped.

30. The method of claim 20, wherein a maximum dopant concentration of the first conductivity type in the collector region is 10.sup.20 at/cm.sup.3 and a maximum dopant concentration of the second conductivity type in the counter-doped region is 10.sup.19 at/cm.sup.3.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with:

(2) FIG. 1 is a cross sectional view of a conventional bipolar transistor;

(3) FIGS. 2-16 are cross sectional views that illustrate steps of an embodiment of a method for manufacturing a heterojunction bipolar transistor;

(4) FIG. 17A is a cross sectional view of the completed bipolar transistor with contacts and a collector region having a counter-doped region of opposite conductivity type;

(5) FIG. 17B is a cross sectional view of the completed bipolar transistor with contacts and a collector region that does not have a counter-doped region of opposite conductivity type;

(6) FIG. 18A is a cross sectional view of the completed bipolar transistor with contacts, an air spacer and a collector region having a counter-doped region of opposite conductivity type; and

(7) FIG. 18B is a cross sectional view of the completed bipolar transistor with contacts, an air spacer and a collector region that does not have a counter-doped region of opposite conductivity type.

DETAILED DESCRIPTION

(8) The same elements have been designated with the same reference numerals in the various drawings and, further, the various drawings are not to scale. For clarity, only those elements which are useful to the understanding of the described embodiments have been shown and are detailed. In particular, certain masks used during the steps of the manufacturing method described hereafter have not been shown.

(9) In the following description, terms “high”, “side”, “lateral”, “top”, “above”, “under”, “on”, “upper”, and “lower” refer to the orientation of the concerned elements in the corresponding drawings.

(10) In FIG. 2, a structure comprises a single-crystal silicon substrate 101 including insulating structures 103, for example, of the deep trench isolation (DTI) type, are provided to delimit a location where a heterojunction bipolar transistor is desired to be formed. At the location of the transistor, substrate 101 comprises a heavily-doped region 105 of a first conductivity type, for example, type N. The region 105 is flush with the upper (top) surface of substrate 101 and forms a collector connection region for the heterojunction bipolar transistor.

(11) The upper surface of substrate 101 is coated with an insulating layer 107 (that is made of silicon dioxide, for example) that is coated with a semiconductor material (for example, silicon) layer 109. Layer 109 may be a polysilicon layer deposited on insulating layer 107. Layer 109 may also be a single-crystal silicon layer. As an example, the layer 109 may correspond to the silicon layer of a structure of SOI (Semiconductor On Insulator) type. Layer 109 may have a doping of a second conductivity type, for example, type P.

(12) The deep trench isolation insulating structures 103 may be formed before the deposition of each of the layers forming the stack of layers 111, particularly in the case where silicon layer 109 is the silicon layer of an SOI-type structure.

(13) A stack of layers 111 rests on layer 109. The stack 111 comprises a first insulating layer 119 that is coated with a second insulating layer 113 that is coated with a third insulating layer 115 that is coated with a fourth insulating layer 117. The material of layers 115 and 119 and the material of layers 113 and 117 are selected to be selectively etchable over each other. In an embodiment, the layers 113 and 117 are made of silicon nitride and the layers 115 and 119 are made of silicon oxide.

(14) FIG. 3 shows the structure after the etching of an opening 121 that crosses completely through the stack 111, the silicon layer 109, and the insulating layer 107 all the way to reach the collector connection region 105 at the top surface of the substrate 101. The etch process used may, for example, comprise major anisotropic and minor isotropic etch steps.

(15) FIG. 4 shows the structure after lining side walls of the opening 121 with an insulating layer 123. The layer 123 may, for example, be made of silicon oxide material. The bottom of opening 121 at the top surface of the substrate 101 is not covered by the layer 123.

(16) FIG. 5 shows the structure after forming, in opening 121, a transistor collector region 125 of the heterojunction bipolar transistor. The collector region 125 is made of a region of single-crystal silicon formed by selective epitaxy from the top surface of substrate 101. The collector region 125 has a thickness such that a top surface of the collector region 125 is at least as high as a top surface of the layer 109 and lower than or equal to a bottom surface of layer 115. Preferably, the level of the top surface of collector region 125 is slightly lower, for example, by from 1 to 3 nm, than the lower surface of layer 115. The collector region 125 is doped during the epitaxy or (less probably) by implantation after the epitaxy with the first conductivity type. As an example, the collector region 125 is doped with phosphorus atoms, possibly associated with carbon atoms to limit the exodiffusion of phosphorus atoms, and/or with arsenic atoms. An exposed portion of the layer 123 after formation of the collector region 125 is removed.

(17) If the bipolar transistor is to be of the MV type or HV type, a counter doping of the collector region 125 is performed by implanting dopant of the second conductivity type, for example, type P. This forms a counter-doped region 126 at or near the top surface of the collector region 125. Thus, both N type and P type dopants are present in the region 126 of the collector region 125 at a location which is adjacent to the not-yet-formed base region of the transistor. The structure is shown in FIG. 6.

(18) If the bipolar transistor is instead to be of the HS type, the structure is masked so that counter doping implant does not affect the collector region 125. In this way, it will be understood that the process disclosed herein for fabricating bipolar transistors is identical for MV, HV and HS type bipolar transistors with the exception of the masking and counter doping implant in the collector region 125 that is provided solely for MV and HV type transistors. Concurrent fabrication of MV, HV and HS type bipolar transistors on a common substrate is thus possible. In the remaining FIGS. 7-16 illustrating the fabrication process, the counter-doped region 126 is present, but it will be understood that this counter-doped region 126 relates only to those bipolar transistors that are of the MV and HV type (with a final structure as shown in FIG. 17A). With respect to bipolar transistors of the HS type (with a final structure as shown in FIG. 18B) the reader should understand that the counter-doped region 126 would not be present.

(19) FIG. 7 shows the structure after the forming, in opening 121, a transistor base region 127 comprising a stack of a doped region 127a and a silicon capping region 127b. The doped region 127a of the transistor base region 127 is made of a single-crystal semiconductor material such as silicon or, preferably, silicon-germanium as in the present embodiment. Doped region 127a is formed by selective epitaxy from collector region 125. The doped region 127a has a thickness such that a top surface of the doped region 127a is higher than a top surface of the insulating layer 113 but below the top surface of the layer 115. The doped region 127a is doped with the second conductivity type, preferably during the epitaxy. As an example, doped region 127a is doped with boron atoms, possibly associated with carbon atoms to avoid the exodiffusion of the boron atoms. The silicon capping region 127b is made of undoped single crystal semiconductor material and is formed by selective epitaxy from the top surface of the doped region 127a. The silicon capping region 127b has a thickness such that a top surface of the silicon capping region 127b is below the top surface of the layer 115.

(20) In FIG. 8, spacers 129 have been formed in the opening 121. The spacers 129 rest on the top surface of silicon capping region 127b and border the sidewall surfaces of at least the layer 115. An opening 124 is provided between the spacers 129 to expose a top surface of the silicon capping region 127b. The spacers 129 have, for example, in cross-sectional view, an L shape. As an example, the spacers 129 are made of silicon oxide. The spacers are formed by forming a silicon oxide layer on the sidewalls of the layer 115 and top surface of the silicon capping region 127b in the opening 121. A nitride deposit is then made on the silicon oxide layer followed by an etch which preferentially removes nitride material from horizontal surfaces. The nitride material remaining after the etch forms a “D” shape spacer 131 which functions as a mask. This mask is used for performing a further etch to remove a portion of the silicon oxide layer to make the opening 124.

(21) The remaining nitride material of the spacer 131 for the etch mask as well as the silicon nitride layer 117 are then removed by using an isotropic etching process. The result is shown in FIG. 9.

(22) A silicon layer 133 doped with the first conductivity type is deposited all over the structure and fills openings 121 and 124. As an example, the silicon layer is deposited by RTCVD (“Reduced Temperature Chemical Vapor Deposition”), which enables the deposited silicon to be monocrystalline at the interface with the silicon capping region 127b of the transistor base region 127. A chemical mechanical polish may then be performed to planarize the top surface of the layer 133. An etch mask formed by a layer 135 (made of silicon oxide, for example) is then formed on the planar top surface of layer 133. The result is shown in FIG. 10.

(23) Convention lithographic processing is then performed to pattern the etch mask layer 135. An anisotropic etch is then performed to remove the unmasked portion of the doped silicon layer 133 and the unmasked portion of the oxide layer 115 all the way to nitride layer 113. The result is shown in FIG. 11. Thus, a portion 133′ of the silicon layer 133 is left in place and forms the emitter region of the heterojunction bipolar transistor. The emitter region 133′ comprises a central portion resting on the transistor base region 127 at silicon capping region 127b (extending through the opening 124) and a peripheral portion that laterally extends beyond the base region 127 and rests on a remaining portion of the layer 115.

(24) A deposition of a silicon oxide layer 141 is made to cover the top of layer 135 and the side walls of the emitter region 133′ and the side walls of the remaining portion of the oxide layer 115. Then, an anisotropic etch is performed to remove the silicon oxide from the top surface of the layer 113. The result is shown in FIG. 12. In an embodiment, the layer 135 may be removed prior to the deposition of layer 141.

(25) In the step illustrated by FIG. 13, the nitride layer 113 has been removed by isotropic etching selective over the material of layers 115, 119 and 141. This exposes the lateral side wall of the base region 127 (more specifically, a lateral side wall of the doped region 127a).

(26) FIG. 14 shows the structure after formation of a first portion 149 of a base contact region 151. The first portion 149 is made of single-crystal silicon formed by selective epitaxy from the lateral side wall of the base region 127. Thus, the portion 149 of the base contact region 151 is monocrystalline, which advantageously enables to decrease the resistance at the interface between base contact region 151 and base region 127 with respect to the case of a transistor which would have its base contact region made of polysilicon. In this example, the first portion 149 of base contact region 151 extends laterally all the way at least to the peripheral edge of the remaining portion of layer 141.

(27) Conventional isotropic etching techniques are then used to selectively remove a portion of insulating layer 119 and expose a top surface of the semiconductor layer 109. The result is shown in FIG. 15.

(28) FIG. 16 shows the structure after formation of a second portion 153 of the base contact region 151. The second portion 153 is made of polycrystalline silicon formed by selective epitaxy of doped silicon of the second conductivity type from the top surface of the polysilicon semiconductor layer 109 and the lateral side wall of the first portion 149. In the case where silicon layer 109 was not doped at the step of FIG. 1, it may be doped by diffusion of dopant atoms from the base contact region 151, and in particular from the first portion 149.

(29) Advantageously, if the starting point for the substrate is a SOI-type structure, then the semiconductor layer 109 is made of single-crystal silicon and the second portion 153 of base contact region 151 will also be made of single-crystal silicon grown by selective epitaxy. Advantageously, the entire base contact region 151 in such an implementation will be made of single-crystal silicon which enables to decrease the resistance of base contact region 151, and thus decrease the resistance of access to the base region 127 with respect to the case of a transistor where all or part of the base contact region is made of polysilicon.

(30) In an alternative implementation, the first and second portions 149 and 153 of the base contact region 151 may be formed simultaneously. To achieve this, the nitride layer 113 is removed to expose the lateral side wall of the base region 127 and the portion of insulating layer 119 is removed to expose the top surface of the semiconductor layer 109. These removal steps are performed prior to performing any epitaxial growth. Then, the first and second portions 149 and 153 are simultaneously formed by epitaxy from the side wall of base region 127 and the top surface of silicon layer 109. A structure similar to that shown in FIG. 16 is then obtained.

(31) The bipolar transistor further includes structure for making electrical contact to the emitter (E), base (B) and collector (C) terminals of the heterojunction bipolar transistor. A premetallization dielectric layer 161 covers the structure. A layer of silicide 163 is provided at each contact location with the collector connection region 105, the emitter region 133′ and the base contact region 151. A metal contact plug 165 extends through the premetallization dielectric layer 161 to make contact with the silicide 163. FIG. 17A shows the bipolar transistor in the configuration (supporting MV type and HV type devices) which includes the counter-doped region 126 within the collector region 125. FIG. 17B shows the bipolar transistor in the configuration (supporting an HS type device) that does not include the counter-doped region 126 within the collector region 125.

(32) Access to the collector connection region 105 for the purpose of exposing the top surface of the substrate 101 can be achieved by forming a mask over the emitter region 133′ and on portions of the base contact region 151 that laterally extend adjacent to the emitter region 133′. An etch may then be performed through the mask. The premetallization dielectric layer 161 may then be deposited over the structures.

(33) The silicide process to form silicide layers 163 may be performed using well known techniques at any suitable point in the fabrication process. The silicide layers 163 are formed at the upper surface of the emitter region 133′, on the upper surface of collector connection region 105, and on the upper surface of the base contact region 151.

(34) Each step of the previously-described method is a step currently used in standard CMOS methods, whereby this method is compatible with standard CMOS methods. Thus, the bipolar transistors as shown herein may be fabricated on a common substrate with CMOS devices to support BiCMOS circuit implementations.

(35) As an example, the various previously-described layers, regions, portions may have the following dimensions: a thickness in the range from 10 to 75 nm, for example, 25 nm, for insulating layer 107; a thickness in the range from 3 to 20 nm, for example, 7 nm, for silicon layer 109; a thickness in the range from 10 to 40 nm, for example, 20 nm, for insulating layer 113; a thickness in the range from 5 to 20 nm, for example, 10 nm, for insulating layer 119; a thickness in the range from 10 to 50 nm, for example, 25 nm, for layers 115 and 117; a width from 0.1 to 0.3 μm, for example, 0.2 μm, for opening 121; and a thickness in the range from 50 to 200 nm, for example, 75 nm, for the silicon layer 133.

(36) The doping levels of the various previously-described layers, regions, portions will be selected conventionally.

(37) In the context of FIG. 17A, an MV type device is distinguishable from an HV type device by the dose and/or energy of the counter-doping implantation. Conventional lithographic processes can be used to differentiate between the MV type devices and the HV type devices during fabrication.

(38) The bipolar transistors of FIGS. 17A and 17B illustrate the use of the insulating layer 123 to insulate the collector region 125 from the layer 109 (which is used for making contact to the base region). It will be understood that other insulating structures may instead be used. For example, FIGS. 18A and 18B illustrate the use of an air spacer 128 positioned between the collector region 125 and the layer 109. The process for forming a bipolar transistor with an air spacer 128 is taught by U.S. patent application Ser. No. 15/783,469 (the disclosure of which is incorporated by reference). FIG. 18A shows the bipolar transistor in the configuration (supporting MV type and HV type devices) which includes the counter-doped region 126 within the collector region 125. FIG. 18B shows the bipolar transistor in the configuration (supporting an HS type device) that does not include the counter-doped region 126 within the collector region 125.

(39) With respect to line 150 of FIGS. 17A and 17B, an example dopant profile for the structure would include first conductivity type (for example, N) dopants in the regions 133′ and 125 in a range of 1×10.sup.19 to 1×10.sup.20 at/cm.sup.3 and second conductivity type (for example, P) dopants in the region 127a in a range of 1×10.sup.19 to 5×10.sup.19 at/cm.sup.3 and in the region 126 in a range of 5×10.sup.18 to 1×10.sup.19 at/cm.sup.3. More particularly, a maximum doping concentration of the first conductivity type dopant in region 125 will be greater than a maximum doping concentration of the second conductivity type dopant in region 126 (for example, to a degree on the order of about one order of magnitude; such as where region 125 has a maximum doping concentration of 1×10.sup.20 at/cm.sup.3 and region 126 has a maximum doping concentration of 1×10.sup.19 at/cm.sup.3).

(40) With reference once again to FIG. 6 and the implantation of the counter dopant to form counter-doped region 126, and for a given energy level of the implantation, the dosage level of the second conductivity type dopant implantation has an effect on the common emitter configuration breakdown voltage (BV.sub.CEO) in that the breakdown voltage increases with increase in dosage level. Furthermore, for a given energy level of the implantation, an increase in the dosage level of the second conductivity type dopant may cause a decrease in frequency of the transit frequency (fT) and the maximum frequency (fMAX).

(41) The energy level used for the implant of the second conductivity type dopant also has an effect on the common emitter configuration breakdown voltage (BV.sub.CEO). For example, an increase in energy level may result in a decrease in the breakdown voltage. The energy level used for the implant of the second conductivity type dopant may also affect the frequency of the transit frequency (fT). For example, an increase in energy level may result in an increase in transit frequency.

(42) It will be understood that the bipolar transistors described herein and illustrated in the figures may be of either the NPN (first dopant conductivity type is N and second dopant conductivity type is P) or PNP type (first dopant conductivity type is P and second dopant conductivity type is N).

(43) The transistor of FIG. 17A (or 18A) and the transistor of FIG. 17B (or 18B) may be provided and supported on a common substrate 101 in different regions of that substrate and used to form an integrated circuit which includes bipolar transistors of two or more of the HS/MV/HV type. The substrate 101 may further support, in another region of that substrate, conventional CMOS transistors to form an integrated circuit of BiCMOS type which includes bipolar transistors of two or more of the HS/MV/HV type along with CMOS devices.

(44) Specific embodiments have been described. Various alterations, modifications, and improvements will occur to those skilled in the art. In particular, the number and the order of the steps of the previously-described method may be adapted by those skilled in the art. For example, the steps of cleaning the exposed surfaces of the semiconductor regions from which the epitaxies are performed may be provided before each epitaxy step. Additional spacer structures may be provided as needed.

(45) During the step of forming the collector region 125, only a central and/or lower portion of region 125 may be doped by selective implantation of dopant atoms. This is shown by the dopant profiles of FIGS. 18A and 18B.

(46) It will readily occur to those skilled in the art that the previously-indicated conductivity types for the layers, regions, etc. may all be inverted.

(47) Although an embodiment of a method where the base region 127 is made of silicon-germanium has been described, the base region 127 may also be formed by epitaxy of silicon, germanium, or another semiconductor material capable of growing by epitaxy from silicon and from which silicon can grow by epitaxy. For example, this method may be used to manufacture transistors using III-V semiconductors.

(48) Alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.