Abstract
An integrated circuit comprising a SGT MOSFET and a SBR is disclosed. The SBR horizontally disposed in different areas to the SGT MOSFET on single chip creates a low potential barrier for majority carrier in MOS channel, therefore has lower forward voltage and reverse leakage current than conventional Schottky Barrier Rectifier. Moreover, in some preferred embodiment, a MSO structure is applied to the shielded gate structure to further reduce the on-resistance.
Claims
1. An integrated circuit comprising a SGT MOSFET and a SBR horizontally disposed in two different areas on single chip, further comprising: an epitaxial layer of a first conductivity type extending over a substrate of said first conductivity type, said substrate having a higher doping concentration than said epitaxial layer; said SGT MOSFET further comprising: a plurality of first type trenches formed in said epitaxial layer, each of said first type trenches being filled with a shielded electrode and a first gate electrode, said shielded electrode being insulated from said epitaxial layer by a first insulating film, said first gate electrode being insulated from said epitaxial layer by a first gate oxide film, said shielded electrode and said first gate electrode being insulated from each other; a first body region of a second conductivity type having a source region of said first conductivity type thereon and surrounding said first gate electrode padded by said first gate oxide film; said SBR further comprising: at least one second type trench formed in parallel with said first type trenches, said second type trench being filled with said shielded electrode and a second gate electrode, said shielded electrode being insulated from said epitaxial layer by said first insulating film, said second gate electrode being insulated from said epitaxial layer by a second gate oxide film, said shielded electrode and said second gate electrode being insulated from each other; said second gate oxide film having a thickness less than said first gate oxide film; a second body region of said second conductivity type having said source region thereon and surrounding said second gate electrode padded by said second gate oxide film; said first body region, said second body region, said source region and said second gate electrode being shorted to a source metal through a plurality of trenched contacts; and said second body region has shallower junction depth and lower doping concentration than said first body region.
2. (canceled)
3. The integrated circuit of claim 1, wherein said second body region has same junction depth and same doping concentration as said first body region.
4. The integrated circuit of claim 1, wherein said epitaxial layer comprises a single epitaxial layer having uniform doping concentration.
5. The integrated circuit of claim 1, wherein said epitaxial layer comprises a lower epitaxial layer with a resistivity R1 and an upper epitaxial layer with a resistivity R2, wherein R1>R2, said first and second type trenches are penetrating through said upper epitaxial layer and extending into said lower epitaxial layer.
6. The integrated circuit of claim 1, wherein said epitaxial layer further comprises an implanted drift region of said first conductivity type formed in upper portion of said epitaxial layer, said first and second type trenches are extending within said implanted drift region.
7. The integrated circuit of claim 1, wherein with each of said first type trenches, said shielded electrode is disposed in lower portion and said first gate electrode is disposed in upper portion, said shielded electrode and said first gate electrode are insulated from each other by a second insulating film; with said second type trench, said shielded electrode is disposed in lower portion and said second gate electrode is disposed in upper portion, said shielded electrode and said second gate electrode are insulated from each other by said second insulating film.
8. The integrated circuit of claim 7, wherein said first insulating film is a single oxide film having uniform thickness.
9. The integrated circuit of claim 7, wherein said first insulating film has multiple stepped oxide structure having greatest thickness along bottom of said first and second type trenches.
10. The integrated circuit of claim 1, wherein within each of said first type trenches, said shielded electrode is disposed in the middle and said first gate electrode is disposed surrounding upper portion of said shielded electrode, said shielded electrode and said first gate electrode are insulated from each other by said first gate oxide film; within said second type trench, said shielded electrode is disposed in the middle and said second gate electrode is disposed surrounding upper portion of said shielded electrode, said shielded electrode and said second gate electrode are insulated from each other by said second gate oxide film.
11. The integrated circuit of claim 1, wherein said second type trench has trench width and trench depth same as said first type trenches.
12. The integrated circuit of claim 1, wherein said second type trench has trench width and trench depth greater than said first type trenches.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:
[0014] FIG. 1A is a cross-sectional view of a conventional SGT MOSFET of prior art.
[0015] FIG. 1B is a cross-sectional view of another conventional SGT MOSFET of prior art.
[0016] FIG. 1C is a cross-sectional view of MSO MOSFET of prior art.
[0017] FIG. 2A is a cross-sectional view of a preferred embodiment according to the present invention.
[0018] FIG. 2B is a cross-sectional view of another preferred embodiment according to the present invention.
[0019] FIG. 2C is a cross-sectional view of another preferred embodiment according to the present invention.
[0020] FIG. 3A is a cross-sectional view of another preferred embodiment according to the present invention.
[0021] FIG. 3B is a cross-sectional view of another preferred embodiment according to the present invention.
[0022] FIG. 3C is a cross-sectional view of another preferred embodiment according to the present invention.
[0023] FIG. 4 is a cross-sectional view of another preferred embodiment according to the present invention.
[0024] FIG. 5 is a cross-sectional view of another preferred embodiment according to the present invention.
[0025] FIG. 6A is a cross-sectional view of another preferred embodiment according to the present invention.
[0026] FIG. 6B is a cross-sectional view of another preferred embodiment according to the present invention.
[0027] FIG. 6C is a cross-sectional view of another preferred embodiment according to the present invention.
[0028] FIG. 7A is a cross-sectional view of another preferred embodiment according to the present invention.
[0029] FIG. 7B is a cross-sectional view of another preferred embodiment according to the present invention.
[0030] FIG. 7C is a cross-sectional view of another preferred embodiment according to the present invention.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0031] In the following Detailed Description, reference is made to the accompanying drawings, which forms a part thereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top”, “bottom”, “front”, “back”, etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purpose of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.
[0032] Please refer to FIG. 2A for a preferred embodiment of this invention wherein an N-channel SGT MOSFET 200 and a SBR 200′ are integrated on a single chip which is formed on an N+ substrate 201 with a less doped single N− epitaxial layer 202 extending thereon. Inside the N epitaxial layer 201, a plurality of first type trenches 203 and at least one second type trench 204 are formed vertically downward, each filled with a shielded gate structure comprising a shielded electrode 205 (SG, as illustrated) padded by a first insulating film 206 in lower portion. The difference of the filling-in structure between the first and the second type trenches is that: the first type trenches 203 comprise a first gate electrode 207 which is isolated from the shielded electrode 205 by a second insulating film 208 while insulated from the N− epitaxial layer by a first gate oxide film 209, and the first gate electrode 207 is further connected to a gate metal (not shown) of the SGT 200; the second type trench 204 comprises a second gate electrode 210 which is isolate from the shielded electrode 205 by the second insulating film 208 while insulated from the N− epitaxial layer by a second gate oxide film 211, wherein the second gate oxide film 211 has a thickness less than the first gate oxide film 209 for formation of SBR, and furthermore, the second gate electrode 210 is connected to a source metal 212 through a trenched contact 213-1. In the SGT MOSFET, a p1 body region 214 having a n+ source region 215 thereon is extending in upper portion of the N− epitaxial layer and surrounding the first gate electrodes 207 padded by the first gate oxide film 209, while in the SBR, a p2 body region 216 having the n+ source region 215 thereon is extending in upper portion of the N− epitaxial layer and surrounding the second gate electrode 210 padded by the second gate oxide film 211, wherein the p2 body region 216 has a shallower junction depth and a lower doping concentration than the p1 body region 214 to provide a short channel length for the SBR. The p1 body region 214, the p2 body region 216 and the n+ source region both in the SGT and SBR are shorted to the source metal 212 through a plurality of trenched contacts 213-2, 213-3 and 213-4, respectively. All the trenched contacts (213-1-213-4) filled with metal plug and barriers are implemented by penetrating through a contact insulating layer 217 and extending into the body region, with each bottom surrounded by a p+ body contact region 218. Trench width and depth of the second type trench 204 are equal to or wider than the first type trenches 203 to avoid early breakdown occurring at the SBR region.
[0033] Please refer to FIG. 2B for another preferred embodiment of the present invention, compared with FIG. 2A, the integrated circuit in FIG. 2B comprising a SGT MOSFET 300 and a SBR 300′ is formed in an epitaxial layer 302, which further comprises a lower N1 epitaxial layer 302-1 with a resistivity R1 and an upper N2 epitaxial layer 302-2 with a resistivity R2, the first type trenches 303 in SGT and the second type trench 304 in SBR are all penetrating through the upper epitaxial layer 302-2 and having trench bottoms within the lower epitaxial layer 302-1. In this embodiment, the resistivity has a function relationship that R1>R2, to provide a higher resistivity epitaxial layer near the trench bottom corners for preventing an early breakdown, while to provide a lower resistivity epitaxial layer above the trench bottom to achieve a reduced device resistance.
[0034] Please refer to FIG. 2C for another preferred embodiment of the present invention, compared with FIG. 2A, the integrated circuit in FIG. 2C comprising a SGT MOSFET 400 and a SBR 400′ is formed in an N− epitaxial layer 402, which further comprises an N implanted drift region 413 thereon. The first type trenches 403 in SGT and the second type trench 404 in SBR are all surrounded by the N implanted drift region 413, because in the manufacturing process, the N implanted drift region 413 is formed by performing angle implantation from opening of the first and second type trenches into mesa area between the trenches, or by performing implantation from top of the mesa area between the first and second type trenches.
[0035] FIG. 3A shows another preferred embodiment of the present invention, wherein an integrated circuit comprising an N-channel SGT MOSFE 500 and a SBR 500′ has a similar device structure to FIG. 2A, except that, in FIG. 3A, the p body region 514 in the SBR 500′ has a same junction depth and same doping concentration as in the SGT MOSFET 500 for preventing the short channel region in FIG. 2A from punching through.
[0036] FIG. 3B shows another preferred embodiment of the present invention, wherein an integrated circuit comprising an N-channel SGT MOSFET 600 and a SBR 600′ has a similar device structure to FIG. 2B, except that, in FIG. 3B, the p body region 614 in the SBR 600′ has a same junction depth and same doping concentration as in the SGT MOSFET 600 for preventing the short channel region in FIG. 2B from punching through.
[0037] FIG. 3C shows another preferred embodiment of the present invention, wherein an integrated circuit comprising an N-channel SGT MOSFET 700 and a SBR 700′ has a similar device structure to FIG. 2C, except that, in FIG. 3C, the p body region 714 in the SBR 700′ has a same junction depth and same doping concentration as in the SGT MOFET 700 for preventing the short channel region in FIG. 2C from punching through.
[0038] FIG. 4 shows another preferred embodiment of the present invention, wherein an integrated circuit comprising an N-channel SGT MOSFET 800 and a SBR 800′ has a similar device structure to FIG. 2C, except that, in FIG. 4, the first insulating film 806 in all the trenches has MSO structure to further reduce the on-resistance while maintaining the same breakdown voltage. As shown in FIG. 4, the first insulating film 806 has a greatest thickness along bottoms of all the trenches.
[0039] FIG. 5 shows another preferred embodiment of the present invention, wherein an integrated circuit comprising an N-channel SGT MOSFET 900 and a SBR 900′ has a similar device structure to FIG. 3C, except that, in FIG. 5, the first insulting film 906 in all the trenches has MSO structure to further reduce the on-resistance while maintaining the same breakdown voltage. As shown in FIG. 5, the first insulating film 806 has a greatest thickness along bottoms of all the trenches.
[0040] FIG. 6A shows another preferred embodiment of the present invention, wherein an integrated circuit comprising an N-channel SGT MOSFET 1000 and a SBR 1000′ has a similar device structure to FIG. 2A, except that, in FIG. 6A, the first type trenches 1003 and the second type trench 1004 comprise a different shielded gate structure. In the first type trenches 1003 of the SGT MOSFET 1000, the shielded gate structure comprises: a shielded electrode 1005 disposed in the middle of the trench; a first gate electrode 1007 disposed in the middle of the shielded electrode 1005 and the trench sidewall in upper portion of the first type trenches 1003; wherein the shielded electrode 1005 is insulated from the N− epitaxial layer 1002 by a first insulating film 1006, the first gate electrode 1007 is isolated from the shielded electrode 1005 and the epitaxial layer by a first gate oxide film 1009. In the second type trench 1004 of the SBR 1000′, the shielded gate structure comprises: the shielded electrode 1005 disposed in the middle of the trench 1004; a second gate electrode 1010 disposed in the middle of the shielded electrode 1005 and the trench sidewall in upper portion of the second type trench 1004; wherein the shielded electrode 1005 is insulated from the N− epitaxial layer 1002 by the first insulating film 1006, the second gate electrode 1010 is isolated from the shielded electrode 1005 and the epitaxial layer by a second gate oxide film 1011, wherein the second gate oxide film 1011 has a thickness less than the first gate oxide film 1009 for formation of the SBR 1000. Trench width and trench depth of the second type trench 1004 are equal to or greater than the first type trenches 1003 to avoid early breakdown occurring at the SBR region.
[0041] Please refer to FIG. 6B for another preferred embodiment of the present invention, compared with FIG. 6A, the integrated circuit in FIG. 6B comprising an N-channel SGT MOSFET 1100 and a SBR 1100′ is formed in an epitaxial layer 1102, which further comprises a lower N1 epitaxial layer 1102-1 with a resistivity R1 and an upper N2 epitaxial layer 1102-2 with a resistivity R2, the first type trenches 1103 in SGT and the second type trench 1104 in SBR are all penetrating through the upper epitaxial layer 1102-2 and having trench bottoms within the lower epitaxial layer 1102-1. In this embodiment, the resistivity has a function relationship that R1>R2, to provide a higher resistivity epitaxial layer near the trench bottom corners for preventing an early breakdown, while to provide a lower resistivity epitaxial layer above the trench bottom to achieve a reduced device resistance.
[0042] Please refer to FIG. 6C for another preferred embodiment of the present invention, compared with FIG. 6A, the integrated circuit in FIG. 6C comprising an N-channel SGT MOSFET 1200 and a SBR 1200′ is formed in an N− epitaxial layer 1202, which further comprises an N implanted drift region 1213 thereon. The first type trenches 1203 in SGT and the second type trench 1204 in SBR are all surrounded by the N implanted drift region 1213, because in the manufacturing process, the N implanted drift region 1213 is formed by performing angle implantation from opening of the first and second type trenches into mesa area between the trenches, or by performing implantation from top of the mesa area between the first and second type trenches.
[0043] FIG. 7A shows another preferred embodiment of the present invention, wherein an integrated circuit comprising an N-channel SGT MOSFE 1300 and a SBR 1300′ has a similar device structure to FIG. 6A, except that, in FIG. 7A, the p body region 1314 in the SBR 1300′ has a same junction depth and same doping concentration as in the SGT MOSFET 1300 for preventing the short channel region in FIG. 6A from punching through.
[0044] FIG. 7B shows another preferred embodiment of the present invention, wherein an integrated circuit comprising an N-channel SGT MOSFET 1400 and a SBR 1400′ has a similar device structure to FIG. 6B, except that, in FIG. 7B, the p body region 1414 in the SBR 1400′ has a same junction depth and same doping concentration as in the SGT MOSFET 1400 for preventing the short channel region in FIG. 6B from punching through.
[0045] FIG. 7C shows another preferred embodiment of the present invention, wherein an integrated circuit comprising an N-channel SGT MOSFET 1500 and a SBR 1500′ has a similar device structure to FIG. 6C, except that, in FIG. 7C, the p body region 1514 in the SBR 1500′ has a same junction depth and same doping concentration as in the SGT MOFET 1500 for preventing the short channel region in FIG. 6C from punching through.
[0046] Although the present invention has been described in terms of the presently preferred embodiments, it is to be understood that such disclosure is not to be interpreted as limiting. Various alternations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alternations and modifications as fall within the true spirit and scope of the invention.
