Component semiconductor structure

Abstract

A component semiconductor structure having a semiconductor layer, which has a front side and a back side, at least one integrated circuit being formed on the front side and a first oxide layer being formed on the back side, a monolithically formed semiconductor body having a top surface and a back surface being provided, and a second oxide layer being formed on the back surface, and the two oxide layers being integrally connected to each other, and a sensor region formed between the top surface and the back surface and having a three-dimensional isotropic Hall sensor structure being disposed in the semiconductor body, the Hall sensor structure extending from a buried lower surface up to the top surface, and at least three first highly doped semiconductor contact regions being formed on the top surface and at least three second highly doped semiconductor contact regions being formed on the lower surface.

Claims

1. A component semiconductor structure comprising: a semiconductor layer having a front side and a back side; at least one integrated circuit formed on the front side; a first oxide layer being formed on back side; a monolithically formed semiconductor body having a top surface and a back surface; a second oxide layer formed on the back surface, the first and second oxide layers being integrally connected to each other via a thermal compression joining method; a shared insulating layer being formed between the semiconductor body and the semiconductor layer; a sensor region formed between the top surface and the back surface and having a three-dimensional isotropic Hall sensor structure being disposed in the semiconductor body, the Hall sensor structure extending from a buried lower surface up to an upper side; a circumferential trench structure delimiting the sensor region of the semiconductor body; at least three first highly doped semiconductor contact regions spaced a distance apart, and formed on the top surface; and at least three second highly doped semiconductor contact regions spaced a distance apart and having a second conductivity type and formed on lower surface, wherein the highly doped first semiconductor contact region is connected with the aid of an assigned first terminal contact and the highly doped second semiconductor contact region is connected with the aid of an assigned second terminal contact, wherein the first semiconductor contact regions are disposed offset from the second semiconductor contact regions in a projection perpendicular to the top surface, and wherein the first semiconductor contact regions and the second semiconductor contact regions each have a multiple rotational symmetry with respect to an axis of symmetry viewed perpendicularly on the top surface and on the lower surface of the semiconductor body.

2. The component semiconductor structure according to claim 1, wherein the semiconductor body has a thickness between 2 μm and 50 μm in the sensor region.

3. The component semiconductor structure according to claim 1, wherein a ratio between the thickness and length of the semiconductor body in the sensor region is in a range between 0.6 and 1.4 or in a range between 0.8 and 1.2.

4. The component semiconductor structure according to claim 1, wherein the second terminal contacts comprise a highly doped polysilicon of a second conductivity type or a metal.

5. The component semiconductor structure according to claim 1, wherein the integrated circuit is in an electrical operative connection with the Hall sensor structure.

6. The component semiconductor structure according to claim 1, wherein the semiconductor layer has regions of a first conductivity type, and the semiconductor body has regions predominantly of a second conductivity type.

7. The component semiconductor structure according to claim 6, wherein the first conductivity type is p and the second conductivity type is n or vice versa.

8. The component semiconductor structure according to claim 1, wherein the semiconductor body and the semiconductor layer have a substantially identical lateral extension.

9. The component semiconductor structure according to claim 1, wherein a continuous oxide layer is formed in the semiconductor layer between the front side and the back side.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:

(2) FIG. 1 shows a cross-sectional view of a first specific embodiment;

(3) FIG. 2 shows a cross-sectional view of a second specific embodiment; and

(4) FIG. 3 shows a top view of an upper side of the sensor region illustrated in FIG. 1 or FIG. 2.

DETAILED DESCRIPTION

(5) The illustration in FIG. 1 shows a cross-sectional view of an exemplary embodiment having a sensor region HSENS.

(6) The illustration in FIG. 1 shows a cross-sectional view of a component semiconductor structure WF. Component semiconductor structure WF comprises a semiconductor body HLK manufactured from a first semiconductor wafer and a semiconductor layer HALS manufactured from a second semiconductor wafer. The two semiconductor wafers are joined by means of a wafer bonding process. The semiconductor wafers are preferably made up of silicon.

(7) Semiconductor layer HALS has a front side VS and a back side RS, at least one integrated circuit IS being formed on front side VS and a first oxide layer being formed on back side RS.

(8) Monolithically formed semiconductor body HLK has a top surface OF and a back surface RF. A second oxide layer is formed on back surface RS.

(9) The two oxide layers are integrally connected to each other by means of a thermal compression joining method, a shared insulating layer being formed between semiconductor body HLK and semiconductor layer HALS.

(10) Semiconductor body HLK has a sensor region formed between top surface OF and back surface RF including a three-dimensional isotropic Hall sensor structure HSENS, Hall sensor structure HSENS extending from a buried lower surface UF up to an upper side OS below top surface OF. The sensor region of semiconductor body HLK is delimited by a circumferential trench structure TR.

(11) The second oxide layer is formed below lower surface UF. Another insulating layer is also formed on upper side OS up to top surface OF. In other words, Hall sensor structure HSENS extends over the entire thickness of the semiconductor material.

(12) Semiconductor body HLK has a thickness between 2 μm and 50 μm in the sensor region.

(13) The ratio between the thickness and length of semiconductor body HLK in the sensor region is in a range between 0.6 and 1.4 or in a range between 0.8 and 1.2.

(14) At least three first highly doped semiconductor contact regions HG11, HG12, HG13, spaced a distance apart, are formed on top surface OF, and at least three second highly doped semiconductor contact regions HG21, HG22, HG23, spaced a distance apart and each having a second conductivity type, are formed on lower surface UF. Only two of the three first highly doped semiconductor contact regions HG11, HG12 and only two of the three second highly doped semiconductor contact regions HG21, HG22 on lower surface UF are illustrated in the cross-sectional view.

(15) Each highly doped first semiconductor contact region HG11, HG12, HG13 is connected with the aid of an assigned first terminal contact K11, K12, K13, and each highly doped second semiconductor contact region HG21, HG22, HG23 is connected with the aid of an assigned second terminal contact K21, K22, K23.

(16) Each of second terminal contacts K21, K22, K23 preferably comprises a highly doped polysilicon of a second conductivity type or a metal.

(17) First semiconductor contact regions HG11, HG12, HG13 are disposed offset from second semiconductor contact regions HG21, HG22, HG23 in a projection perpendicular to top surface OF.

(18) First semiconductor contact regions HG11, HG12, HG13 and second semiconductor contact regions HG21, HG22, HG23 each have a multiple rotational symmetry with respect to an axis of symmetry viewed perpendicularly on top surface OF and on lower surface UF of semiconductor body HLK.

(19) Semiconductor body HLK and semiconductor layer HALS have an identical lateral extension.

(20) Integrated circuit IS is in an electrical operative connection with Hall sensor structure HSENS, the design of the operative connection not being illustrated.

(21) The illustration in FIG. 2 shows a cross-sectional view of a second specific embodiment having a sensor region HSENS. Only the differences from the illustration in FIG. 1 are explained below.

(22) Semiconductor layer HALS comprises an oxide layer SOI formed continuously between front side VS1 and back side RS1.

(23) The integrated circuit includes a plurality of vertical insulation trenches TR1. Insulation trenches TR1 extend from front side VS up to continuous oxide layer SOI.

(24) The illustration in FIG. 3 shows a top view of a top surface OF of the sensor region illustrated in FIG. 1 or FIG. 2. Only the differences from the preceding illustrations are explained below.

(25) Semiconductor body HLK and thus also sensor region HSENS are separated from the other regions of the semiconductor layer of semiconductor body HLK with the aid of circumferential trench structure TR. In the present case, sensor region HSENS has a hexagonal cross section. First semiconductor contact regions HG11, HG12 and HG13 and second semiconductor contact regions HG21, HG22 and HG23 are disposed near trench structure TR and preferably in the corners of the hexagonal structure.

(26) It should be noted that the cross section of sensor region HSENS is also provided with a square design or is designed in the shape of a polygon in other specific embodiments.

(27) Second semiconductor contact regions HG21, HG22 and HG23—drawn with a dashed line—have a multiple, in particular a ternary, symmetry with regard to an axis of symmetry SA.

(28) First semiconductor contact regions HG11, HG12 and HG13 are formed on upper side OS and also have a multiple, in particular a ternary, symmetry with regard to axis of symmetry SA.

(29) First semiconductor contact regions HG11, HG12 and HG13 on upper side OS are disposed, offset from second semiconductor contact regions HG21, HG22 and HG23, on buried lower surface US.

(30) The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.