Systems And Methods For Automotive Synthetic Aperture Radar

Abstract

Embodiments are disclosed that for synthetic aperture radar (SAR) systems and methods. Front-end circuitry transmits radar signals, receives return radar signals, and outputs digital radar data. FFT circuits process the digital radar data without zero-padding to generate FFT data corresponding to oversampled pixel range values. A processor further processes the FFT data to generate radar pixel data representing a radar image. Further, the FFT circuits can interpolate the FFT data based upon pixel ranges using a streamlined range computation process. This process pre-computes x-axis components for pixels in common rows and y-axis components for pixels in common columns within the FFT data. For one embodiment, a navigation processor is coupled to a SAR system within a vehicle, receives the radar pixel data, and causes one or more actions to occur based upon the radar pixel data, such as an advanced driver assistance system function or an autonomous driving function.

Claims

1. A radar system, comprising: front-end circuitry coupled to transmit radar signals, to receive return radar signals, and to output digital radar data; FFT circuits coupled to receive the digital radar data and to output FFT data corresponding to oversampled pixel range values, the FFT circuits being configured to apply FFT processes without zero-padding; and a processor coupled to receive the FFT data and to output radar pixel data representing a radar image.

2. The radar system of claim 1, further comprising a navigation processor coupled to receive the radar pixel data and to cause one or more actions to occur based upon the radar pixel data; and wherein the front-end circuitry, the FFT circuits, the processor, and the navigation processor are coupled within a vehicle.

3. The radar system of claim 2, wherein the one or more actions comprises at least one of an advanced driver assistance system function or an autonomous driving function.

4. The radar system of claim 1, wherein the FFT circuits are configured to output interpolated FFT data based upon pixel ranges.

5. The radar system of claim 4, wherein the FFT circuits are configured to perform K/N instances of N-sample FFT operations to generate the interpolated FFT data; and wherein K, N, and K/N are integers and K>N.

6. The radar system of claim 4, wherein the FFT data represents x-axis data and y-axis data for pixels within the radar image, and wherein the FFT circuits are configured to pre-compute x-axis components for pixels in common rows and y-axis components for pixels in common columns.

7. The radar system of claim 6, wherein the FFT circuits comprise a plurality of hardware cores configured to process the FFT data in parallel to output the interpolated FFT data.

8. The radar system of claim 1, wherein the front-end circuitry comprises antennas configured to transmit radar chirp signals and to receive return radar signals and digital-to-analog converter circuitry configured to convert the return radar signals to the digital radar data.

9. A circuit assembly, comprising FFT circuits coupled to receive the digital radar data and to output FFT data corresponding to oversampled pixel range values, the FFT circuits being configured to apply FFT processes without zero-padding; and a processor coupled to receive the FFT data and to output radar pixel data representing a radar image.

10. The circuit assembly of claim 9, wherein the FFT circuits comprise a plurality of application specific integrated circuits.

11. The circuit assembly of claim 9, wherein the FFT circuits are configured to output interpolated FFT data based upon pixel ranges.

12. The circuit assembly of claim 11, wherein the FFT circuits are configured to perform K/N instances of N-sample FFT operations to generate the interpolated FFT data; and wherein K, N, and K/N are integers and K>N.

13. The circuit assembly of claim 11, wherein the FFT data represents x-axis data and y-axis data for pixels within the radar image, and wherein the FFT circuits are configured to pre-compute x-axis components for pixels in common rows and y-axis components for pixels in common columns.

14. A method to generate a radar image, comprising: transmitting radar signals; receiving return radar signals; converting the return radar signals to digital radar data; processing, with FFT circuits, the digital radar data by applying FFT processes without zero-padding to output FFT data corresponding to oversampled pixel range values; and outputting radar pixel data representing a radar image based upon the FFT data.

15. The method of claim 14, further comprising performing the transmitting, receiving, converting, processing, and outputting within a vehicle, and further comprising causing one or more actions to occur based upon the radar pixel data.

16. The method of claim 15, wherein the one or more actions comprises at least one of an advanced driver assistance system function or an autonomous driving function.

17. The method of claim 14, further comprising interpolating the FFT data based upon pixel ranges to generate interpolated FFT data prior to the outputting.

18. The method of claim 17, wherein the processing performs K/N instances of N-sample FFT operations to generate the interpolated FFT data; and wherein K, N, and K/N are integers and K>N.

19. The method of claim 17, wherein the FFT data represents x-axis data and y-axis data for pixels within the radar image, and further comprising pre-computing x-axis components for pixels in common rows and y-axis components for pixels in common columns for the interpolating.

20. The method of claim 19, further comprising performing the interpolating in parallel with a plurality of hardware cores.

Description

DESCRIPTION OF THE DRAWINGS

[0007] It is noted that the appended figures illustrate only example embodiments and are, therefore, not to be considered as limiting the scope of the present invention. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

[0008] FIG. 1 is a block diagram of an example embodiment for a vehicle including a synthetic aperture radar (SAR) system that implements one or more of the techniques described herein.

[0009] FIG. 2 provides an example embodiment for the SAR system and processing implemented by the SAR system.

[0010] FIG. 3 provides an example embodiment for the high-performance and high-efficiency oversampled FFT processes performed by FFT circuits without using zero-padding.

[0011] FIG. 4 provides an example embodiment where a streamlined range computation process is used to determine a range for each pixel within the radar pixel image being generated.

DETAILED DESCRIPTION

[0012] Systems and methods are disclosed for synthetic aperture radar (SAR). Within the SAR system, FFT circuits receive digital radar data and output FFT data corresponding to oversampled pixel range values, and the FFT circuits apply FFT processes without zero-padding. Further, the FFT circuits can interpolate the FFT data based upon pixel ranges using a streamlined range computation process. This process pre-computes x-axis components for pixels in common rows and y-axis components for pixels in common columns within the FFT data. A variety of embodiments can be implemented and different features and variations can be implemented while still taking advantage of the techniques described herein.

[0013] As described above, the formation of SAR images typically requires that the relative motion between each antenna and any hypothesized point target, on which a pixel is to be constructed, to be precisely known. From this hypothesized range and range rate information, radar data across multiple frames is combined. If a target is indeed present at a hypothesized pixel position and has motion that matches the assumed motion, the energy of the echoes or returns radar signals for this target will add up coherently. On the other hand, if a target is not present at the pixel under test or has motion that does not match the assumed motion, only noise is added up in a non-coherent fashion. As such, over a number (X) of integrations, the signal-to-noise power ratio (SNR) will be enhanced by up to a factor of X, and an image is formed for the target that is indeed present. However, adequate resolution with FFT computations is achieved in prior solutions by zero-padding the original samples by four-times or eight-times or more. Unfortunately, these prior SAR solutions are computationally intensive and impractical for low-cost automotive radar applications.

[0014] The disclosed embodiments implement SAR processing in an efficient manner making SAR solutions viable for a wider range of applications including low-cost solutions. The disclosed embodiments in part leverage algorithmic enhancements as well as efficient system-on-chip (SoC) hardware accelerators to make SAR processing practical for a wider range of applications and open a new class of applications for automotive systems based on SAR imaging. For example, SAR techniques can now efficiently be applied to detailed environment mapping, parking assist, parking and autopilot, target classifications, advanced driver assistance system (ADAS) and autonomous driving (AD) functions, or other functions or applications that can take advantage of the SAR systems described herein.

[0015] As described further below, the disclosed embodiments significantly reduce the processing load of conventional back projection (BP) SAR processing and improve the quality of formed images. In one aspect of the disclosed embodiments, a high-performance and high-efficiency interpolation approach replaces the conventional zero-padding FFT interpolators as well as interpolators such as linear interpolators, periodic Sinc interpolators, and the DFT interpolators. The improved interpolator techniques described herein can also be implemented using existing ASIC FFT accelerators without enlarging the maximum vector size requirement. In another aspect of the disclosed embodiments, the computation of hypothesized ranges to the pixels under test is streamlined to achieve a much higher computational efficiency without any degradation in the performance. This streamlined range computation can also be implemented with parallel computing hardware cores to achieve high frame throughput. For example, parallel computing can be implemented using vector processors, single-instruction multiple data (SIMD) processors, multiple-instruction multiple data (MIMD) processors, general-purpose graphic processing units (GPGPUs), multi-core central processing units (CPUs), or other hardware processors or combinations of processors. The disclosed embodiments achieve SAR processing with improved performance and higher efficiency as compared to prior solutions. As such, the disclosed embodiments are useful in a wide range of applications and make SAR processing viable for low-cost automotive radar systems and applications.

[0016] FIG. 1 is a block diagram of an example embodiment 100 for a vehicle 130 including a SAR system 105 that implements one or more of the techniques described herein. For the example embodiment 100, the vehicle 130 is assumed to be moving in a one direction, as represented by arrow 124, and the imaging provided by the SAR system 105 is directed to one side of the vehicle 130. Multiple SAR systems 105 can also be included on the vehicle 120 to provide imaging for multiple different sides of the vehicle 130. The SAR system 105 includes front-end circuitry 102 that transmits radar signals 122, such as chirps, and captures return radar signals 123 that are reflected by an object 125. The front-end circuitry 102 preferably includes multiple antennas that transmit chirps and receive return signals as the vehicle 130 moves, and these antennas can be dedicated exclusively to transmit operations or receive operations in some solutions. The front-end circuitry 102 also includes mixing and analog-to-digital converter (ADC) circuitry to convert the return radar signals 123 into digital radar data that is sent to FFT circuits 104. These FFT circuits 104 can be, for example, ASICs that are programmed to implement the FFT interpolator functions described herein. The interpolated FFT data output by the FFT circuits 104 is received by the processor 106, and the processor 106 further processes the FFT output data to generate a radar pixel image 109 that is output by the SAR system 105. The memory 108 stores data for the FFT circuits 104 and the processor 106 including the final radar pixel image 109. For one embodiment, the radar pixel image 109 is output by the SAR system 105 to a navigation processor 110, which in turn outputs control signals for autonomous driving of the vehicle 130. For example, the navigation processor 110 can output these control signals to vehicle control systems 114, such as a steering system, an acceleration system, a braking system, or other control system or combination of control systems. For one embodiment, the navigation processor 110 outputs vision-based assistance images to a passenger or driver of the vehicle 130 through a display 112.

[0017] It is noted that one or more components of the SAR system 105 including the FFT circuits 104 and the processor 106 can be implemented using one or more application specific integrated circuits (ASICs), microcontrollers, microprocessors, programmable logic devices, or other programmable circuits that execute hardware instructions or program instructions stored in one or more non-volatile data storage mediums to carry out the functions described herein. In addition, the SAR system 105 can be implemented in whole or in part as a system-on-chip (SoC) integrated circuit. Further, the memory 108 and other memories used by the SAR system 105 can be implemented as one or more data storage mediums configured to store the data described herein. Other variations can also be implemented while still taking advantage of the adaptive sub-tile techniques described herein.

[0018] FIG. 2 provides an example embodiment for the SAR system 105 and processing implemented using the FFT circuits 104, the processor 106, and the memory 108. As described above, the front-end circuitry 102 sends digital radar data 202 to FFT circuits 104. As shown in more details in FIG. 2, this digital radar data 202 can be stored within memory 108. For one embodiment, the digital radar data 202 is ADC cube data that represents multiple time samples of data collected over time for multiple antennas within the front-end circuitry 102. For example, the ADC cube data can represent a three-dimensional matrix of multiple chirps by multiple antennas by multiple samples over time. The FFT circuits 104 process the digital radar data 202 and generates FFT data 204, which can also be stored in memory 108. As described further below, the FFT circuits 104 implement FFT processes 210 that provide improved efficiency and performance. For one embodiment, the FFT data 204 is range cube data that represents oversampled range cells of FFT data representing pixels for a radar image. For example, the range cube data can represent a three-dimensional matrix of oversampled range cells of FFT data by multiple chirps by multiple antennas. The FFT circuits 104 also processes the FFT data 204 to generate interpolated FFT data 206. As described further below, the FFT circuits 104 can implement a streamlined range computation process 220 to facilitate pixel range determinations. For one embodiment, the interpolated FFT data 206 represents interpolated range cell data that represents an interpolation of multiple data elements from the FFT data 204 to form each cell of the range cell data. The processor 106 then processes the interpolated FFT data 206 to apply phase compensation and coherent integration and to generate the radar pixel image 109, which can also be stored in memory 108. The radar pixel data 109 is output for further use or processing, for example, by a navigation processor 110 as described above. The radar pixel data 109 represents a radar image captured by the SAR system 105. It is noted that memory 108 can be implemented as a single memory or as multiple different memories or registers that store the data being processed and generated by the SAR system 105. Other variations can also be implemented.

[0019] In operation, the SAR system 105 implements efficient radar image processing as described further below with respect to FIGS. 3-4. For example, as described with respect to FIG. 3, the SAR system 105 can implement a high-performance and high-efficiency FFT computation and interpolation processes that replaces conventional FFT interpolators. As described with respect to FIG. 4, the SAR system 105 can implement a streamlined range computation for image pixels. Other SAR processing can also be implemented while still taking advantage of the techniques described herein.

[0020] Looking now to FIG. 3, an example embodiment is provided for the high-performance and high-efficiency oversampled FFT processes 210 performed by FFT circuits 104. In block 302, weights are applied to the signal samples from the ADC cube data 202 to generate weighted samples 312. In block, 304, a modulation application is applied to the weighted samples 312 to generate modulated samples 314. In block 306, a length-N FFT computation is applied to the modulated samples 314 to generate oversampled FFT data 204. As described further below, the length-N FFT computation does not use zero-padding and thereby reduces size and computation requirements. In block 308, the oversampled FFT data 204 is interpolated to generate interpolated FFT data 206, which is output to the processor 106 for further processing as described above.

[0021] In operation, the example embodiment of FIG. 3 provides an efficient implementation of an oversampled FFT nearest-cell interpolator. In practice, the sufficiently (e.g., ×4, ×8) oversampled FFT implementation results in negligible quantization error, and the performance is comparable to that of the ideal DFT interpolator or a full-sample periodic Sinc interpolator. In contrast with conventional oversampling FFT solutions that require zero-padding such that the length of FFT is prolonged, the embodiment of FIG. 3 provides an alternative implementation that does not use zero-padding for the length-N FFT computation in block 306.

[0022] The alternative SAR processing and efficient FFT interpolators described herein are based on the following formulations. For the case of weighted oversampled FFT of {x.sub.n} that evaluates the following DFT expression:

[00001]$Y_k=\underset{n=0}{\overset{N-1}{.Math.}}{w}_n{x}_n{e}^{-j\gamma kn}$

where Y.sub.k represents the FFT interpolated data; n=0, 1, . . . , N−1; k=0, 1, . . . , K−1; γ=2π/K; w.sub.n represents a weight value; and x.sub.n represents a sample value.

[0023] When K/N is an integer, the above equation can be evaluated by computing K/N instances of an N-point FFT operation and by combining their outputs thereby reducing the complexity from O(K log K) to O(K log N) and reducing the required FFT length from K to N. Further, denoting

[00002]$\eta =\mathrm{rem}\left(k,\frac{K}{N}\right)$

where η=0,1, . . . , K/N−1, for a given k and η:

[00003]$Y_{k|r\mathrm{em}\left(k,\frac{K}{N}\right)=\eta }=\underset{n=0}{\overset{N-1}{.Math.}}{w}_n{x}_n{e}^{-j\frac{2\pi }{N}\frac{k}{\left(\frac{K}{N}\right)}n}=\underset{n=0}{\overset{N-1}{.Math.}}\left(w_n{e}^{-j\gamma n\eta }\right)x_n{e}^{-j\frac{2\pi \left(k-\eta \right)}{K}n}$

where e.sup.−jγnη is the modulation term; Y.sub.k represents the FFT interpolated data; η represents the remainder of k divided by K/N; n=0, 1, . . . , N−1; k=0, 1, . . . , K−1; γ=2π/K; w.sub.n represents a weight value; x.sub.n represents a sample value; and K, N, and K/N are integers with K>N. In general, K/N instances are needed for FFT computations for all K output samples of Y.sub.k. For an example of K/N=4 (such that η=0,1,2,3), the 4 instances of the N-point DFT are:

[00004]$Y_k=\stackrel{N-1}{\underset{n=0}{.Math.}}{w}_n{x}_n{e}^{-j\frac{2\pi }{N}\frac{k}{4}n}=\{\begin{array}{cc}\stackrel{N-1}{\underset{n=0}{.Math.}}{w}_n{x}_n{e}^{-j\frac{2\pi }{N}\frac{k}{4}n}& \mathrm{for}\mathrm{rem}\left(k,\frac{K}{N}\right)=0\\ \stackrel{N-1}{\underset{n=0}{.Math.}}\left(w_n{e}^{-j\frac{2\pi }{4N}n}\right)x_n{e}^{-j\frac{2\pi }{N}\frac{k-1}{4}n}& \mathrm{for}\mathrm{rem}\left(k,\frac{K}{N}\right)=1\\ \stackrel{N-1}{\underset{n=0}{.Math.}}\left(w_n{e}^{-j\frac{4\pi }{4N}n}\right)x_n{e}^{-j\frac{2\pi }{N}\frac{k-2}{4}n}& \mathrm{for}\mathrm{rem}\left(k,\frac{K}{N}\right)=2\\ \stackrel{N-1}{\underset{n=0}{.Math.}}\left(w_n{e}^{-j\frac{6\pi }{4N}n}\right)x_n{e}^{-j\frac{2\pi }{N}\frac{k-3}{4}n}& \mathrm{for}\mathrm{rem}\left(k,\frac{K}{N}\right)=3\end{array}$

where each instance is evaluated using an N-point FFT. Further, it is noted that rem

[00005]$\left(k,\frac{K}{N}\right)$

represents the remainder (rem) of k divided by K/N.

[0024] The above formulas show the output (Y) of the process can be implemented using multiple shorter (i.e., fewer number of samples) DFT operations. More specifically, looking at the N elements of the output Y: Y[1], Y[2], . . . Y[K], the elements with indices k such that rem(k,K/N)=0 will form a group. The indices k such that rem(k,K/N)=1 will form another group, and so on. This continues to form a total K/N groups. Each of these K/N groups is computed using the DFT formula with the N-sample (x) as an input. Although the formula above is written using a DFT expression, it is recognized that FFT is simply a faster implementation of DFT, and it is understood that this DFT expression can be implemented using FFT operations. As such, the above process leads to K/N instances of N-sample FFT operations.

[0025] Looking back to FIGS. 2-3, the processing of the FFT processes 210 provide efficient oversampled FFT operation for a SAR system 105. Given N input samples within data 202, the complex weighting provided in block 302 can have a complexity of O{N}. The K/N-times oversampled FFT operation (K/N instances of length-N FFT) in block 306 has a complexity of O{K+K log N}. The subsequent nearest-cell interpolation and quantization in block 308 has a complexity of O{M}. The computing of the normalized range value (ω.sub.m) for each pixel has a complexity of O{4} or O{4M} for M pixels. The normalized range value (ω.sub.m) of the m-th pixel can be calculated as:

ω.sub.m=k.sub.m_to_Hz√{square root over ((x.sub.pixel−x.sub.radar).sup.2+(y.sub.pixel−y.sub.radar).sup.2)}

where k.sub.m_to_Hz is a scaling constant converting meters to Hz according to the chirp de-ramp mixing effect; [x.sub.pixel,y.sub.pixel] are the pixel's x and y positions relative to a global frame of reference; and [x.sub.radar,y.sub.radar] are the antenna's x and y positions relative to a global frame of reference. For the above equation, it is assumed that the transmit and receive antennas are co-located, and this expression can be extended to cases where the transmit and receive antennas are not co-located.

[0026] Finally, phase compensation can have a complexity of O{M}. As a result, the total complexity amounts to O{N+K+K log N+5M}. It can be seen that if K(1+log N)<NM the efficient oversampled FFT approach described herein is more efficient than a traditional DFT-based approach. It can also be seen if K log N+K<K log K+M, the efficient oversampled FFT approach described herein is more efficient than a conventional oversampled FFT SAR approach where K samples are used. Because K is multiple times larger than N by definition and where M (e.g., number of pixel, a 200×200 image results in M=40,000) is usually much larger than K, the efficient oversampled FFT approach described herein is almost always more efficient.

[0027] In addition to the algorithmic improvement of the oversampled FFT processing provided by the FFT circuits 104, the FFT circuits 104 can be carried out in one or more ASIC-based N-point FFT accelerators. In contrast to the N-point FFT solution in FIG. 3, conventional implementation requires a K-point FFT that is many times larger than the N-point FFT technique describe herein. The relaxed requirement on FFT size makes the disclosed embodiments practical for a wide range of solutions.

[0028] In addition to FFT computations, one main contributor to the computational complexity of prior SAR solutions is the calculation of pixel ranges. For example, when the number of pixels increases in a SAR solution, the pixel range calculations become a dominant factor increasing complexity in the computational requirements. In addition to reducing the complexity through the efficient oversampled FFT processes described in FIG. 3, complexity of the pixel range calculations can also be reduced using the technique described below.

[0029] Looking now to FIG. 4, an example embodiment 400 is provided where streamlined range computation process 220 is used to determine a range 406 for each pixel 404 within the radar pixel image 109 being generated. The radar pixel image 109 is shown with respect to an x-axis 408 and a y-axis 410. The vehicle 130, which is moving, encounters an object 125 within a scene being detected by the SAR system 105. As described above, radar signals 122, such as chirps, are transmitted by the SAR system 105, and return radar signals 123 reflected by an object 125 are received by the SAR system 105. The SAR system 105 processes the return radar signals 123 to generate a radar pixel image 109 representing the scene being detected including object 125. The radar pixel image 109 includes an array of pixels 404, and a range 406 is determined for each pixel 404. The range 406 represents the hypothetical range from the vehicle 130 to a portion of reflecting object 125 represented by pixel 404. The range 406 for each pixel is determined using the range computation process 220. As described below, the range computation process 220 uses pre-computed x-axis components 412, pre-computed y-axis components 414, or both to achieve reduced computational complexity in determining the range for each pixel 404. These pre-computed x-axis and y-axis components 412/414 can be stored, for example, in the memory 108 or in another memory used by the SAR system 105.

[0030] Initially, upon the examination of the following simplistic range equation, it can be concluded that the complexity of the standard computation is O{3M.sub.xM.sub.y} for an SAR image consisting of M.sub.x horizontal positions and M.sub.y vertical positions.

pixel range=√{square root over ((x.sub.m.sub.x−X).sup.2+(y.sub.m.sub.y−Y).sup.2)}; (m.sub.x=0: M.sub.x−1, y.sub.x=0: M.sub.y−1)

Looking again to FIG. 4, a geometric relationship exists between the pixel image 109 and the radar antennas within the SAR system 105. As an example, if the pixel image 109 is M.sub.x pixels by M.sub.y pixels and if M.sub.x=200 and M.sub.y=200, then the conventional range computation results in complexity of O{3M.sub.xM.sub.y}=120,000.

[0031] Upon a closer examination, it is noted for the disclosed embodiments that, if the imaged area is arranged in a rectangular grid fashion, the y-axis components (i.e., (y.sub.m.sub.y−Y).sup.2) in the square root of the range equation of a row are identical for all pixels on the same row. Likewise, the x-axis components (i.e., (x.sub.m.sub.x−X).sup.2) in the square root of the range equation of a column are identical for all pixels on the same column. As a result, savings can be achieved by pre-calculating the x-axis components and storing them as x-axis components 412, pre-calculating the y-axis components and storing them as y-axis components 414, or both. The x-axis components 412 can be pre-calculated by computing the values for: (x.sub.m.sub.x−X).sup.2 for each x value from m.sub.x=0 to M.sub.x−1. The y-axis components 414 can be pre-calculated by computing the values for: (y.sub.m.sub.y−Y).sup.2 for each y value from m.sub.y=0 to M.sub.y−1. These pre-calculated x-axis and y-axis components 412/414 can then be re-used in pixel range calculations for pixels within the same column or the same row thereby reducing computational complexity. As a result, the complexity is reduced to O{M.sub.xM.sub.y+(M.sub.x+M.sub.y)} for all pixels. Comparing to the prior example of M.sub.x=200 and M.sub.y=200, the complexity is reduced to 40400 from the original 120000. The saving becomes more and more significant with increasing values of M.sub.x and M.sub.y.

[0032] In addition to the algorithmic enhancement of the pixel range determinations, the implementation of FIG. 4 can be further enhanced by applying parallel computing hardware resources. For example, the range computations can be parallelized by sending multiple x.sub.m.sub.x values of a row to multiple hardware cores or components, such as ALUs (Arithmetic Logic Units) of a computing core, and loading each ALU with constant values of −X and (y.sub.m.sub.y−Y).sup.2. Sequential instructions can then be performed that first perform an addition operation to compute “x.sub.m.sub.x−X”, then perform a square operation to compute “(x.sub.m.sub.x−X).sup.2”, then perform another addition operation to compute “(x.sub.m.sub.x−X).sup.2+(y.sub.m.sub.y−Y).sup.2”, and finally perform a square root operation to compute the pixel range value “√{square root over ((x.sub.m.sub.x−X).sup.2+(y.sub.m.sub.y−Y).sup.2)}”.

[0033] It is noted that the radar position for the SAR system 105 is assumed to be changing at each chirp start due to the movement of the vehicle 130. As such, the pixel range computation is performed for each chirp. Because the processing is performed on a chirp-by-chirp basis, the movement of SAR system 105 does not need to be constant for the SAR processing to work. The radar position information is assumed to be estimated by a position sensor, such as a GPS-IMU sensor, and this position information is provided to the SAR system 105. Because the instruction and loaded constant values are identical to each of the multiple x.sub.m.sub.x values fed to the vector of the ALUs, multiple pixel ranges can be computed within the same number of cycles that is required to compute a single pixel in a sequential fashion. For example, by utilizing a SIMD (single instruction multiple data) processor or vector processor, the computation throughput can be greatly increased. Likewise, the parallelization can also be carried out by other kinds of parallel computing resources such as a MIMD (multiple instruction multiple data) processor, a general-purpose graphic processing unit (GP-GPU), a multiple-core CPU, or other hardware cores.

[0034] It is further noted that combining the pixel range determination processes of FIG. 4 with the oversampled FFT processes of FIG. 3 provides further efficiency advantages and reduction in complexity. With the efficient oversampling FFT of FIG. 3, the order of complexity is reduced to O{N+K+K log.sub.2 (N)+5M} not including the reduction in the pixel range computation. By replacing the conventional pixel range computation approach with the optimized pixel range computation of FIG. 3, the complexity is further reduced to O{N+K+K log.sub.2 (N)+(M.sub.x+M.sub.y)+3M}. As such, the combination provides a high efficiency and high performance solution for a SAR system that is practical for a wide range of applications including automotive radar systems and applications. Further, as described above, the SAR images can be displayed to a driver or can be sent to further automotive processing units to support autonomous self-driving functions or other advanced driver assistance functions.

[0035] As described herein, a variety of embodiments can be implemented and different features and variations can be implemented, as desired.

[0036] For one embodiment, a radar system is disclosed including front-end circuitry, FFT circuits, and a processor. The front-end circuitry is coupled to transmit radar signals, to receive return radar signals, and to output digital radar data. The FFT circuits coupled to receive the digital radar data and to output FFT data corresponding to oversampled pixel range values, and the FFT circuits are configured to apply FFT processes without zero-padding. A processor coupled to receive the FFT data and to output radar pixel data representing a radar image.

[0037] In additional embodiments, the radar system also includes a navigation processor coupled to receive the radar pixel data and to cause one or more actions to occur based upon the radar pixel data; and the front-end circuitry, the FFT circuits, the processor, and the navigation processor are coupled within a vehicle. In further embodiments, the one or more actions include at least one of an advanced driver assistance system function or an autonomous driving function.

[0038] In additional embodiments, the FFT circuits are configured to output interpolated FFT data based upon pixel ranges. In further embodiments, the FFT circuits are configured to perform K/N instances of N-sample FFT operations to generate the interpolated FFT data where K, N, and K/N are integers and K>N. In further embodiments, the FFT data represents x-axis data and y-axis data for pixels within the radar image, and the FFT circuits are configured to pre-compute x-axis components for pixels in common rows and y-axis components for pixels in common columns. In still further embodiments, the FFT circuits include a plurality of hardware cores configured to process the FFT data in parallel to output the interpolated FFT data.

[0039] In additional embodiments, the front-end circuitry includes antennas configured to transmit radar chirp signals and to receive return radar signals and digital-to-analog converter circuitry configured to convert the return radar signals to the digital radar data.

[0040] For one embodiment, a circuit assembly is disclosed including FFT circuits and a processor. The FFT circuits are coupled to receive the digital radar data and to output FFT data corresponding to oversampled pixel range values, the FFT circuits being configured to apply FFT processes without zero-padding. The processor is coupled to receive the FFT data and to output radar pixel data representing a radar image.

[0041] In additional embodiments, the FFT circuits include a plurality of application specific integrated circuits. In further additional embodiments, the FFT circuits are configured to output interpolated FFT data based upon pixel ranges. In further embodiments, the FFT circuits are configured to perform K/N instances of N-sample FFT operations to generate the interpolated FFT data where K, N, and K/N are integers and K>N. In further embodiments, the FFT data represents x-axis data and y-axis data for pixels within the radar image, and the FFT circuits are configured to pre-compute x-axis components for pixels in common rows and y-axis components for pixels in common columns.

[0042] For one embodiment, a method to generate a radar image is disclosed including transmitting radar signals, receiving return radar signals, converting the return radar signals to digital radar data, processing the digital radar data with FFT circuits by applying FFT processes without zero-padding to output FFT data corresponding to oversampled pixel range values, and outputting radar pixel data representing a radar image based upon the FFT data.

[0043] In additional embodiments, the method includes performing the transmitting, receiving, converting, processing, and outputting within a vehicle, and further includes causing one or more actions to occur based upon the radar pixel data. In further embodiments, the one or more actions includes at least one of an advanced driver assistance system function or an autonomous driving function.

[0044] In additional embodiments, the method includes interpolating the FFT data based upon pixel ranges to generate interpolated FFT data prior to the outputting. In further embodiments, the processing performs K/N instances of N-sample FFT operations to generate the interpolated FFT data where K, N, and K/N are integers and K>N. In further embodiments, the FFT data represents x-axis data and y-axis data for pixels within the radar image, and the method includes pre-computing x-axis components for pixels in common rows and y-axis components for pixels in common columns for the interpolating. In still further embodiments, the method includes performing the interpolating in parallel with a plurality of hardware cores.

[0045] It is further noted that the functional blocks, components, systems, devices, or circuitry described herein can be implemented using hardware, software, or a combination of hardware and software along with analog circuitry as needed. For example, the disclosed embodiments can be implemented using one or more integrated circuits that are programmed to perform the functions, tasks, methods, actions, or other operational features described herein for the disclosed embodiments. The one or more integrated circuits can include, for example, one or more processors or configurable logic devices (CLDs) or a combination thereof. The one or more processors can be, for example, one or more central processing units (CPUs), control circuits, microcontroller, microprocessors, hardware accelerators, ASIC s (application specific integrated circuit), or other integrated processing devices. The one or more CLDs can be, for example, one or more CPLDs (complex programmable logic devices), FPGAs (field programmable gate arrays), PLAs (programmable logic array), reconfigurable logic circuits, or other integrated logic devices. Further, the integrated circuits, including the one or more processors, can be programmed to execute software, firmware, code, or other program instructions that are embodied in one or more non-transitory tangible computer-readable mediums to perform the functions, tasks, methods, actions, or other operational features described herein for the disclosed embodiments. The integrated circuits, including the one or more CLDs, can also be programmed using logic code, logic definitions, hardware description languages, configuration files, or other logic instructions that are embodied in one or more non-transitory tangible computer-readable mediums to perform the functions, tasks, methods, actions, or other operational features described herein for the disclosed embodiments. In addition, the one or more non-transitory tangible computer-readable mediums can include, for example, one or more data storage devices, memory devices, flash memories, random access memories, read only memories, programmable memory devices, reprogrammable storage devices, hard drives, floppy disks, DVDs, CD-ROMs, or any other non-transitory tangible computer-readable mediums. Other variations can also be implemented while still taking advantage of the techniques described herein.

[0046] Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

[0047] Further modifications and alternative embodiments of the described systems and methods will be apparent to those skilled in the art in view of this description. It will be recognized, therefore, that the described systems and methods are not limited by these example arrangements. It is to be understood that the forms of the systems and methods herein shown and described are to be taken as example embodiments. Various changes may be made in the implementations. Thus, although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and such modifications are intended to be included within the scope of the present invention. Further, any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.