Inverting circuit

Abstract

An inverter includes a semiconductor substrate. A Z2-FET switch is disposed at a first surface of the semiconductor substrate and a further switch is disposed at the first surface of the semiconductor substrate. The further switch and the Z2-FET switch have current paths coupled between a first reference terminal and a second reference terminal.

Claims

1. An inverter comprising: a semiconductor substrate; a Z.sup.2-FET switch disposed at a first surface of the semiconductor substrate, wherein the Z.sup.2-FET comprises a first anode, a first cathode, a first front gate, a first back gate, and a second back gate; and a further switch disposed at the first surface of the semiconductor substrate, wherein the further switch comprises a second anode, a second cathode, a second front gate, a third back gate, and a fourth back gate, wherein the first back gate and the third back gate are coupled to a first reference potential and the second back gate and the fourth back gate are coupled to a second reference potential, the further switch having a current path between the anode and the cathode of the further switch coupled in series with a current path between the anode and the cathode of the Z.sup.2-FET switch between a first reference terminal and a second reference terminal.

2. The inverter of claim 1, wherein the first gate is coupled to an inverter input terminal.

3. The inverter of claim 1, wherein the Z.sup.2-FET switch is of type N.

4. The inverter of claim 1, wherein the Z.sup.2-FET switch is of type P.

5. The inverter of claim 1, wherein the further switch comprises a second Z.sup.2-FET switch.

6. The inverter of claim 5, wherein the Z.sup.2-FET switch is an N-type Z.sup.2-FET switch and wherein the further switch is a P-type Z.sup.2-FET switch.

7. The inverter of claim 6, wherein the anode of the Z.sup.2-FET switch is coupled to the first reference terminal and the cathode of the Z.sup.2-FET switch is coupled to an inverter output terminal, and wherein the anode of the further switch is coupled to the inverter output terminal and the cathode of the further switch is coupled to the second reference terminal.

8. The inverter of claim 7, wherein the first reference terminal is a power supply terminal.

9. The inverter of claim 7, wherein the second reference terminal is a reference terminal.

10. The inverter of claim 9, wherein the reference terminal is ground.

11. The inverter of claim 1, wherein the first front gate and the second front gate are positioned on an upper surface of the semiconductor substrate and wherein the first back gate, the second back gate, the third back gate, and the fourth back gate are positioned on a lower surface of the semiconductor substrate, the lower surface opposite the upper surface.

12. The inverter of claim 1, wherein each second gate comprises an N-type doped portion and a P-type doped portion.

13. The inverter of claim 12, wherein, for the Z.sup.2-FET switch and the further switch, the P-type doped portion is coupled to a positive potential and the N-type doped portion is coupled to a negative potential.

14. The inverter of claim 1, wherein the Z.sup.2-FET switch comprises: an anode region forming the anode disposed within the semiconductor substrate; a cathode region forming the cathode disposed within the semiconductor substrate; a P-type doped region separating the anode region from the cathode region; and an insulated gate region positioned on top of and in contact with a portion of the P-type doped region.

15. An inverter comprising: an N-type Z.sup.2-FET switch having a cathode coupled to an inverter output terminal, an anode coupled to a positive reference terminal, a top gate coupled to an inverter input terminal, and a back gate having a P-type doped portion coupled to a positive potential and an N-type doped portion coupled to a negative potential; and a P-type Z.sup.2-FET switch having a cathode connected to the cathode of the N-type Z.sup.2-FET switch and the inverter output terminal, an anode coupled to a negative reference terminal, a top gate coupled to the inverter input terminal, and a back gate having a P-type doped portion coupled to the positive potential and the N-type doped portion coupled to a negative potential.

16. An inverter comprising: a silicon on insulator substrate having a semiconductor layer overlying an insulating layer that overlies a semiconductor substrate; a first Z.sup.2-FET switch having an anode region disposed in the semiconductor layer, a cathode region disposed in the semiconductor layer, a P-type doped region disposed in the semiconductor layer between the anode region and the cathode region, an insulated gate region positioned on top of and in contact with a portion of the P-type doped region, and a back gate disposed in the semiconductor substrate beneath the anode region, cathode and P-type doped region; a second Z.sup.2-FET switch having an anode region disposed in the semiconductor layer, a cathode region disposed in the semiconductor layer, a P-type doped region disposed in the semiconductor layer between the anode region and the cathode region, an insulated gate region positioned on top of and in contact with a portion of the P-type doped region, and a back gate disposed in the semiconductor substrate beneath the anode region, cathode and P-type doped region; an input terminal coupled to the gate region of the first Z.sup.2-FET switch and to the gate region of the second Z.sup.2-FET switch; an output terminal coupled to the cathode region of the first Z.sup.2-FET switch and to the cathode region of the second Z.sup.2-FET switch; a first reference terminal coupled to the anode region of the first Z.sup.2-FET switch; and a second reference terminal coupled to the anode region of the second Z.sup.2-FET switch.

17. The inverter of claim 16, wherein the back gate of the first Z.sup.2-FET switch comprises a first N-type doped portion and a first P-type doped portion and wherein the back gate of the second Z.sup.2-FET switch comprises a second N-type doped portion and a second P-type doped portion.

18. The inverter of claim 17, wherein the first and second P-type doped portions are coupled to a positive potential and wherein the first and second N-type doped portions are coupled to a negative potential.

19. The inverter of claim 16, wherein the first Z.sup.2-FET switch is of type N and wherein the second Z.sup.2-FET switch is of type P.

20. The inverter of claim 16, wherein the first reference terminal is a power supply terminal and the second reference terminal is a ground terminal.

21. The inverter of claim 15, wherein the N-type Z.sup.2-FET switch comprises: a first anode region forming the anode of the N-type Z.sup.2-FET switch disposed within a semiconductor layer of a silicon on insulator (SOI) substrate; a first cathode region forming the cathode of the N-type Z.sup.2-FET switch disposed within the semiconductor layer; a first P-type doped region separating the anode region from the cathode region; and the P-type doped portion of the N-type Z.sup.2-FET switch and the N-type doped portion of the N-type Z.sup.2-FET switch formed on a semiconductor substrate portion of the SOI substrate.

22. The inverter of claim 21, wherein the top gate of the N-type Z.sup.2-FET switch directly overlies the P-type doped portion of the back gate of the N-type Z.sup.2-FET switch, and wherein the top gate is disposed over the P-type doped region and disposed closer to the anode region than the cathode region.

23. The inverter of claim 21, wherein the P-type Z.sup.2-FET switch comprises: an anode region forming the anode of the P-type Z.sup.2-FET switch disposed within the semiconductor layer; a cathode region forming the cathode of the P-type Z.sup.2-FET switch disposed within the semiconductor layer; a P-type doped region separating the anode region from the cathode region; and the P-type doped portion and the N-type doped portion formed on a semiconductor substrate portion of the SOI substrate.

24. The inverter of claim 23, wherein the top gate of the P-type Z.sup.2-FET switch directly overlies the N-type doped portion of the back gate of the P-type Z.sup.2-FET switch, and wherein the top gate is disposed over the P-type doped region and disposed closer to the cathode region than the anode region.

25. An inverter comprising: an N-type Z.sup.2-FET switch disposed at a first surface of a semiconductor substrate, wherein the Z.sup.2-FET comprises a P-type anode region, an N-type cathode region, a P-type intermediate region disposed between the P-type anode region and the N-type cathode region, a front gate disposed over the P-type intermediate region, a first back gate comprising a P-type doped portion, and a second back gate comprising a N-type doped portion, the first back gate being coupled to a negative reference potential node and the second back gate being coupled to a positive reference potential node; and an N-channel MOS transistor disposed at the first surface of the semiconductor substrate, the N-channel MOS transistor having a gate, the N-channel MOS transistor being coupled between the N-type cathode region of the N-type Z.sup.2-FET switch and a reference potential node, the P-type anode region coupled to a supply voltage node, the gate of the N-channel MOS transistor and the front gate of the N-type Z.sup.2-FET switch being coupled to an input voltage node.

26. The inverter of claim 25, wherein the P-type intermediate region comprises silicon-germanium.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a simplified cross-section view illustrating an N-type Z.sup.2-FET switch;

(2) FIG. 2 is a simplified cross-section view illustrating a P-type Z.sup.2-FET switch;

(3) FIG. 3 is an electric diagram of an embodiment of an inverter; and

(4) FIG. 4 is an electric diagram of another embodiment of an inverter.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(5) The same elements have been designated with the same reference numerals in the different drawings. For clarity, only those steps and elements which are useful to the understanding of the described embodiments have been shown and are detailed.

(6) In the following description, when reference is made to terms qualifying absolute positions, such as terms front, back, top, bottom, left, right, etc., or relative positions, such as terms above, under, upper, lower, etc., or to terms qualifying directions, such as terms horizontal, vertical, etc., it is referred to the orientation of the drawings. The terms approximately, substantially, and in the order of are used herein to designate a tolerance of plus or minus 10%, preferably of plus or minus 5%, of the value in question.

(7) In the present description, the term connected will be used to designate a direct electric connection, with no intermediate electronic component, for example, by means of a conductive track, and term coupled or term linked will be used to designate either a direct electric connection (then meaning connected) or a connection via one or a plurality of intermediate components (resistor, capacitor, etc.).

(8) FIG. 1 is a cross-section view schematically showing a Z.sup.2-FET switch, and more particularly an N-type switch I.sub.N. In FIG. 1, switch I.sub.N is more particularly a double ground plane (DGP) Z.sup.2-FET type switch.

(9) Switch I.sub.N is formed inside and on top of a SOI (Silicon On Insulator) structure comprising a semiconductor layer 1, currently made of silicon, resting on an insulating layer 3, currently called BOX (for Buried OXide) and itself resting on a semiconductor support 5, currently made of silicon. Semiconductor support 5 is used as a back gate BG of switch I.sub.N. An active area is delimited in layer 1 and comprises an anode region A.sub.N and a cathode region K.sub.N (or an anode A.sub.N and a cathode K.sub.N) separated by an intermediate region 11. Anode region A.sub.N is heavily P-type doped (P+) and is located on the left-hand side of FIG. 1. Cathode region K.sub.N is heavily N-type doped (N+) and is located on the right-hand side of FIG. 1. Intermediate region 11 is heavily P type doped (P) and is located between anode region A.sub.N and cathode region K.sub.N. As an example, the intermediate region may be made of compressed silicon-germanium. Back gate BG is divided into a P-type doped portion BG.sub.P and an N-type doped portion BG.sub.N. As a variation, the back gate might be P-type doped only. Portion BG.sub.P is positioned on the side of anode A.sub.N (on the left-hand side of FIG. 1) and portion BG.sub.N is positioned on the side of cathode K.sub.N. Portions BG.sub.N and BG.sub.P are separated in FIG. 1 by dotted lines 6. An insulated gate is formed on a portion of layer 11 on the side of anode region 7. The insulated region comprises a gate region FG.sub.N called front gate FG.sub.N made of polysilicon and an insulating layer 15 resting on the portion of layer 11.

(10) The operation of N-type Z.sup.2-FET switch I.sub.N will now be described. During an operating phase, a potential is applied to back gate BG. More particularly, portion BG.sub.N is coupled to a terminal of application of a positive potential and portion BG.sub.P is coupled to a terminal of application of a negative potential. Further, a positive potential is applied to front gate FG.sub.N. To turn on switch I.sub.N, a positive potential is applied to anode A.sub.N, after which a pulse at a zero potential is applied to front gate FG.sub.N, which results in attracting electrons under front gate FG.sub.N of switch I.sub.N. Switch I.sub.N thus is in a low-impedance state and is thus on.

(11) FIG. 2 is a cross-section view of a P-type Z.sup.2-FET switch I.sub.P. The switch I.sub.P of FIG. 2 is similar to the switch I.sub.N of FIG. 1, and thus switch I.sub.P comprises a semiconductor layer 1 resting on an insulating layer 3 which itself rests on a semiconductor layer 5. Layer 1 is divided into three regions: an anode region A.sub.P, an intermediate region 11, and a cathode region K.sub.P. The back gate and the front gate of switch I.sub.P are respectively designated with references BG and FG.sub.P. The difference between switch I.sub.P and switch I.sub.N is that the insulated gate of switch I.sub.P is formed on a portion of layer 11 on the side of cathode region K.sub.P (on the right-hand side in FIG. 2). The insulated gate then still comprises front gate FG.sub.P and an insulating layer 15 resting on the portion of layer 11. The back gate is divided into two portions, one N-type doped (BG.sub.N) and one P-type doped (BG.sub.P).

(12) The operation of P-type Z.sup.2-FET switch I.sub.P will now be described. During an operating phase, back gate BG is coupled to a terminal of application of a potential. More particularly, portion BG.sub.P is coupled to a terminal of application of a positive potential and portion BG.sub.N is coupled to a terminal of application of a negative potential. Further, a zero potential is applied to front gate FG.sub.P. To turn on switch I.sub.P, a zero potential is applied to cathode K.sub.P, after which a pulse at a positive potential is applied to front gate FG.sub.P, which results in attracting holes under front gate FG.sub.P of switch I.sub.P. Switch I.sub.P then is in a low-impedance state and is thus on.

(13) FIG. 3 is an electric diagram of an embodiment of an inverter 20 comprising an N-type Z.sup.2-FET switch I.sub.N and a P-type Z.sup.2-FET switch I.sub.P.

(14) In FIG. 3, the N-type and P-type Z.sup.2-FET switches are symbolized in the form of a diode to which certain connections have been added. The anode of the diode corresponds to the anode of the switch and its cathode corresponds to the cathode of the switch. This symbol comprises connections symbolizing front gate FG.sub.N and the two doped portions of back gate BG.sub.N and BG.sub.P. The connection symbolizing front gate FG.sub.N is positioned on the lateral side (on the left-hand side in FIG. 3) of the diode symbol, on the anode side for the N-type Z.sup.2-FET switch and on the cathode side for the P-type Z.sup.2-FET switch. The connection symbolizing the N-type doped portion BG.sub.N of the back gate is positioned on the lateral side (on the right-hand side in FIG. 3) of the diode symbol on the anode side. The connection symbolizing the P-type doped portion BG.sub.P of the back gate is positioned on the lateral side (on the right-hand side in FIG. 3) of the diode symbol on the cathode side. Further, to help differentiate the N-type Z.sup.2 FET switch from the P-type Z.sup.2-FET switch, the symbol of the P type Z.sup.2-FET switch comprises on the cathode side a black dot.

(15) In inverter 20, switches I.sub.N and I.sub.P are series-connected between a terminal of application of a power supply potential Vdd and a terminal of application of a reference potential Vss, for example, the ground. More particularly, the anode of switch I.sub.N is coupled, preferably connected, to the terminal of application of potential Vdd and the cathode of switch I.sub.N is coupled, preferably connected, to an output terminal supplying an output potential Vout. The anode of switch I.sub.P is coupled, preferably connected, to the output terminal supplying output potential Vout and the cathode of switch I.sub.P is coupled, preferably connected, to the terminal of application of reference potential Vss. The front gates of switches I.sub.N and I.sub.P are coupled, preferably connected, to a terminal of application of an input potential V.sub.in. The N-type doped portions of the back gates of switches I.sub.N and I.sub.P are coupled, for example, connected, to a terminal of application of a positive potential V.sub.N. The P-type doped portions of the back gates of switches I.sub.N and I.sub.P are coupled, for example, connected, to a terminal of application of a negative potential V.sub.P.

(16) Since the cathode of switch I.sub.P receives the reference potential (Vss), generally zero, a positive pulse on input potential Vin turns on switch I.sub.P. The output potential is then equal to potential Vss.

(17) Since the anode of switch I.sub.N receives the positive potential (Vdd), a negative or zero pulse on input potential Vin turns on switch I.sub.N. The output potential is then equal to potential Vdd.

(18) FIG. 4 is an electric diagram of an embodiment of an inverter 30 comprising a Z.sup.2-FET switch I.sub.N and of an N-channel MOS transistor T. Inverter 30 is similar to inverter 20, with the difference that switch I.sub.P is replaced with transistor T.

(19) When input potential Vin is positive, transistor T turns on and the output potential is then equal to potential Vss.

(20) Since the anode of switch I.sub.N receives a positive potential (Vdd), a negative or zero pulse on input potential Vin turns on switch I.sub.N. The output potential is then equal to potential Vdd.

(21) As a variation, based on the structure of FIG. 3, switch I.sub.N may be replaced with a P-channel MOS transistor.

(22) As usual, the following terms are used:

(23) lightly-doped semiconductor layer designates a layer having a dopant atom concentration in the range from 10.sup.14 to 510.sup.15 atoms/cm.sup.3;

(24) heavily-doped semiconductor layer designates a layer having a dopant atom concentration in the range from 10.sup.17 to 10.sup.18 atoms/cm.sup.3; and

(25) very heavily-doped semiconductor layer designates a layer having a dopant atom concentration in the range from 10.sup.18 to 10.sup.20 atoms/cm.sup.3.

(26) Specific embodiments have been described. Various alterations, modifications, and improvements will occur to those skilled in the art. In particular, N-type and P-type Z.sup.2-FET switches having a fully lightly P-type doped back gate, also called single ground plane Z.sup.2-FET switch, may be used.

(27) Various embodiments with different variations have been described hereabove. It should be noted that those skilled in the art may combine various elements of these various embodiments and variations without showing any inventive step.

(28) Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.