METHOD FOR MANUFACTURING A SEMICONDUCTOR PACKAGE ASSEMBLY AS WELL AS SUCH SEMICONDUCTOR PACKAGE ASSEMBLY

Abstract

A method for manufacturing a semiconductor package assembly is provided. The assembly includes a semiconductor package and a molding resin case encapsulating the semiconductor package. The complete semiconductor package undergoes a surface roughening treatment, thus improving the overall adhesion with the molding resin (EMC) and reducing the risks of delamination.

Claims

1. A method for manufacturing a semiconductor package assembly, the method comprising the steps of i) forming at least one semiconductor package by: i1) providing a lead frame having a first frame side and a second frame side opposite to the first frame side; i2) adhering at least one semiconductor die structure having a first die side and a second die side opposite to the first die side with the second die side on the first frame side of the lead frame, resulting in a first conductive connection between the lead frame and the at least one semiconductor die structure; i3) adhering at least one bond element on the first die side of the at least one semiconductor die structure and/or on the first frame side of the lead frame, resulting in at least one further conductive connection between the at least one bond element and the at least one semiconductor die structure and between at least a further bond element and the lead frame; and ii) encapsulating the at least one semiconductor package with a molding resin, thereby forming at least one encapsulated semiconductor package assembly; wherein, prior to step ii but after step i3, the method further comprises the step of: iii) subjecting the exposed surfaces of the first frame side of the lead frame, the adhering connections and the at least one bond element of the at least one semiconductor package to a surface roughening treatment using a chemical solution, wherein the chemical solution is an organic or inorganic cleaning agent.

2. The method according to claim 1, wherein the organic or inorganic cleaning agent is a photoresist layer stripping agent.

3. The method according to claim 1, wherein the surface roughening treatment of step iii) consists of submerging the at least one semiconductor package in the chemical solution for a period of at least 10 minutes.

4. The method according to claim 1, wherein prior to the encapsulating of step ii) but after the surface roughening treatment of step iii) the method further comprises the steps of: iv) rinsing the semiconductor package with deionized water; and v) drying the semiconductor package.

5. The method according to claim 1, further comprising, after the encapsulating of step ii), the steps of: vi) plating the exposed lead frame; and vii) singulating the at least one encapsulated semiconductor package assembly.

6. The method according to claim 2, wherein the surface roughening treatment of step iii) consists of submerging the at least one semiconductor package in the chemical solution for a period of at least 10 minutes.

7. The method according to claim 2, wherein, prior to the encapsulating of step ii) but after the surface roughening treatment of step iii) the method further comprises the steps of: iv) rinsing the semiconductor package with deionized water; and v) drying the semiconductor package.

8. The method according to claim 2, further comprising, after the encapsulating of step ii), the steps of: vi) plating the exposed lead frame; and vii) singulating the at least one encapsulated semiconductor package assembly.

9. The method according to claim 2, wherein the photoresist layer stripping agent can be an aqueous, a solvent or a semi-aqueous agent.

10. The method according to claim 3, wherein the submerging period is 20-40 minutes.

11. The method according to claim 3, wherein the submerging period is about minutes.

12. The method according to claim 3, wherein the submerging of step iii) is performed at an elevated temperature of at least 10 C. below the flashpoint temperature of the chemical solution used.

13. The method according to claim 10, wherein the submerging period is about minutes.

14. The method according to claim 11, wherein the submerging of step iii) is performed at an elevated temperature of at least 10 C. below the flashpoint temperature of the chemical solution used.

15. The method according to claim 12, wherein, prior to the encapsulating of step ii) but after the surface roughening treatment of step iii) the method further comprises the steps of: iv) rinsing the semiconductor package with deionized water; and v) drying the semiconductor package.

16. A semiconductor package assembly comprising: semiconductor package composed of a lead frame having a first frame side and a second frame side opposite to the first frame side; at least one semiconductor die structure having a first die side and a second die side opposite to the first die side being adhered with the second die side on the first frame side of the lead frame, resulting in a first conductive connection between the lead frame and the at least one semiconductor die structure; at least one bond element adhered on the first die side of the at least one semiconductor die structure and/or on the first frame side of the lead frame, resulting in at least one further conductive connection between the at least one bond element and the at least one semiconductor die structure and between at least a further bond element and the lead frame; and a molding resin encapsulating the at least one semiconductor package, wherein prior to encapsulating the at least one semiconductor package with the molding resin the exposed surfaces of the first frame side of the lead frame, the adhering connections and the at least one bond element of the at least one semiconductor package are surface roughened using a chemical solution using the method steps of claim 1.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0020] The disclosure will now be discussed with reference to the drawings, which show in:

[0021] FIG. 1 a flow chart depicting the relevant steps of an example of the method according to the disclosure.

[0022] FIGS. 2 and 3 two examples showing details of a semiconductor package assembly as obtained with the method according to the disclosure.

[0023] FIG. 4 details showing a comparison between a semiconductor package assembly according to the state of the art and a semiconductor package assembly as obtained with the method according to the disclosure.

DETAILED DESCRIPTION

[0024] For a proper understanding of the disclosure, in the detailed description below corresponding elements or parts of the disclosure will be denoted with identical reference numerals in the drawings.

[0025] In FIG. 1 a flow chart is shown, which depicts the relevant steps of an example of the method according to the disclosure. The reference numerals denoted below when outlining the method steps according to the disclosure, reference is made to FIGS. 2 and 3.

[0026] In a first steps at least one semiconductor package (reference numeral 11 in FIG. 2, 11 in FIG. 3) is formed by means of the sub-steps i1) providing a lead frame 13 having a first frame side 13a and a second frame side 13b opposite to the first frame side 13a. The lead frame 13 is preferably made from a copper material plate. Following the sub-step i1, in a sub-step i2 at least one semiconductor die structure 14 is adhered to the lead frame 13. In general at least one semiconductor die structure 14 has a first die side 14a and a second die side 14b opposite to the first side 14a and the adhering step i2 is performed by adhering the second die side 14b on the first frame side 13a of the lead frame 13.

[0027] The adhering step i2 can be performed with any suitable adhering principle used in semiconductor package manufacturing. For example, a glue connection or a soldering connection can be implemented, as long as step i2 results in a first conductive connection 15 between the lead frame 13 and the at least one semiconductor die structure 14.

[0028] Similarly, in a further adhering step i3 at least one bond element is adhered on the first die side 14a of the at least one semiconductor die structure 14 and/or on the first frame side 13a of the lead frame 13. Likewise, in step i3, any suitable adhering principle can be used in semiconductor package manufacturing, such as a glue connection or a soldering connection. In either way, also step i3 results in at least one further conductive connection 16 between the at least one bond element and the at least one semiconductor die structure 14 and between at least a further bond element and the lead frame 13. As to the type of bond element used, in an example of step i3, a bond clip 17 (FIG. 2) is adhered to the semiconductor die structure 14 thus forming the further conductive connection 16, whereas in FIG. 3, the result of step i3 is a further conductive connection being formed of a contact pad or ball bond 170 adhered to the first die side 14a of the semiconductor die structure 14, further completed with the adhering of a bond wire 171 to the contact pad or ball bond 170.

[0029] After establishing all conductive connections 15 and 16 (depicted in either FIGS. 2 and 3), the encapsulated semiconductor package assembly 10-10 is created in step ii by encapsulating the at least one semiconductor package 11-11 with a molding resin case 12 (EMC, or Epoxy Molding Compound).

[0030] In order to prevent or limit the occurrence of delamination in the semiconductor package assembly 10-10 between the molding resin (EMC) and the semiconductor package 11-11 the adhesion between both parts of the semiconductor package assembly 10-10 has to be improved and according to the disclosure a step iii is proposed, wherein the exposed surface 13z of the first frame side 13a of the lead frame 13, the exposed surfaces 15z-16z of the adhering conductive connections 15-16, the exposed surface 14z of the semiconductor die structure 14 and the exposed surfaces 17z-170z of the bond elements 17-170 of the at least one semiconductor package 11-11 are subjected to a surface roughening treatment using a chemical solution.

[0031] It is essential to note that the surface roughening treatment step iii is performed prior to the encapsulating step ii, but after the adhering step i3 of adhering the at least one bond element 17 (170-171) on the first die side 14a of the at least one semiconductor die structure 14 and/or on the first frame side 13a of the lead frame 13.

[0032] Alternatively, it is also noted that the step i3 of adhering the bond wire 171 to the contact pad or ball bond 170 can be performed before or after the roughening treatment step iii. The roughening of a bond wire 171 is only applicable if the wire bonding step is performed before the chemical treatment.

[0033] Accordingly, with the surface roughening treatment of step iii all outer surfaces 13z-14z-15z-16z-17z-170z of the complete semiconductor package 11-11 undergo a surface roughening treatment prior to its encapsulation with the EMC molding resin case 12. The overall adhesion with the molding resin (EMC) 12 is thus significantly improved and any risk of delamination between (the outer surface of) the semiconductor package 11-11 and the EMC 12 is reduced. Also, the adverse effects of surface roughening of the lead frame 13 in advance at the supplier site are obviated as well as its corresponding negative impact on solder wettability issues and pattern recognition (PR) issues in DACA (Die Attach Clip Attach) processes.

[0034] The chemical solution used in step iii can be an organic or inorganic cleaning agent. It has been discovered that preferably a photoresist layer stripping agent is highly beneficial for performing the step iii. In particular, the photoresist layer stripping agent can be an aqueous, a solvent or a semi-aqueous agent.

[0035] In a beneficial application step, it has been found the roughening step iii should involve submerging the at least one semiconductor package 11-11 in the chemical solution and exposing its outer surfaces 13z-14z-15z-16z-17z-170z for a period of at least 10 minutes. As examples of beneficial time frames, the step iii of submerging and exposing the outer surfaces 13z-14z-15z-16z-17z-170z is to be performed during a time frame of at least 10 minutes.

[0036] Additionally, by performing the surface roughening of the exposed surfaces 13z-14z-15z-16z-17z-170z of the complete semiconductor package 11 (11) during the submerging step iii) at an elevated temperature of at least 10 C. below the flashpoint temperature of the chemical solution used, the resulting adhesion of the molding resin (EMC) with the surface roughened semiconductor package 11-11 is improved significantly. Elevated temperatures will increase the chemical reaction rate and increase the roughening effect while too high temperature will cause fire hazards since the flash point is minimum temperature where chemical gives off vapor to form an ignitable mixture with the air near the surface of the liquid.

[0037] Subsequently, the method according to the disclosure is finalized after the surface roughening step iii, but prior to the encapsulating step ii by step iv, wherein the roughened semiconductor package 11-11 is rinsed with deionized water, and subsequently dried during a step v.

[0038] Finally, after the encapsulating step ii, the method according to the disclosure comprises the step vi of plating the exposed lead frame ends and singulating in step vii the at least one encapsulated semiconductor package assembly, thereby obtaining a single encapsulated semiconductor package assembly 10-10 with a molding resin case 12 having an improved adhesion with the roughened yet encapsulated semiconductor package 11-11 and consequently a reduced risk of delamination.

[0039] Although already referenced above when describing the method steps according to the disclosure, FIGS. 2 and 3 disclose two examples of a semiconductor package assembly as obtained with the method according to the disclosure. These examples are denoted with reference numeral 10 (FIG. 2) and 10 respectively (FIG. 3). The semiconductor package assemblies 10-10 as shown in FIGS. 2 and 3 are conventional lead frame-based IC package assemblies. The main part is the semiconductor package, indicated with reference numeral 11 in FIG. 2 and reference numeral 11 in FIG. 3. The semiconductor package 11 (11) includes in a non-limited example, a lead frame 13 having a first frame side 13a and a second frame side 13b, the latter being positioned opposite to the first frame side 13a. In the Figures, the first frame side 13a can be classified as the upper or top side, whereas the second frame side 13b opposite to the first frame side 13a can be classified as the bottom or lower side. The lead frame 13 is in an example made from copper plate material.

[0040] Reference numeral 14 denotes a semiconductor die structure having a first (top or upper) die side 14a and a second (bottom or lower) die side 14b opposite to the first side 14a. The semiconductor die structure 14 is provided or mounted with its lower, second die side 14b on the upper, first frame side 13a of the lead frame 13. The mounting can be facilitated by means of an adhering connection, e.g. a glue connection or a soldering connection 15, which, during manufacturing, as outlined in step i2 of the method according to the disclosure, is provided between the lower, second die side 14b and the upper, first frame side 13a.

[0041] In both examples of FIGS. 2 and 3, conformal to step i3 of the method of the disclosure, one or more bond elements are electrically connecting the semiconductor die structure 14 with e.g. the lead frame 13. Accordingly, as shown in FIG. 2, the semiconductor die structure 14 is on its first (top or upper) die side 14a provided with one or more bond elements 17, which are construed as bond clips 17. The bond clips 17 in this example are provided on the upper, first die side 14a with the assistance of the adhering connection 16, e.g. through gluing or soldering.

[0042] Alternatively, as shown in FIG. 3, one or more bond wires 171 can be electrically connected via a contact pad or ball bond 171 with the first die side 14a of the semiconductor die structure 14 using suitable known semiconductor connecting techniques. Each bond wire 171 can be electrically connected with a frame lead (not shown) of the lead frame 13.

[0043] When performing the surface roughening treatment of step iii of the method according to the disclosure, all exposed outer surfaces 13z-14z-15z-16z-17z-170z of the first frame side 13a of the lead frame 13, the adhering conductive connections the semiconductor die structure 14 and the bond elements 17-170 of the at least one complete semiconductor package 11-11 are surface roughened treatment prior to their encapsulation with the EMC molding resin case 12.

[0044] The results of the surface roughening step iii are for example shown in FIG. 4, which shows in its left column L surface SEM (scanning electron microscope) pictures of various parts of a semiconductor package according to the state of art, and in its right column R SEM (scanning electron microscope) pictures of corresponding parts of a semiconductor package, which underwent the surface roughening treatment of to the method according to the disclosure.

[0045] FIG. 4a depicts the differences in surface roughness 13z-17z of a surface side 13a of a lead frame 13 according to the state of the art (LEFT) and according to the method of the disclosure (RIGHT). It is noted that the surface 13z in the right column exhibits a more irregular surface roughness and hence an improved adhesion than the surface according to the state of the art in the left column.

[0046] FIG. 4b depicts the differences in surface roughness 15z-16z of the adhering conductive connections 15-16, according to the state of the art (LEFT) and according to the method of the disclosure (RIGHT). It is noted that the surface in the right column exhibits a more irregular surface roughness and hence an improved adhesion than the surfaces according to the state of the art in the left column.

[0047] FIGS. 4c and 4d depict the differences as the contact angles on the lead frame surface 13a (FIG. 4c: 80.1 in the left column versus 33.2 in the right column) and the differences as the contact angles on die surface side 14a (FIG. 4d: 10.4 in the left column versus 4.5 in the right column). In both Figures, the pictures in the right column show that the surface treated surfaces have reduced contact angles compared to the untreated surfaces according to the state of the art in the left column. Accordingly, the surfaces which have undergone the surface roughening treatment of the method according to the disclosure have a smaller contact surface, hence an improved adhesion with the molding resin case 12 and accordingly a reduced delamination.

[0048] The reduction in delamination is shown in FIG. 4e, wherein the delamination occurrence has been reduced from 30% in the untreated surface in the left column to 3% in the surface roughened surface in the right column.

[0049] Similarly, FIGS. 4f and 4g pertain to the decapping or removal of the molding resin case 12 from the semiconductor package assembly in order to expose the semiconductor die structure 14. FIG. 4f pertains to mechanical decapping, whereas FIG. 4g pertains to chemical decapping. In both decapping techniques, the right column shows that after decapping the exposed roughened surfaces 15z-16z of the adhering conductive connections 15-16 as treated with the method according to the disclosure exhibit a rougher surface, than the unroughened surfaces of the corresponding parts in a semiconductor package assembly according to the state of art.

[0050] In the lead frame roughening according to the prior art, particularly Cu lead frame is achieved through chemical etching which consists of acids like H.sub.2SO.sub.4, H.sub.2O.sub.2 or a mixture of it. These acids are etchant and potentially will etch/attack the die top metal typically AlCu/TiNiAg which eventually will cause poor contact and reliability issue. In the disclosure, we are using the chemical which is generally safe/compatible with the die structure preferably a photo resist stripper which will not attack the die top metal/surface at the same time have substantial roughening effect to the lead frame surface typically of Cu lead frame and interconnects.