Semiconductor device

Abstract

A multilayer semiconductor device includes first wirings extending in a first direction and arranged adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and the second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The third and fourth directions are neither parallel nor orthogonal to the first and second directions. The dummy wirings have a first, a second, and a third dummy wiring. Centers of the second and third dummy wirings are nearest to a center of the first dummy wiring relative to others of the dummy wirings. The respective centers of the first, second, and third dummy wirings are aligned on a third virtual linear line extending in a fifth direction neither parallel to nor perpendicular to the first and second directions.

Claims

1. A semiconductor device comprising: a plurality of first wirings extending in a first direction, the plurality of first wirings are arranged adjacent to each other in a second direction on a layer level; a second wiring that is apart from the plurality of first wirings in the second direction on the layer level; and a plurality of dummy wirings arranged between the plurality of first wirings and the second wiring on the layer level, wherein the plurality of dummy wirings are arranged at a plurality of crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction, wherein: the third direction and the fourth direction are neither parallel nor orthogonal to the first direction and the second direction, the plurality of dummy wirings having: a first dummy wiring; a second dummy wiring; and a third dummy wiring, wherein centers of the second dummy wiring and the third dummy wiring are nearest to a center of the first dummy wiring relative to others of the plurality of dummy wirings, and the respective centers of the first dummy wiring, the second dummy wiring, and the third dummy wiring are aligned on one of the first virtual linear line extending in the third direction, the plurality of dummy wirings are square-shaped in a plan view, a distance between the first dummy wiring and the second dummy wiring is smaller than a length of each side of the first dummy wiring, and a distance between the first dummy wiring and the third dummy wiring is smaller than the length of each side of the first dummy wiring.

2. The semiconductor device of according to claim 1, wherein each distance between adjacent ones of the plurality of dummy wirings is about half of a length of each side of each of the plurality of dummy wirings.

3. The semiconductor device according to claim 1, wherein an angle between the one of the first virtual linear line and the first direction is between 15 and 25.

4. The semiconductor device according to claim 1, wherein an angle between the one of the first virtual linear line and the first direction is between 2 and 40.

5. The semiconductor device according to claim 1, wherein a plan area of layers of the dummy wirings occupies a unit plan area at a rate of 30-50%.

6. The semiconductor device according to claim 1, wherein an angle between the one of the first virtual linear line and the first direction is between 2 and 40 and the dummy wirings are formed from an alloy of aluminum and copper.

7. The semiconductor device according to claim 1, wherein an angle between the one of the first virtual linear line and the first direction is between 2 and 40, a via plug connects a wiring on another layer level with the plurality of first wirings or the second wiring on the layer level, and the via plug is made of tungsten.

8. The semiconductor device according to claim 7, wherein the distance between the first dummy wiring and the second dummy wiring is in a range of 0.5 to 5.0 m.

9. The semiconductor device according to claim 7, wherein the distance between the first dummy wiring and the second dummy wiring is approximately 1.0 m and the distance between the first dummy wiring and the third dummy wiring is approximately 1.0 m.

10. The semiconductor device according to claim 1, wherein the plurality of dummy wirings includes a fourth dummy wiring and a fifth dummy wiring.

11. The semiconductor device according to claim 10, wherein centers of the fourth dummy wiring and the fifth dummy wiring are a same distance to a center of the first dummy wiring as the second dummy wiring and the third dummy wiring.

12. The semiconductor device according to claim 11, wherein the respective centers of the first dummy wiring, the fourth dummy wiring, and the fifth dummy wiring are aligned on one of the second virtual linear lines extending in the fourth direction.

13. A semiconductor device comprising: a plurality of first wirings extending in a first direction, the plurality of first wirings are arranged adjacent to each other in a second direction on a layer level; a second wiring that is apart from the plurality of first wirings in the second direction on the layer level; and a plurality of dummy wirings arranged between the plurality of first wirings and the second wiring on the layer level, wherein the plurality of dummy wirings are arranged at a plurality of crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction, wherein: the third direction and the fourth direction are neither parallel nor orthogonal to the first direction and the second direction, the plurality of dummy wirings having: a first dummy wiring; a second dummy wiring; and a third dummy wiring, wherein centers of the second dummy wiring and the third dummy wiring are nearest to a center of the first dummy wiring relative to others of the plurality of dummy wirings, wherein the respective centers of the first dummy wiring, the second dummy wiring, and the third dummy wiring are aligned on one of the first virtual linear line extending in the third direction, wherein the dummy wirings have a polygonal shape and rotational symmetries through 90 degrees about respective centers of the dummy wirings, and wherein an angle between the one of the first virtual linear line and the first direction is between 2 and 40.

14. The semiconductor device according to claim 13, wherein the dummy wirings are formed from an alloy of aluminum and copper.

15. The semiconductor device according to claim 13, further comprising a via plug connecting a wiring on another layer level to the first or second wiring on the layer level, wherein the via plug is made of tungsten.

16. The semiconductor device according to claim 13, wherein the plurality of dummy wirings includes a fourth dummy wiring and a fifth dummy wiring.

17. The semiconductor device according to claim 16, wherein centers of the fourth dummy wiring and the fifth dummy wiring are a same distance to a center of the first dummy wiring as the second dummy wiring and the third dummy wiring.

18. The semiconductor device according to claim 17, wherein the respective centers of the first dummy wiring, the fourth dummy wiring, and the fifth dummy wiring are aligned on one of the second virtual linear lines extending in the fourth direction.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 schematically shows a plan view of a semiconductor device.

(2) FIG. 2 schematically shows a cross-sectional view taken along a line A-A of FIG. 1.

(3) FIG. 3 shows a plan view of a surface at a level where first wiring layers are formed.

(4) FIG. 4 schematically shows a plan view of patterns of dummy wiring layers.

(5) FIGS. 5(a) and 5(b) schematically show plan view of patterns of dummy wiring layers adjacent to prohibited areas.

(6) FIGS. 6(a) and 6(b) show intermediate mask data representing patterns used in a process for forming first mask data.

(7) FIG. 7 shows an intermediate mask data representing one pattern used in the process for forming the first mask data.

(8) FIG. 8 shows an intermediate mask data representing one pattern used in the process for forming the first mask data.

(9) FIG. 9 shows a figure representing the first mask data.

(10) FIG. 10 shows a figure representing second mask data.

(11) FIG. 11 shows figures indicating the relation between dummy patterns in a mask and patterns of dummy wiring layers in a semiconductor device when the mask is formed based on the second mask data.

(12) FIG. 12 shows a figure representing third mask data.

(13) FIG. 13 shows a figure representing mask data.

(14) FIG. 14(a)-14(c) schematically show in cross section of a semiconductor device in different manufacturing steps.

(15) FIGS. 15(a) and 15(b) schematically show in cross section of the semiconductor device in different manufacturing steps.

(16) FIG. 16 shows a plan view of wiring layers and dummy wiring layers in an embodiment sample.

(17) FIG. 17 shows a plan view of wiring layers and dummy wiring layers in a comparison sample.

(18) FIG. 18 schematically shows a cross section of a semiconductor device having multiple wiring layers in a manufacturing step using a conventional multiple layer wiring technique.

(19) FIG. 19 schematically shows a cross section of a semiconductor device having multiple wiring layers in which dummy wiring layers are also formed.

DESCRIPTION OF PREFERRED EMBODIMENTS

(20) Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

(21) Semiconductor devices in accordance with embodiments of the present invention will be described below. FIG. 1 illustratively shows a plan view of a semiconductor device. FIG. 2 illustratively shows a cross-sectional view taken along a line A-A of FIG. 1.

(22) Referring to FIG. 2, a semiconductor device 1000 has a semiconductor substrate (for example, a silicon substrate) 10. Semiconductor elements such as MOSFETs, wiring layers and element isolation regions (not shown) are formed on a surface of the semiconductor substrate 10. A first interlayer dielectric layer 20 is formed over the semiconductor substrate 10

(23) First wiring layers 30 and dummy wiring layers 32 are formed over the first interlayer dielectric layer 20. Depending on certain device designs, some of the first wiring layers 30 may be closely formed in one area and an isolated one of the first wiring layer 30 may be formed separated from the other first wiring layers 30

(24) Contact holes (not shown) may be formed in the first interlayer dielectric layer 20 at specified locations to connect semiconductor elements or wiring layers formed on the surface of the semiconductor substrate 10 to the first wiring layers 30. Contact layers (not shown) may be formed in the contact holes. The contact layers may be formed from, for example, tungsten plugs, aluminum alloy layers or copper layers.

(25) A second interlayer dielectric layer 40 is formed over the first wiring layers 30 and the dummy wiring layers 32. Second wiring layers 50 are formed over the second interlayer dielectric layer 40.

(26) A first contact hole 60 is formed in the second interlayer dielectric layer 40. The first contact hole 60 is a connection aperture for connecting the first wiring layers 30 and the second wiring layers 50. A first contact layer 62 is formed in the first contact hole 60. The first contact hole 62 is formed from, for example, a tungsten plug, an aluminum alloy layer or a copper layer.

(27) A second contact hole 70 is formed through the first interlayer dielectric layer 20 and the second interlayer dielectric layer 40. The second contact hold 70 is a connection aperture for connecting a semiconductor element or a wiring layer formed on the surface of the semiconductor substrate 10 to the second wiring layer 50. A second contact layer 72 is formed in the second contact hole 70. The second contact layer 72 is formed from, for example, a tungsten plug, an aluminum alloy layer or a copper layer.

(28) A pattern in plan view at a level where the first wiring layers 30 are formed is described below. FIG. 3 is a plan view of the level where the first wiring layers 30 are formed.

(29) Prohibited areas 80 are set around the first wiring layers 30 and the second contact hole 70 (i.e., an area where the second contact layer 72 is formed). It is noted that the first wiring layers 30 and the second contact hole 70 define wiring effective regions 90. Furthermore, the wiring effective regions 90 and the prohibited areas 80 define restriction regions 100.

(30) The prohibited areas 80 are regions that do not allow the dummy wiring layers 32 to be generated. The width of the prohibited area 80 is determined in consideration of circuit design. For example, the prohibited area may have a width of 0.5-100 m. When a semiconductor device does not use circuits that use electromagnetic effects, such as inductors using wiring layers, the prohibited area 80 may preferably have a width of 0.5-20 m, and more preferably 1-5 m. It is noted that the prohibited areas 80 may or may not have the same width along the entire prohibited areas 80. For example, all of the prohibited areas 80 around the first wiring layers 30 may have different widths. Alternatively, all of the prohibited areas 80 around the first wiring layers 30 may have the same width.

(31) Dummy wiring layers 32 are formed in areas other than the restriction regions (including the wiring effective regions and the prohibited areas) 100. In other words, the dummy wiring layers 32 are formed in such a manner that the dummy wiring layers 32 do not overlap the restriction regions 100. More particularly, the dummy wiring layers 32 that entirely or partially overlap the restriction regions 100 are completely excluded. Advantages derived from completely excluding the dummy wiring layers 32 that may partially overlap the restriction regions 100 are described below.

(32) The prohibited areas 80 are provided around the first wiring layers 32 and the second contact hole 70 because of the following reasons.

(33) (1) First Wiring Layer

(34) Unless the prohibited areas 80 are provided around the first wiring layers 30, dummy wiring layers 32 may be formed connected with the first wiring layers 30. In this case, for example, the wirings become wide or narrow in various places and thus have different resistance values at different places. When the wirings have different resistance values at different places, the designed wiring resistance values cannot be attained. As a result, device characteristics may vary. Also, due to the increased area of the wirings, the wirings may be readily short-circuited.

(35) (2) Second Contact Hole

(36) Unless the prohibited area 80 is provided around the second contact hole 70, a dummy wiring layer 32 may be formed in a region where the second contact hole 70 is formed. In this case, when the second interlayer dielectric layer 40 and the first interlayer dielectric layer 20 are etched to form the second contact hole 70, the dummy wiring layer 32 may function as an etching stopper layer for the first interlayer dielectric layer 20 such that the second contact hole 70 may not be formed.

(37) Referring to FIG. 4, a disposition pattern of the dummy wiring layers 32 is described below.

(38) The dummy wiring layers 32 are located on first virtual linear lines L1. In one embodiment, for example, the dummy wiring layers 32 may be formed in a manner that centers of the dummy wiring layers 32 are located on the first virtual linear lines L1.

(39) The dummy wiring layers 32 are also formed in a manner to be located on second virtual linear lines L2. In one embodiment, for example, the dummy wiring layers 32 may be formed in a manner that centers of the dummy wiring layers 32 are located on the second virtual linear lines L2.

(40) The dummy wiring layers 32 are disposed in a direction traversing a first matrix direction (for example, a direction of rows or a direction of columns in a matrix) and also disposed in a direction traversing a second matrix direction (for example, a direction of rows or a direction of columns in the matrix). The first matrix direction may perpendicularly traverse the second matrix direction.

(41) The first virtual linear lines L1 traverse the row direction. The first virtual linear lines L1 and the row direction define an angle 1 that is 2-40 degrees. Preferably, the angle 1 is 15-25 degrees. More preferably, the angle 1 is about 20 degrees. The row direction used here refers to one direction that is virtually defined in view of, for example, the first wiring layers 30, the second contact hole 70, and the prohibited areas 80.

(42) The second virtual linear lines L2 traverse the column direction. The second virtual linear lines L2 and the column direction define an angle 2 that is 2-40 degrees. Preferably, the angle 2 is 15-25 degrees. More preferably, the angle 2 is about 20 degrees. The column direction used here refers to one direction that is virtually defined, for example, in consideration of the first wiring layers 30, the second contact hole 70, and the prohibited areas 80.

(43) The first virtual linear lines L1 are defined in plurality. The first virtual linear lines L1 are defined to be separated from one another at a specified pitch. The first virtual linear lines L1 may be separated from one another by any distance. However, in a preferred embodiment, adjacent ones of the first virtual linear lines L1 may be separated from one another by a gap of, for example, about 1-16 m, and more preferably 2-5 m. The second virtual linear lines L2 are defined in plurality. The second virtual linear lines L2 are defined to be separated from one another at a specified pitch. The second virtual linear lines L2 may be separated from one another by any distance. However, in a preferred embodiment, adjacent ones of the second virtual linear lines L2 may be separated from one another by a gap of, for example, 1-16 m, and more preferably 2-5 m.

(44) Adjacent ones of the dummy wiring layers 32 disposed next to one another on each one of the first virtual linear lines L1 are mutually offset in the column direction. The dummy wiring layers 32 may be offset in the column direction by a width Y10. In one embodiment, the width Y10 is 0.5-5 m. In a preferred embodiment, the width Y10 is 0.5-2 m, and more preferably about 1 m.

(45) Adjacent ones of the dummy wiring layers 32 disposed next to one another on each one of the second virtual linear lines L2 are mutually offset in the row direction. The dummy wiring layers 32 may be offset in the row direction by a width X10. In one embodiment, the width X10 is about 0.5-5 m. In a preferred embodiment, the width X10 is 0.5-2 m, and more preferably about 1 m.

(46) In a plan configuration, a ratio of an area occupied by the dummy wiring layers 32 with respect to a unit area is not particularly limited. However, in a preferred embodiment, the area occupied by the dummy wiring layers 32 in a unit area is 30-50%, and more preferably about 40%. In one embodiment, the area occupied by the dummy wiring layers 32 in a unit area may preferably be 30-50%, and more preferably about 40%.

(47) The unit area used here is the minimum unit area that can be repeated in an up-to-down direction and right-to-left direction to form the entire pattern. In one embodiment, a unit area is defined by a rectangle ABCD shown in FIG. 4.

(48) The configuration in plan view of the dummy wiring layer 32 is not particularly limited. For example, the dummy wiring layer 32 may have a polygonal shape in plan view or a circular shape in plan view. In one embodiment, the dummy wiring layer 32 may have a polygonal shape in plan view. Preferably, the dummy wiring layer 32 may have a rectangular shape in plan view, and more preferably a square shape in plan view. When the dummy wiring layers 32 each have a generally square shape in plan view, the dummy wiring layers 32 can be more densely formed. For example, the dummy wiring layers 32 can be more securely formed even in an area adjacent to a crossing area where prohibited areas cross each other at right angles. As a result, the dummy wiring layers 32 can be more effectively formed in an area adjacent to a prohibited area formed with a complex pattern (for example, a prohibited area around a wiring layer that is formed with a complex pattern).

(49) When the configuration in plan view of the dummy wiring layer 32 is generally square, the length T10 of each side of the dummy wiring layer 32 is not particularly limited. However, for example, the length of each side of the dummy wiring layer 32 may be 1-10 m. Preferably, the length of each side of the dummy wiring layer 32 may be about 2 m. When the length T10 of each side of each of the dummy wiring layers 32 is about 1 m or greater, the amount of data for generating a mask, which is used to form the dummy wiring layers 32, is prevented from substantially increasing. When the length T10 of each side of each of the dummy wiring layers 32 is 10 m or shorter, the dummy wiring layers can be formed in a space between wiring layers that are separated from one another by at least 10 m, where step differences in an interlayer dielectric layer over the wiring layers are readily formed. Therefore, step differences in the interlayer dielectric layer can be effectively eliminated.

(50) When the configuration in plan view of the dummy wiring layer 32 is generally square, adjacent ones of the dummy wiring layers 32 disposed next to one another on the same one of the first virtual linear lines L1 have sides S1 and S2 that partially oppose to one another. A gap G10 between the partially opposing sides S1 and S2 is not particularly limited to a specific range. However, the gap G10 may preferably be 0.5-5 m, and more preferably about 1 m. Also, the gap G10 may preferably be set shorter than the side length T10 of each of the dummy wiring layers 32. More preferably, the gap G10 may be about a half of the side length T10 of each of the dummy wiring layers 32.

(51) When the configuration in plan view of the dummy wiring layer 32 is generally square, adjacent ones of the dummy wiring layers 32 disposed next to one another on the same one of the second virtual linear lines L2 have sides S3 and S4 that partially oppose to one another. A gap G20 between the partially opposing sides S3 and S4 is not particularly limited to a specific range. However, the gap G20 may preferably be 0.5-5 m, and more preferably about 1 m. Also, the gap G20 may preferably be set shorter than the side length T10 of each of the dummy wiring layers 32. More preferably, the gap G20 may be about a half of the side length T10 of each the dummy wiring layers 32.

(52) When the configuration in plan view of the dummy wiring layer 32 is generally square, adjacent ones of the dummy wiring layers 32 disposed next to one another in the row direction are offset by a width Y10 in the column direction. The width Y10 may preferably be about a half of the length of each side of the dummy wiring layer 32. Also, adjacent ones of the dummy wiring layers 32 disposed next to one another in the column direction are offset by a width X10 in the row direction. The width X10 may preferably be about a half of the length of each edge of the dummy wiring layer 32.

(53) The dummy wiring layers 32 having the configurations described above provide at least the following effects. The effects obtained by the above-described configurations of the dummy wiring layers 32 will be described below with reference to FIG. 5.

(54) (1) For example, let us consider one case in which a restriction region 100 is provided in a manner shown in FIG. 5(a). The restriction region 100 includes a wiring effective region 90 and a prohibited area 80. The prohibited area 80 extends in the row direction about the wiring effective region 90. Let us consider one situation in which dummy wiring layers 32a in a lattice structure are formed in parallel with the restriction region 100. When the dummy wiring layers 32a are formed in a lattice structure in parallel with the restriction region 40, and if any one of the dummy wiring layers 32a in one of the rows of the lattice overlaps the restriction region 100, all the other dummy wiring layers 32a in the same row overlap the restriction region 100. In order to form dummy wiring layers 32a adjacent to the restriction region 100 while preventing the dummy wiring layers 32a from overlapping the restriction region 100, the location of the dummy wiring layers 32a needs to be controlled. Such a control is technically difficult because it may cause a substantial increase in the amount of data for generating masks. On the other hand, when dummy wiring layers 32a cannot be formed adjacent to the restriction region 100, the density of the dummy wiring layers 32a formed in an area adjacent to the restriction region 100 becomes insufficient.

(55) However, in accordance with the embodiments of the present invention, as shown in FIG. 5(b), the dummy wiring layers 32 are disposed on the first virtual linear lines L1 that extend in a direction traversing the row direction. In other words, adjacent ones of the dummy wiring layers 32 disposed next to one another on the same one of the first virtual linear lines L1 are mutually offset in the column direction. As a result, even when one of the dummy wiring layers 32 disposed on one of the first virtual linear lines L1 overlaps the restriction region 100, the next one of the dummy wiring layers 32 on the same first virtual linear line L1 can be disposed without overlapping the restriction region 100. As a result, the dummy wiring layers 32a can be securely formed in an area adjacent to the restriction region 100 without substantially controlling the locations where the dummy wiring layer 32 are formed.

(56) Also, in accordance with the embodiments of the present invention, the dummy wiring layers 32 are disposed on the second virtual linear lines L2 that extend in a direction traversing the column direction. In other words, adjacent ones of the dummy wiring layers 32 disposed next to one another on the same one of the second virtual linear lines L2 are mutually off set in the row direction. As a result, even when one of the dummy wiring layers 32 disposed on one of the second virtual linear lines L2 overlaps the restriction region 100, the next one of the dummy wiring layers 32 on the same second virtual linear line L2 can be disposed without overlapping the restriction region 100. Accordingly, the dummy wiring layers 32 can be securely formed in areas adjacent to the restriction region 100 that extends in the column direction.

(57) (2) In the semiconductor device in accordance with the embodiments of the present invention, dummy wiring layers 32 that partially overlap a restriction region 100 are entirely eliminated. As a result, the following effects are obtained

(58) If dummy wiring layers 32 partially overlap a restriction region 100, portions (hatched areas) 32b of the dummy wiring layers 32 do not overlap the restriction region 100. The portions 32b are hereafter referred to as hangover dummy wiring layers. The hangover dummy wiring layer 32b has a shape in plan view that lacks a portion of the plan shape of the original dummy wiring layer 32. In other words, the hangover dummy wiring layer 32b has a smaller plan area compared to a plan area of the original dummy wiring layer 32. When the hangover dummy wiring layer 32b is extremely small in plan area (for example, when it is smaller than the resolution limit or the design rule), the following problems may occur.

(59) (a) A resist layer to define the hangover dummy wiring layers 32b is difficult to form, and pattern skipping of the pattern for the hangover dummy wiring layers 32b occurs. (b) Even if a resist layer to define the hangover dummy wiring layers 32b is formed, the resist layer may fall. The fallen resist layer becomes dusts in an etching step to form the first wiring layers 30, and therefore deteriorates the etching step. (c) Convex portions of the hangover dummy wiring layers 32b are very narrow, and therefore may break in a washing step to be conducted after the wiring layers are patterned. The broken convex portions become foreign particles that may remain on the surface of the substrate. (d) If the foreign particles on the surface enter a dielectric layer, wiring layers may become short-circuited.

(60) In accordance with the embodiments of the present invention, any hangover dummy wiring layers 32b are not formed. As a result, the occurrence of the problems described above is securely prevented.

(61) One example of a method for generating mask data is described below. The mask data is used for forming first wiring layers and dummy wiring layers. The mask data can be generated using a computer. FIG. 13 shows a pattern representing a mask data set.

(62) First, data for a first mask is generated. FIG. 9 shows a pattern representing first mask data 200. Restriction region patterns 242 that define restriction regions are set in the first mask data 200. In one embodiment, the first mask data 200 is formed in a manner described below. FIGS. 6-8 show steps of forming the first mask data that include intermediate mask data sets.

(63) Initially, first and second intermediate mask data 210 and 220, which represent regions shown in FIGS. 6(a) and 6(b), respectively, are prepared.

(64) Wiring patterns 212 are defined in the first intermediate mask data 210 in a manner shown in FIG. 6(a). The wiring patterns 212 define first wiring layers. A second contact hole pattern 222 is defined in the second intermediate mask data 220 in a manner shown in FIG. 6(b). The second contact hole pattern 222 defines a second contact hole.

(65) Then, a logical sum of the first and second intermediate mask data 210 and 220 is made to obtain third intermediate mask data 230 shown in FIG. 7. In other words, the hatched regions 212 and 222 of the first and second intermediate mask data 210 and 220 are added to define wiring effective region patterns 232 in the third intermediate mask data 230. The wiring effective region patterns 232 define wiring effective regions.

(66) Then, the wiring effective region patterns 232 are expanded by a specified width to obtain fourth intermediate mask data 240 shown in FIG. 8. In other words, prohibited area patterns 244 are added around the wiring effective region patterns 232 to set the restriction region patterns 242. The prohibited area patterns 244 define prohibited areas. The restriction region patterns 222 define restriction regions.

(67) Then, the fourth intermediate mask data 240 is diagrammatically reversed to obtain the first mask data 200 shown in FIG. 9. More particularly, the hatched regions in the fourth intermediate mask data 240 are changed to blank regions, and the blank regions in the fourth intermediate mask data 240 are replaced with hatched regions, to generate the first mask data 200.

(68) Next, second mask data 300 is formed. FIG. 10 shows a pattern representing the second mask data 300. Dummy patterns 310 are defined in the second mask data 300. The dummy patterns 310 correspond to the patterns of the above-described dummy wiring layers 32 and thus define the dummy wiring layers 32. In other words, the dummy patterns 310 and placement patterns of the dummy wiring layers 32 are identical or approximate to one another. More particularly, as shown in FIG. 11, when a mask 600 having dummy patterns 610 is formed based on the second mask data 300, the dummy patterns 610 of the mask 600 correspond to the patterns of the dummy wiring layers 32 to be formed in a semiconductor device 700.

(69) In a preferred embodiment, the dummy patterns 310 are disposed in the following manner.

(70) The dummy patterns 310 are formed in a manner to be located on first virtual linear lines L10. The dummy patterns 310 can be formed in a manner that centers of the dummy patterns 310 are located on the first virtual linear lines L10. Also, the dummy patterns 310 can be formed in a manner that portions other than the centers of the dummy patterns 310 are located on the first virtual linear lines L10. In other words, the dummy patterns 310 are accepted as long as they are located on the first virtual linear lines L10.

(71) The dummy patterns 310 are formed in a manner to be located on second virtual linear lines L20. The dummy patterns 310 may be formed in a manner that centers of the dummy patterns 310 are located on the second virtual linear lines L20. Also, the dummy patterns 310 may be formed in a manner that portions other than the centers of the dummy patterns 310 are located on the second virtual linear lines L20. In other words, the dummy patterns 310 are accepted as long as they are located on the second virtual linear lines L20.

(72) The first virtual linear lines L10 traverse the row direction. The first virtual linear lines L10 and the row direction define an angle 10 that is 2-40 degrees. Preferably, the angle 10 is 15-25 degrees. More preferably, the angle 10 is about 20 degrees. The row direction used here refers to one direction that is virtually defined in view of, for example, the wiring patterns, the second contact hole pattern, and the prohibited area patterns.

(73) The second virtual linear lines L20 traverse the column direction. The second virtual linear lines L20 and the column direction define an angle 20 that is 2-40 degrees. Preferably, the angle 20 is 15-25 degrees. More preferably, the angle 20 is about 20 degrees. The column direction used here refers to one direction that perpendicularly traverses the row direction and is virtually defined in view of, for example, the wiring patterns, the second contact hole pattern, and the prohibited area patterns.

(74) The first virtual linear lines L10 are defined in plurality. The first virtual linear lines L1 are defined to be separated from one another at a specified pitch. The second virtual linear lines L2 are defined in plurality. The second virtual linear lines L2 are defined to be separated from one another at a specified pitch. A gap D10 between adjacent ones of the first virtual linear lines L10 is set such that a gap D1 between adjacent ones of the first virtual linear lines L1 in a semiconductor device acquires a designed amount (see FIG. 11). Also, a gap D20 between adjacent ones of the second virtual linear lines L20 is set such that a gap D2 between adjacent ones of the second virtual linear lines L2 in the semiconductor device acquires a designed amount (see FIG. 11).

(75) It is noted that the second mask data 300 can be formed before the first mask data 200 is formed.

(76) Next, the first mask data 200 and the second mask data 300 are mixed to form a third mask data 400. FIG. 12 shows a pattern representing the third mask data 400. For example, the first and second mask data 200 and 300 can be mixed in the following manner. Common areas of the hatched regions in the first mask data 200 and the dummy patterns (hatched regions) 310 of the second mask data 300 are extracted. In other words, the dummy patterns 310 that overlap the restriction region patterns 242 are excluded. It is noted that the dummy patterns 312 that partially overlap the restriction region patterns 242 are also entirely excluded.

(77) Then, a logical sum of the third mask data 400 and the first intermediate mask data 210 is obtained. In other words, the wiring patterns (hatched regions) 212 of the first intermediate mask data 210 are added to the third mask data 400. As a result, mask data 500 shown in FIG. 13 is obtained for a mask that is used to form the first wiring layers and the dummy wiring layers.

(78) When a positive type resist is used for patterning the wiring layers, the hatched regions of the mask data 500 represent shading portions of the mask (for example, chrome patterns). When a negative type resist is used, regions other than the hatched regions (i.e., blank regions) of the mask data 500 represent shading portions of the mask (for example, chrome patterns).

(79) The mask data 500 thus obtained can be recorded in a computer readable recording media if required. Also, a mask that is used to form the first wiring layers and the dummy wiring layers can be obtained based on the mask data 500.

(80) In the method for generating mask data in accordance with the embodiments of the present invention, the dummy patterns 310 correspond to placement patterns of the dummy wiring layers 32 as described above. As a result, for the same reasons described above in conjunction with the effects of the semiconductor device in accordance with the embodiment of the present invention, the dummy patterns 310 can be securely generated in areas adjacent to the restriction regions 24 without controlling placement positions of the dummy patterns 310. In other words, the dummy patterns 310 can be automatically generated in areas adjacent to the restriction region patterns 242. As a result, when a mask is obtained by the method for generating mask data in accordance with the embodiments of the present invention, and such a mask is used to form dummy wiring layers, the dummy wiring layers can be securely formed in areas adjacent to restriction regions. Accordingly, when a dielectric layer formed over the wiring layers is polished, the polishing pressure is securely distributed on the dummy wiring layers in areas adjacent to the restriction regions.

(81) Also, the dummy patterns 310 that at least partially overlap the restriction region patterns 242 are entirely excluded. As a result, the generation of pattern skipping of patterns of dummy wiring layers can be securely prevented.

(82) Furthermore, since the dummy patterns 310 can be securely set in areas adjacent to the restriction region patterns 242, the dummy patterns 310 can also be securely set in regions where gaps between adjacent restriction region patterns 242 are narrow.

(83) In accordance with the embodiments of the present invention, the step of generating the first mask data 200 includes the step of diagrammatically reversing the fourth intermediate mask data 240. However, depending on software used for generating mask data, the step of diagrammatically reversing the fourth intermediate mask data 240 may not necessarily be included.

(84) Next, a method for manufacturing a semiconductor device in accordance with an embodiment of the present invention will be described. FIGS. 14 and 15 schematically show cross sections of a semiconductor device in manufacturing process steps.

(85) (1) Referring to FIG. 14(a), semiconductor elements (for example, MOSFETs), wiring layers, and element isolation regions (not shown) are formed over a silicon substrate 10 by a known method.

(86) Then, a first interlayer dielectric layer 20 is formed over the semiconductor substrate 10. The first interlayer dielectric layer 20 may be formed in the same manner as a second interlayer dielectric layer 40 (to be described below) is formed. The thickness of the first interlayer dielectric layer 20 is not limited to a specific range. For example, the thickness of the first interlayer dielectric layer 20 is about 300 nm-1000 nm. The first interlayer dielectric layer 20 can be planarized by a chemical-mechanical polishing (CMP) method depending on requirements.

(87) Contact holes (not shown) are formed in the first interlayer dielectric layer 20. For example, the contact holes are formed by an anisotropic reactive ion etching. Contact layers (not shown) are formed in the contact holes by a known method. The contact layers are formed from, for example, tungsten plugs or aluminum alloy layers.

(88) A conductive layer 36 is formed over the first interlayer dielectric layer 20. The conductive layer 36 is not limited to a specific material. For example, an alloy of aluminum and copper, titanium nitride, titanium can be used for the conductive layer 36. The conductive layer 36 may be formed by an appropriate method, for example, a sputtering method. The thickness of the conductive layer 36 may be appropriately selected depending on device designs. For example, the thickness of the conductive layer 36 is about 50-700 nm.

(89) Next, a resist layer R1 is formed over the conductive layer 36.

(90) (2) Then, the resist layer R1 is exposed and developed to thereby pattern the resist layer R1 as shown in FIG. 14(b). A mask that is used for exposing the resist layer R1 is manufactured based on the mask data obtained by the method for generating mask data in accordance with the present invention. It is noted that an area above a forming region where a second contact hole 70 is to be formed is not opened.

(91) (3) Then, as shown in FIG. 14(c), the conductive layer 36 is etched using the resist layer R1 to thereby form first wiring layers 30 and dummy wiring layers 32 having specified patterns.

(92) Then, as shown in FIG. 15(a), a dielectric layer 42 is formed over the first interlayer dielectric layer 20, the first wiring layers 30 and the dummy wiring layers 32. The dielectric layer 42 may be formed from, for example, silicon oxide. When the dielectric layer 42 is formed from silicon oxide, the silicon oxide may contain phosphorous, boron or the like. The dielectric layer 42 may be formed by, for example, a CVD method, a coating method. The thickness of the dielectric layer 42 is not limited to a specific range or value. For example, the thickness of the dielectric layer 42 is about 500-2000 nm.

(93) Then, the dielectric layer 42 is polished by a CMP method to planarize the dielectric layer 42 to form a second interlayer dielectric layer 40 shown in FIG. 15(b). The thickness of the resultant second interlayer dielectric layer 40 may vary depending on device designs, and may be, for example, 200-600 nm. The following effects are achieved when the dielectric layer 42 is planarized. Namely, the dummy wiring layers 32 are formed with the placement pattern that is described above in connection with the semiconductor device in accordance with the embodiment of the present invention. Accordingly, the dummy wiring layers 32 are securely formed in areas adjacent to the restriction regions. As a result, the polishing pressure can be more securely distributed over the dummy wiring layers 32 to the extent that the dummy wiring layers 32 are more securely formed in areas adjacent to the restriction regions. Thus, the polishing pressure can be better prevented from concentrating on the isolated first wiring layer 30, and therefore the dielectric layer 42 over the isolated first wiring layer 30 can be better prevented from being excessively cut. As a result, the second interlayer dielectric layer 40 can be better planarized.

(94) Then, as shown in FIG. 2, second contact holes 70 (only one contact hole is shown in the figure) are formed in the first and second interlayer dielectric layers 20 and 40 at specified regions by photolithography and etching methods. Then, second contact layers 72 are formed in the second contact holes 70.

(95) Then, first contact holes 60 (only one contact hole is shown in the figure) are formed in the second interlayer dielectric layer 40 at specified regions by photolithography and etching methods. Then, first contact layers 62 are formed in the first contact holes 60.

(96) Next, a conductive layer is formed over the second interlayer dielectric layer 40, and the conductive layer is patterned to form second wiring layers 50, whereby a semiconductor device 1000 is completed.

(97) Effects of the method for manufacturing semiconductor devices in accordance with the embodiment of the present invention will be described.

(98) By the method for manufacturing a semiconductor device in accordance with the embodiment of the present invention, the dummy wiring layers 32 are formed with the same pattern of the dummy wiring layers 32 described above in conjunction with the structure of the semiconductor device. Accordingly, the dummy wiring layers 32 are securely formed in areas adjacent to the restriction regions. As a result, when the dielectric layer 42 is polished, the dielectric layer 42 over the isolated wiring layer 30 can be better prevented from being excessively cut. Thus, the second interlayer dielectric layer 40 can have a more uniform thickness.

(99) Experiments are conducted to show how patterns of dummy wiring layers change the formation of the dummy wiring layers between wiring effective regions.

(100) Conditions for embodiment samples will be described below.

(101) (1) In accordance with one embodiment of the present invention, in an embodiment sample, placement patterns of dummy wiring layers are made according to the following rule:

(102) (a) An angle between the first virtual linear lines and the row line is about 18.4 degrees.

(103) (b) A gap between the adjacent first virtual linear lines is about 3.2 m.

(104) (c) An angle between the second virtual linear lines and the column line is about 18.4 degrees.

(105) (d) A gap between the adjacent second virtual linear lines is about 3.2 m.

(106) (e) A ratio of an area of the dummy wiring layers occupied in a unit area is 40%.

(107) (f) A shape of each of the dummy wiring layers in plan view is square.

(108) (g) Each side of each of the dummy wiring layers in plan view has a length of 2 m.

(109) (h) A gap between opposing sides of adjacent ones of the dummy wiring layers disposed next to one another on the same one of the first virtual linear lines is 1 m.

(110) (i) A gap between opposing sides of adjacent ones of the dummy wiring layers disposed next to one another on the same one of the second virtual linear lines is 1 m.

(111) (j) An offset width in the column direction between opposing sides of adjacent ones of the dummy wiring layers disposed next to one another on the same one of the first virtual linear lines is 1 m.

(112) (k) An offset width in the row direction between opposing sides of adjacent ones of the dummy wiring layers disposed next to one another on the same one of the second virtual linear lines is 1 m.

(113) (l) The dummy wiring layers are formed such that their centers are located on the first virtual linear lines.

(114) (m) The dummy wiring layers are formed such that their centers are located on the second virtual linear lines.

(115) (n) Any dummy wiring layers that may entirely or partially overlap restriction regions 100 (including dummy wiring layers connecting to restriction regions) are excluded.

(116) (2) The restriction regions 100 include wiring effective regions (wiring layers) 90 and prohibited areas 80 provided around the wiring effective regions (wiring layers) 90.

(117) (3) The width of each of the prohibited areas 80 is 1 m.

(118) A region A10 and a region B10 are set. In the region A10, a gap between adjacent ones of the wiring effective regions (i.e., the wiring layers) 90 is 10 m. In the region B10, a gap between adjacent ones of the wiring effective regions (i.e., the wiring layers) 90 is 6 m.

(119) Conditions for comparison samples will be described below.

(120) (1) In a comparison sample, dummy wiring layers are disposed in the form of a lattice. More particularly, the dummy wiring layers are disposed according to the following rule:

(121) (a) A gap between adjacent ones of the dummy wiring layers disposed next to one another in the row direction is 1 m.

(122) (b) A gap between adjacent ones of the dummy wiring layers disposed next to one another in the column direction is 1 m.

(123) (c) A shape of each of the dummy wiring layers in plan view is square.

(124) (d) Each side of each of the dummy wiring layers in plan view has a length of 2 m.

(125) (e) Any dummy wiring layers that may entirely or partially overlap restriction regions 100 (including dummy wiring layers connecting to the restriction regions) are entirely excluded.

(126) (2) The restriction regions 100 include wiring effective regions 90 and prohibited areas 80 provided around the wiring effective regions 90.

(127) (3) The width of each of the prohibited areas 80 is 1 m.

(128) (4) The same patterns as those of the embodiment samples are used for patterns of the wiring effective regions (i.e., the wiring layers) 90. A region of the comparison sample corresponding to the region A10 of the embodiment sample is presented as B10, and a region of the comparison sample corresponding to the region A20 of the embodiment sample is presented as B20.

(129) Comparison results are shown in FIGS. 16 and 17. FIG. 16 shows a plan view of wiring effective regions (wiring layers) and dummy wiring layers of the embodiment sample of the present invention. FIG. 17 shows a plan view of wiring effective regions (wiring layers) and dummy wiring layers of the comparison sample. In the figures, squares shown by solid lines indicate dummy wiring layers that are actually formed, and squares shown by broken lines indicate virtual dummy wiring layers that are excluded.

(130) In the comparison example shown in FIG. 17, only one line of the dummy wiring layers is formed in the region A20. In other words, dummy wiring layers are not formed adjacent to the restriction regions 100. In contrast, as shown in FIG. 16, in accordance with the embodiment of the present invention, the dummy wiring layers are securely formed in the region A10 in areas adjacent to the restriction regions 100.

(131) Also, in the embodiment sample of the present invention shown in FIG. 16, the dummy wiring layers are formed in an area where the gap between the wiring effective regions (i.e., the wiring layers) is narrow (see the region B10). In contrast, in the comparison example shown in FIG. 17, dummy wiring layers are not formed in an area where the gap between the wiring effective regions (i.e., the wiring layers) is narrow (see the region B20).

(132) It is understood from the above that the embodiment sample of the present invention more securely form dummy wiring layers adjacent to restriction regions 100 compared to the comparison example.

(133) The present invention is not limited to the embodiments described above, and many modifications can be made within the scope of the subject matter of the present invention.

(134) (1) In the embodiments described above, the dummy wiring layers 32 are formed in a manner that their centers are disposed on the first virtual linear lines L1. However, the dummy wiring layers 32 may be formed in a manner that portions other than their centers are disposed on the first virtual linear lines L1. In other words, it is acceptable if the dummy wiring layers 32 may be disposed on the first virtual linear lines L1.

(135) (2) In the embodiments described above, the dummy wiring layers 32 are formed in a manner that their centers are disposed on the second virtual linear lines L2. However, the dummy wiring layers 32 may be formed in a manner that portions other than the centers of the dummy wiring layers 32 are disposed on the second virtual linear lines L2. In other words, it is acceptable if the dummy wiring layers 32 may be disposed on the second virtual linear lines L2.

(136) (3) In the embodiments described above, the dummy wiring layers 32 are formed over the first interlayer dielectric layer 20. However, the present invention is not limited to this embodiment. The dummy wiring layers 32 may be formed over a second interlayer dielectric layer or above.

(137) (4) In the embodiments described above, the second contact hole 70 formed in the first interlayer dielectric layer 20 and the second interlayer dielectric layer 40 defines a wiring effective region. However, the present invention is not limited to this embodiment. For contact holes that pass through a plurality of interlayer dielectric layers, wiring effective regions for the contact holes may be defined in a wiring layer provided between the plurality of interlayer dielectric layers. In other words, for example, when an upper wiring layer is formed in a layer above dummy wiring layers, another lower wiring layer is formed in a layer below the dummy wiring layers, and a contact hole for connecting the upper wiring layer and the lower wring layer, a region where the contact hole is formed is defined as a wiring effective region at the level where the dummy wiring layers are formed.

(138) While the description above refers to particular embodiments of the present invention, it will be understood that many modifications may be made without departing from the spirit thereof. The accompanying claims are intended to cover such modifications as would fall within the true scope and spirit of the present invention.

(139) The presently disclosed embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims, rather than the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.