Hybrid integrated semiconductor tri-gate and split dual-gate FinFET devices and method for manufacturing

Abstract

A method for making a tri-gate FinFET and a dual-gate FinFET includes providing a semiconductor on insulator (SOI) wafer having a semiconductor layer over an insulator layer. The method further includes forming a hard mask on the semiconductor layer and patterning the hard mask to form first and second cap portions. The method also includes etching the semiconductor layer to form first and second fins using the first and second cap portions as an etch mask. The method also includes removing the second cap portion to expose the top surface of the second fin and forming a gate dielectric layer on the first and second fins. The method further includes forming a conductive layer over the gate dielectric layer, selectively etching the conductive layer to form first and second gate structures, forming an interlayer dielectric layer over the gate structures, and planarizing the interlayer dielectric layer using the first cap portion as a polish stop.

Claims

1. A method for fabricating an integrated circuit having at least a tri-gate FinFET and a dual-gate FinFET, the method comprising: providing a semiconductor on insulator (SOI) substrate, the SOI substrate comprising a semiconductor layer overlying an insulator layer, the semiconductor layer having a surface region; implanting impurities into the semiconductor layer for a threshold voltage adjustment; forming a hard mask overlying the surface region; patterning the hard mask to form a first hard mask cap portion and a second hard mask cap portion; etching the semiconductor layer using the patterned hard mask as an etch mask to form a first fin and a second fin and expose a contiguous surface of the insulator layer between the first and second fins; removing the second hard mask cap portion overlying the second fin; forming a gate dielectric layer over side surfaces of the first fin and side surfaces and a top surface of the second fin while leaving the first hard mask cap portion uncovered; forming a conductive layer overlying the gate dielectric layer, the conductive layer in direct contact with the first hard mask cap portion and with the exposed contiguous surface of the insulator layer; selectively etching the conductive layer using a photolithographic and etch process to form a first gate structure covering the first hard mask cap portion on the first fin and the side surfaces the first fin and a second gate structure covering the top surface and the side surfaces the second fin; forming an interlayer dielectric layer overlying the first and second gate structures; and removing a top portion of the first and second gate structures by chemical mechanical polishing (CMP) using the first hard mask cap portion as a polish stop, such that the first gate structure is separated into a first gate electrode and a second gate electrode covering the side surfaces of the first fin to form the dual-gate FinFET, and the second gate structure covers the top surface and the side surfaces of the second fin to form the tri-gate FinFET.

2. The method of claim 1, wherein the insulator layer comprises silicon dioxide and the semiconductor layer comprises silicon.

3. The method of claim 1, wherein forming the conductive layer comprises an atomic layer deposition process.

4. The method of claim 1, wherein the first fin has a rectangular cross-section with a width in a range between about 5 nm and about 50 nm and a height in a range between about 5 nm and about 100 nm.

5. The method of claim 1, wherein the second fin has a rectangular cross-section with a width in a range between about 5 nm and about 50 nm and a height in a range between about 5 and about 100 nm.

6. The method of claim 1, wherein forming the first and second fins further comprising annealing in an H.sub.2 ambient at a temperature ranging from about 800 C. to about 1000 C.

7. The method of claim 1, wherein selectively etching the conductive layer comprises: providing an etch mask; patterning the etch mask; etching the conductive layer; and removing the etch mask.

8. The method of claim 1 further comprising: forming elevated source and drain regions; and forming a SiGe layer on the elevated source and drain regions by selective epitaxial growth at a temperature of about 700-800 C. in an ambient of SiH.sub.2Cl.sub.2+HCl+GeH.sub.4.

9. The method of claim 8, wherein the SiGe layer has a thickness of about 100 nm to about 500 nm and a germanium content of about 10-30%.

10. The method of claim 1 further comprising: forming contact regions, the contact regions comprising tungsten plugs; and forming interconnects, the interconnects comprising copper interconnect lines.

11. The method of claim 1, wherein the second gate structure contacts at least three surfaces of the second fin.

12. The method of claim 1, wherein the first gate structure comprises a first gate electrode and a second electrode, the first and second electrodes being disposed on opposite sides of the first fin and electrically insulated from each other.

13. The method of claim 1, wherein the first fin is disposed in a core region and the second fin is disposed in an input/output region.

14. The method of claim 1, wherein the hard mask is one of SiN, SiO.sub.2, and SiON.

15. The method of claim 1, wherein the gate dielectric layer comprises one of HfO.sub.2, ZrO.sub.2, La.sub.2O.sub.3, Al.sub.2O.sub.3, TiO.sub.2, SrTiO.sub.3, LaAlO.sub.3, Y.sub.2O.sub.3, HfO.sub.xN.sub.y, ZrO.sub.xN.sub.y, La.sub.2O.sub.xN.sub.y, Al.sub.2O.sub.xN.sub.y, TiO.sub.xN.sub.y, SrTiO.sub.xN.sub.y, LaAlO.sub.xN.sub.y, and Y.sub.2O.sub.xN.sub.y, wherein x and y are integer.

16. The method of claim 1, wherein the conductive layer comprises one of W, Ta, TiN, ZrN, HfN, VN, NbN, TaN, WN, TiAlN, TaC, TaMgC, and TaCN.

17. The method of claim 1, wherein the tri-gate FinFET has a source/drain region disposed at a distal end of the first fin and the dual-gate FinFET has a source/drain region disposed at a distal end of the second fin.

18. The method of claim 17, wherein the source/drain region of the tri-gate FinFET comprises SiGe.

19. The method of claim 17, wherein the source/drain region of the dual-gate FinFET comprises SiGe.

20. The method of claim 1, wherein forming the gate dielectric layer comprises: forming an oxide layer having a thickness in a range between about 0.1 nm and about 3 nm with in situ steam-generated (ISSG) or rapid thermal oxidation (RTO) at a temperature in a range between about 700 C. and about 900 C.; submitting the oxide layer to a decoupled plasma nitridation (DPN) process in a nitrogen ambient to form a nitrided oxide layer; and annealing the nitrided oxide layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain embodiments of the invention.

(2) FIG. 1A is a simplified cross-sectional view diagram of a split dual-gate FinFET device according to an embodiment of the present invention;

(3) FIG. 1B is a simplified cross-sectional view diagram of a tri-gate FinFET device according to an embodiment of the present invention;

(4) FIG. 2 is a simplified top view layout diagram for a dual-gate FinFET device and a tri-gate FinFET device according to an embodiment of the present invention;

(5) FIG. 3 is a simplified flowchart diagram of a method for making a dual-gate FinFET device and a tri-gate FinFET device according to an embodiment of the present invention;

(6) FIGS. 4-10 and FIGS. 11, 11A-D, 12A, 12B, 13A, 13B, 14A, 14B, 15A, and 15B are simplified cross-sectional view diagrams of a method for making a dual-gate FinFET device and a tri-gate FinFET device according to an embodiment of the present invention; and

(7) FIG. 16 is a simplified diagram of current voltage curves of a tri-gate FinFET according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

(8) Embodiments of the present invention relate to integrated circuits and the processing for the manufacture of semiconductor devices. More particularly, embodiments of the present invention provide a method and device for providing a dual-gate FinFET and a tri-gate FinFET on the same SOI substrate. Merely by way of example, the invention has been applied to high current drive I/O devices and low leakage core logic devices in integrated circuits. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to integrated circuits requiring devices having different threshold voltages and performance requirements.

(9) Depending upon the embodiment, the present invention includes various features, which may be used. These features include the following:

(10) 1. Simultaneous fabrication of tri-gate and dual-gate FinFETs on a same substrate;

(11) 2. Fabrication method using conventional process and equipment; and

(12) 3. Method for using tri-gate FinFETs in I/O circuits and dual-gate FinFETs in core logic circuits.

(13) As shown, the above features may be included in one or more of the embodiments to follow. These features are merely examples, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

(14) FIG. 1A is a simplified diagram of a dual-gate FinFET device 101 according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. As shown, dual-gate FinFET device 101 includes a substrate 110, and an insulator layer 120 overlying the substrate. In an embodiment, substrate 110 may comprise silicon, and insulator layer 120 may comprise silicon oxide. Dual-gate FinFET 101 also includes a silicon fin region 130 on the insulator layer 120. In a specific embodiment, silicon fin region 130 is a rectangular block of silicon characterized by a thickness or height of about 5 nm to about 100 nm and a width of about 5 nm to about 50 nm.

(15) The dual-gate FinFET 101 also includes gate oxide regions 131 and 132 disposed on the sides of the silicon fin region. A gate region 150 is disposed on one side of the silicon fin region and is separated from the silicon fin region by gate oxide region 131. A gate region 151 is disposed on an opposing side of the silicon fin region and is separated from the silicon fin region by gate oxide region 132. An end portion of silicon fin region 130 includes a source region 140, and the opposing end portion of the silicon fin region includes a drain region 160. As shown, gate region 150, gate oxide 131 and silicon fin region 130 are associated with an MOS transistor, which also includes a source region 140 and a drain region 160 at its distal ends. Gate 150 is characterized by a width 152 which is associated with a channel length of the transistor. In an embodiment, the channel length is about 5-30 nm. In an embodiment, source region 140 and drain region 160 disposed at the distal ends of the silicon fin region may include silicon germanium (SiGe). In another embodiment, source region 140 and drain region 160 disposed at the distal ends of the silicon fin region may include silicon carbide (SiC).

(16) Referring still to FIG. 1A, a second MOS transistor is formed with gate region 151, gate oxide 132, silicon fin region 130, source region 140 and drain region 160. In an embodiment, the silicon fin has a thickness (height) in a range between about 5 nm to about 100 nm. Each MOS transistor has a front gate that controls the conductivity of its channel and a back gate that controls the body potential of the transistor. As shown, an insulator region 155 lies above the top surface of silicon fin region 130. The insulator region separates gate region 150 from gate region 151. Therefore, gate 150 and gate 151 can be independently biased to control current flow in the fin channel, and allow device characteristics such as threshold voltage and sub-threshold swing (SS) to be adjusted for specific applications. In some embodiments, the dual gates can be used to dynamically modulate the characteristics of the FinFET, i.e., a control signal derived from a part of the circuit can be applied to one of the dual gates to modulate the current flow and affect the behavior of the dual-gate FinFET. As an example, the dual-gate FinFET can be utilized in core logic circuits applications which demand low leakage current.

(17) FIG. 1B is a simplified diagram of a single-gate or tri-gate FinFET device 102 according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. As shown in FIG. 1B, single-gate FinFET device 102 includes similar device elements as in dual-gate FinFET 101, e. g., substrate 110, insulator layer 120, silicon fin 130, gate oxide regions 131 and 132, source region 140, drain region 160, and gate region 150. However, FinFET 102 has a single continuous gate region 150 which is disposed on three sides (i.e., opposite sides and the top surface) of silicon fin 130 and is separated from the silicon fin by gate oxide regions 131, 132, and 133. Therefore, an MOS transistor is formed with gate region 150 modulating a bias voltage on three sides of the fin channel. The single-gate or tri-gate FinFET is capable of providing large current drive thank to the wide effective channel width provided by the three sides of the silicon fin. Such large current drive is advantageous in, for example, I/O circuit applications.

(18) In an embodiment of the present invention, a dual-gate FinFET device and a single-gate FinFET device are provided on the same substrate. In an embodiment, an integrated circuit chip includes single-gate FinFETs in I/O circuits and dual-gate FinFETs in core logic circuits. Of course, one of ordinary skill in the art would recognize other variations, modifications, and alternatives.

(19) FIG. 2 is a simplified top view layout diagram for a dual-gate FinFET 201 device and a tri-gate FinFET 202 device according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. As shown, dual-gate FinFET 201 includes a silicon fin region 230, a source region 240, and a drain region 260. FinFET 201 also includes gate regions 250 and 251, separated by nitride region 255. In an embodiment, the channel width W is about 5-50 nm, and the channel length L is about 5 nm to about 30 nm. The widened areas for source, drain, and gates are used for contact formation. Also shown in FIG. 2, tri-gate FinFET 202 includes a silicon fin region 230, a source region 240, and a drain region 260. FinFET 202 also includes a single gate region 250. In an embodiment of FinFET 202, the channel width W is about 5-50 nm, and the channel length L is about 5-30 nm. In a specific embodiment, the channel width of the FinFET is larger than the channel length.

(20) A method for fabricating an integrated circuit device according to an embodiment of the present invention may be outlined as follows:

(21) 1. Provide a silicon on insulator (SOI) wafer having a semiconductor layer on an insulator layer and threshold voltage implant;

(22) 2. Form a hard mask overlying the semiconductor layer;

(23) 3. Pattern the hard mask to form a first cap portion and a second cap portion;

(24) 4. Etch the semiconductor layer using the patterned hard mask to form first and second fin regions;

(25) 5. Remove the second cap portion to expose the top surface of the second fin region;

(26) 6. Form a gate dielectric layer on opposite sides of the first silicon fin region and on three sides of the second fin region;

(27) 7. Deposit a conductive layer;

(28) 8. Selectively etch the conductive layer to form a first gate structure for the first fin region and a second gate structure for the second fin region;

(29) 9. Forming source/drain regions at distal ends of the first and second fin regions;

(30) 10. Form an interlayer dielectric layer over the conductive layer;

(31) 11. Planarize the interlayer dielectric layer by chemical mechanical polishing (CMP) using the first cap portion as a polish stop;

(32) 12. Form elevated source/drain regions; and

(33) 12. Perform a backend process.

(34) The above sequence of steps provides a method for fabricating an integrated circuit including a dual gate FinFET and a tri-gate FinFET according to an embodiment of the present invention. As shown, the method uses a combination of steps including a way of fabricating a dual gate FinFET and a single-gate (tri-gate) FinFET on the same SOI substrate. Other alternatives can also be provided where steps are added, one or more steps are removed, or one or more steps are provided in a different sequence without departing from the scope of the claims herein. Further details of the present method can be found throughout the present specification and more particularly below.

(35) To summarize the above steps, FIG. 3 is a simplified process flow diagram illustrating a method 300 for fabricating a dual-gate FinFET device and a tri-gate FinFET device according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. The processes in FIG. 3 will be discussed with reference to FIGS. 4-15.

(36) FIGS. 4 to 15 are simplified cross-sectional view diagrams of a method for fabricating a dual-gate FinFET device and a tri-gate FinFET device according to an embodiment of the present invention. These diagrams are merely examples, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. As shown, the method according to an embodiment of the invention starts by providing a silicon on insulator (SOI) substrate (process 310 in FIG. 3).

(37) FIG. 4 is a simplified cross-sectional view diagram of a method according to an embodiment of the present invention along cross section AA of FIG. 2. As shown in FIG. 4, the SOI substrate in an embodiment of the invention includes a silicon substrate 410, a silicon dioxide layer 420 overlying the silicon substrate, and a semiconductor layer 430 overlying the silicon dioxide layer. In an embodiment, the semiconductor layer 430 includes silicon. In an alternative embodiment, the semiconductor layer 430 may include silicon germanium (SiGe). In an embodiment, semiconductor layer 430 may have a thickness in a range between about 5 nm and 100 nm. Process 310 also includes performing threshold adjustment implant (Vt implant). In an embodiment, the channel doping is around 1-510.sup.18/cm.sup.3 for an N-type FinFET. In a specific embodiment, threshold adjustment implant is performed using boron containing impurities at a dose of 1-510.sup.12/cm.sup.2 and an implantation energy of 1-30 KeV. In other embodiments, a P-type FinFET receives N-type impurities such as arsenic or phosphorus at a dose of 1-510.sup.12/cm.sup.2 and implant energy of 1-20 KeV. These implant conditions are merely examples, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives.

(38) FIG. 5 is a simplified view diagram of a method according to an embodiment of the present invention. As shown in FIG. 5, the method includes (process 320) forming a hard mask 510 on semiconductor layer 430. In an embodiment, a hard mask may include a silicon nitride (SiN) layer that is deposited on semiconductor layer 430 at a temperature range of approximately 700-800 C. to a thickness of about 100-500 nm. In other embodiments, hard mask 510 may include silicon dioxide (SiO.sub.2) or silicon oxide nitride (SiON). Of course, there can be other variations, modifications, and alternatives.

(39) In process 330, the hard mask is patterned as shown in FIG. 6. FIG. 6 is a simplified cross-sectional view diagram of a method according to an embodiment of the present invention. In an embodiment, the SOI substrate includes a first region for core logic devices and a second region for I/O devices. In a specific embodiment, dual-gate FinFETs are provided in a core logic region, and tri-gate FinFETs are provided in an I/O circuit region. In process 330, the hard mask is patterned to form a first hard mask cap portion 610 and a second hard mask cap portion 620.

(40) In process 340, silicon fin regions are defined. Here, semiconductor layer 430 is etched using the patterned hard mask as an etch mask to form fin regions. In a specific embodiment, conventional reactive ion etching (RIE) process is used to etch semiconductor layer 430. FIG. 7 is a simplified cross-sectional view diagram of a method according to an embodiment of the present invention. FIG. 7 shows a first silicon fin region 710 under first hard mask cap portion 610 for a dual-gate FinFET device and a second silicon fin region 720 of a single-gate FinFET device under second hard mask cap portion 620.

(41) The method then proceeds to process 350 which removes second hard mask cap portion 620. Second hard mask cap portion 620 can be removed using techniques known in the art such as, for example, ME, wet or dry etching and the like. The silicon fin regions are then annealed in an H.sub.2 ambient at a temperature ranging from about 800 C. to about 1000 C. Silicon fin regions 710, 720 defined in process 340 are used as FET active areas, including source, channel, and drain regions, as will be discussed more in detail below. Of course, there can be other variations, modifications, and alternatives.

(42) FIG. 8 is a simplified cross-sectional view diagram of a method according to an embodiment of the present invention. In process 360, a gate dielectric layer is formed over the fin regions. As shown in FIG. 8, gate dielectric regions 811 and 812 are formed on the sides of silicon fin region 710 in the dual-gate FinFET region. A gate dielectric layer is formed on the surfaces of silicon fin region 720 in the single-gate FinFET region, identified as 821, 822, and 823. In an embodiment, process 360 includes the following steps:

(43) 1. Base oxide grow with in situ steam-generated (ISSG) or rapid thermal oxidation (RTO) at a temperature range of about 700 C. to 900 C. to a thickness of about 0.1-3 nm;

(44) 2. Decoupled Plasma nitridation (DPN) in a nitrogen ambient; and

(45) 3. Post nitridation anneal (PNA).

(46) In an embodiment, the gate dielectric layer includes one of HfO.sub.2, ZrO.sub.2, La.sub.2O.sub.3, Al.sub.2O.sub.3, TiO.sub.2, SrTiO.sub.3, LaAlO.sub.3, Y.sub.2O.sub.3, HfO.sub.xN.sub.y, ZrO.sub.xN.sub.y, La.sub.2O.sub.xN.sub.y, Al.sub.2O.sub.xN.sub.y, TiO.sub.xN.sub.y, SrTiO.sub.xN.sub.y, LaAlO.sub.xN.sub.y, and Y.sub.2O.sub.xN.sub.y, wherein x and y are integer, or other high-K dielectric materials. Of course, there can be other variations, modifications, and alternatives.

(47) In process 365, a conductive layer is deposited over the gate dielectric layer. In an embodiment, the conductive layer includes a metal material comprising one of W, Ta, TiN, ZrN, HfN, VN, NbN, TaN, WN, TiAlN, TaC, TaMgC, and TaCN, and an alloy thereof. The conductive layer can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), vacuum evaporation, and the like. In another embodiment, the conductive layer may include polysilicon. In yet another embodiment, the conductive layer may include conductive refractory metal nitrides. In an embodiment, the conductive layer may have a thickness in a range between about 100 nm to about 500 nm, and preferably in a range between about 40 nm and about 150 nm. FIG. 9 is a simplified cross-sectional view diagram illustrating a conductive layer 910 overlying gate dielectric regions 821, 822, 823 of second fin region 720, and gate regions 811, 812, and first cap portion 610 of first fin region 710 according to an embodiment of the present invention.

(48) A photolithographic and etch process is performed in process 370 to form gate structures for fin regions. As shown in FIG. 10, the conductive layer 910 is selectively etched to form a first gate structure 1010 for first fin region 710 and a second gate structure 1020 for second fin region 720.

(49) In process 375, a source/drain ion implantation is performed to form sources and drains in the fin regions on both distal ends of first and second fin regions 710 and 720. In an embodiment, the source/drain ion implantation may be performed prior to forming gate sidewall spacers. FIG. 11, similar to FIG. 2, is a simplified top view layout diagram according to an embodiment of the invention. FIG. 11 includes dashed line marked AA which extends through the gate electrode patterns of a dual-gate FinFET 1101 on the left and a tri-gate FinFET 1102 on the right. FIG. 11 also includes dashed lines BB extending through the first fin region of first FinFET 1101 on the left and dashed CC extending through the second fin region of a second FinFET 1102 on the right.

(50) In process 380, an interlayer dielectric layer 1130 is formed overlying first and second gate structures 1010 and 1020. FIG. 11A is a simplified cross-sectional view diagram of a method according to an embodiment of the present invention. In process 385, interlayer dielectric layer 1130 is planarized by chemical mechanical polish (CMP) using first hard mask cap portion 610 as a polish stop. As shown in FIG. 11B, after CMP, first gate structure 1010 is divided into a first gate electrode 1111 and a second gate electrode 1112, the first and second gate electrodes are electrically insulated from each other. In contrast, second gate structure 1020 is disposed continuously across second fin region 1102. In other words, second gate structure 1020 covers the top surface and side surfaces of second fin region 720 to form tri-gate FinFET 1102 on the right, whereas each of the gate electrodes 1111 and 1112 covers one side of the first fin region to form dual-gate FinFET 1101 on the left, as shown in FIG. 11.

(51) Referring still to FIG. 11B, the planarization process stops when the upper surface of first hard makes cap portion 610 is exposed. The CMP process thus divides first gate structure 1010 into two gate electrodes 1111 and 1112. The planarization process also divides interlayer dielectric layer 1130 into three portions 1131, 1132, and 1133 that are separated by first and second fin regions 710 and 720.

(52) FIG. 11C is a simplified cross-sectional view diagram of dual-gate FinFET 1101 along the BB direction of FIG. 11. As shown, first hard mask cap portion 610 is disposed on the top surface of first silicon fin region 710.

(53) FIG. 11D is a simplified cross-sectional view diagram of tri-gate FinFET 1102 along the CC direction of FIG. 11. As shown, second gate structure 1020 is disposed on gate dielectric layer 823 which is disposed on the top surface of silicon fin region 720.

(54) FIG. 12A is a simplified cross-sectional view diagram of dual-gate FinFET 1101 along the BB direction of FIG. 11 according to an embodiment of the invention. FIG. 12B is a simplified cross-sectional view diagram of tri-gate FinFET 1102 along the CC direction of FIG. 11 according to an embodiment of the invention. In an embodiment, the method of forming dual-gate and tri-gate FinFETs includes forming ONO (oxide-nitride-oxide) spacers. The method first performs gate nitridation, followed by an high temperature oxidation (HTO) offset process. The method then forms a nitride spacer. The method also includes forming HTO layer and RIE etching to form spacers 1210 as shown in FIGS. 12A and 12B. Of course, there can be other variations, modifications, and alternatives.

(55) The method also includes implanting impurities to form source regions 1310 and 1330, and drain regions 1320 and 1340 as shown in FIGS. 13A and 13B. FIG. 13A is a simplified cross-sectional view diagram of dual-gate FinFET 1101 along the BB direction of FIG. 11 according to an embodiment of the invention. FIG. 13B is a simplified cross-sectional view diagram of tri-gate FinFET 1102 along the CC direction of FIG. 11 according to an embodiment of the invention. For N-type FinFET, the source/drain implantation includes, for example, N-type impurities such as As, at a dose of about 1-510.sup.15/cm.sup.2 and an energy of less than 1.0 KeV. In specific embodiments, tilt angles of 1-30 degrees are used. For P-type FinFET, source/drain implantation includes P-type impurities such as boron at a dose of about 1-510.sup.15/cm.sup.2, and an energy of less than 1.0 KeV. In specific embodiments, tilt angles of 1-30 degrees are used. The method also includes performing spike anneal at a temperature range of about 1000-1100 degrees Celsius. Of course, there can be other variations, modifications, and alternatives.

(56) In specific embodiments, the method includes process 387 that forms elevated source/drain structures 1410, 1420, 1430, and 1440 as shown in FIGS. 14A and 14B. FIG. 14A is a simplified cross-sectional view diagram of dual-gate FinFET 1101 along the BB direction of FIG. 11 according to an embodiment of the invention. FIG. 14B is a simplified cross-sectional view diagram of tri-gate FinFET 1102 along the CC direction of FIG. 11 according to an embodiment of the invention. Where FinFETs 1101, 1102 are p-type FinFET, the formation of elevated source/drain structures 1410, 1420, 1430, and 1440 may include Selective Epitaxial Growth (SEG) of SiGe at a temperature range of about 700-800 C. in an ambient of SiH.sub.2Cl.sub.2+HCl+GeH.sub.4. In some embodiments, the SiGe layer may have a thickness of about 100-500 nm and a germanium (Ge) content of about 10-30%. In some embodiments, the SiGe layer is also doped with boron at a concentration of about 1-510.sup.20 cm.sup.3. Of course, there can be other variations, modifications, and alternatives.

(57) Alternatively, where FinFETs 1101, 1102 are n-type FinFET, silicon carbide can be epitaxially deposited on source/drain structures 1410, 1420, 1430, and 1440 using in-situ doping techniques. That is, impurities such as phosphorous (P) or arsenic (As) are introduced while the silicon carbide material grows. In an embodiment, a p-type impurity concentration can be in the range from about 110.sup.19 to about 110.sup.20 atoms/cm.sup.3. Of course, there can be other variations, modifications, and alternatives.

(58) In some embodiments of the present invention, the method also includes performing backend processing. As shown in FIGS. 15A and 15B, backend process 390 includes forming an interlayer dielectric (ILD) 1510 and contact structures such as 1520 and 1530 coupled to the elevated source/drain regions. FIG. 15A is a simplified cross-sectional view diagram of dual-gate FinFET 1101 along the BB direction of FIG. 11 according to an embodiment of the invention. FIG. 15B is a simplified cross-sectional view diagram of tri-gate FinFET 1102 along the CC direction of FIG. 11 according to an embodiment of the invention. In some embodiments, the contact structures are tungsten plugs. Process 312 also includes forming interconnects using copper and low k dielectrics. In a preferred embodiment, tri-gate (single-gate) FinFETs and dual-gate FinFETs are formed on the same chip.

(59) FIG. 16 is a simplified diagram of simulated current voltage curves of a single-gate (tri-gate) FinFET device according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. As shown, the simulated drain current of a 30 nm tri-gate FinFET device is plotted against gate voltage for drain biases of 0.8 V and 50 mV, respectively.

(60) A method for operating an integrated circuit device according to an embodiment of the present invention may be outlined as follows:

(61) 1. providing an SOI substrate;

(62) 2. providing a first circuit region in the SOI substrate;

(63) 3. providing a second circuit region in the SOI substrate;

(64) 4. forming a tri-gate FinFET in the first circuit region, the tri-gate FinFET comprising a drain electrode, a source electrode, and a gate electrode;

(65) 5. forming a dual-gate FinFET in the second circuit region, the dual-gate FinFET comprising a drain electrode, a source electrode, and a first gate electrode a second gate electrode;

(66) 6. applying a first bias voltage and second bias voltage to the drain electrode and the source electrode of the tri-gate FinFET, respectively;

(67) 7. receiving a first signal at the gate electrode of the tri-gate FinFET;

(68) 8. applying a third bias voltage and fourth bias voltage to the drain electrode and the source electrode of the dual-gate FinFET, respectively; and

(69) 9. receiving a second signal and a third signal at the first gate electrode and the second gate electrode of the tri-gate FinFET, respectively.

(70) In a specific embodiment, the tri-gate FinFET includes a channel region that is surrounded by the gate electrode on three sides. The dual-gate FinFET includes a channel region sandwiched between the first and second gate electrodes. In some embodiments, the first circuit region is an I/O region. In other embodiments, the second circuit region is a core logic region. In a specific embodiment, the third signal is a dynamic signal generated by another circuit. In some embodiments, the dual-gate FinFET is configured to be operated in a weak inversion region. Of course, there can be other variations, modifications, and alternatives.

(71) The above sequence of processes provides a method for operating an integrated circuit including a dual-gate FinFET and a tri-gate FinFET according to an embodiment of the present invention. As shown, the method uses a combination of steps including a way of operating a dual gate FinFET and a single-gate FinFET on the same SOI substrate. For example, in some embodiments, an integrated circuit chip includes single-gate FinFETs in I/O circuits and dual-gate FinFETs in core logic circuits. Of course, there can be other variations, modifications, and alternatives. Other alternatives can also be provided where steps are added, one or more steps are removed, or one or more steps are provided in a different sequence without departing from the scope of the claims herein.

(72) It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.