PSEUDO-SUBSTRATE WITH IMPROVED EFFICIENCY OF USAGE OF SINGLE CRYSTAL MATERIAL
20210050248 ยท 2021-02-18
Inventors
Cpc classification
Y10T156/1062
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
B32B9/04
PERFORMING OPERATIONS; TRANSPORTING
H01L21/185
ELECTRICITY
H01L27/1203
ELECTRICITY
B32B7/12
PERFORMING OPERATIONS; TRANSPORTING
C30B29/68
CHEMISTRY; METALLURGY
C30B33/00
CHEMISTRY; METALLURGY
Y10T428/24942
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
International classification
H01L21/762
ELECTRICITY
B32B7/12
PERFORMING OPERATIONS; TRANSPORTING
B32B9/04
PERFORMING OPERATIONS; TRANSPORTING
C30B29/68
CHEMISTRY; METALLURGY
C30B33/00
CHEMISTRY; METALLURGY
H01L21/02
ELECTRICITY
H01L21/18
ELECTRICITY
Abstract
The invention relates to a method for fabricating a pseudo-substrate comprising the steps of providing a single crystal ingot, providing a handle substrate, cutting a thin slice from the single crystal ingot, and attaching the thin slice to the handle substrate to form a pseudo-substrate. According to the invention, the thickness of the thin slice is substantially equal or inferior to a critical thickness below which the slice, if taken alone, is no longer mechanically stable. The invention further relates to a semiconductor structure.
Claims
1. A method for fabricating at least one pseudo-substrate, comprising: providing a single crystal ingot comprising a piezoelectric material; providing a bonding layer on a surface of the single crystal ingot without polishing the surface of the single crystal ingot; and transferring a thin piezoelectric layer of the single crystal ingot adjacent the bonding layer to a handle substrate, the bonding layer bonding the thin piezoelectric layer to the handle substrate; wherein a thickness of the thin piezoelectric layer is 300 m or less.
2. The method of claim 1, wherein the piezoelectric material comprises LiNbO.sub.3 or LiTaO.sub.3.
3. The method of claim 1, wherein transferring the thin piezoelectric layer of the single crystal ingot adjacent the bonding layer to the handle substrate comprises cutting the thin piezoelectric layer from the single crystal ingot.
4. The method of claim 3, wherein cutting the thin piezoelectric layer from the single crystal ingot comprises sawing the thin piezoelectric layer from the single crystal ingot.
5. The method of claim 1, wherein transferring the thin piezoelectric layer of the single crystal ingot adjacent the bonding layer to the handle substrate comprises separating the thin piezoelectric layer of the single crystal ingot from a remainder of the single crystal ingot, and subsequently bonding the bonding layer to the handle substrate.
6. The method of claim 1, wherein the handle substrate comprises a silicon substrate.
7. The method of claim 1, further comprising at least one of: polishing a surface of the thin piezoelectric layer on the pseudo-substrate; chamfering an edge of the pseudo-substrate; and forming a flat or a notch on the pseudo-substrate.
8. The method of claim 1, wherein providing the bonding layer on the surface of the single crystal ingot comprises forming an oxide layer on the surface of the single crystal ingot, and wherein transferring the thin piezoelectric layer of the single crystal ingot adjacent the bonding layer to the handle substrate comprises molecularly bonding the oxide layer to the handle substrate.
9. The method of claim 1, wherein providing the bonding layer on the surface of the single crystal ingot comprises providing an adhesive layer on the surface of the single crystal ingot, and wherein transferring the thin piezoelectric layer of the single crystal ingot adjacent the bonding layer to the handle substrate comprises adhering the adhesive layer to the handle substrate.
10. The method of claim 1, further comprising, after fabricating the at least one pseudo-substrate, fabricating a second pseudo-substrate by: providing another bonding layer on another surface of the single crystal ingot without polishing the another surface of the single crystal ingot; transferring another thin piezoelectric layer of the single crystal ingot adjacent the another bonding layer to another handle substrate, the another bonding layer bonding the another thin piezoelectric layer to the another handle substrate; wherein a thickness of the another thin piezoelectric layer is 300 m or less.
11. A method for fabricating a structure comprising a layer of piezoelectric material on a final substrate, the method comprising: providing a pseudo-substrate, including: providing a piezoelectric layer on a handle substrate; bonding the piezoelectric layer of the pseudo-substrate to the final substrate; and removing the handle substrate of the pseudo-substrate from the piezoelectric layer after bonding the piezoelectric layer of the pseudo-substrate to the final substrate.
12. The method of claim 11, wherein providing the piezoelectric layer on the handle substrate comprises: providing a single crystal ingot comprising a piezoelectric material; providing a bonding layer on a surface of the single crystal ingot without polishing the surface of the single crystal ingot; and transferring a piezoelectric layer of the single crystal ingot adjacent the bonding layer to the handle substrate, the bonding layer bonding the piezoelectric layer to the handle substrate; wherein a thickness of the piezoelectric layer is 300 m or less.
13. The method of claim 12, wherein bonding the piezoelectric layer of the pseudo-substrate to the final substrate comprises: providing an oxide layer on at least one of a free surface of the final substrate and the piezoelectric layer of the pseudo-substrate; and molecularly bonding the piezoelectric layer of the pseudo-substrate to the final substrate with the oxide layer therebetween.
14. The method of claim 12, wherein transferring the piezoelectric layer of the single crystal ingot adjacent the bonding layer to the handle substrate comprises cutting the piezoelectric layer from the single crystal ingot.
15. The method of claim 14, wherein cutting the piezoelectric layer from the single crystal ingot comprises sawing the piezoelectric layer from the single crystal ingot.
16. The method of claim 12, further comprising separating the piezoelectric layer of the single crystal ingot from a remainder of the single crystal ingot, and subsequently bonding the bonding layer to the handle substrate.
17. The method of claim 12, wherein providing the bonding layer on the surface of the single crystal ingot comprises forming an oxide layer on the surface of the single crystal ingot, and wherein transferring the piezoelectric layer of the single crystal ingot adjacent the bonding layer to the handle substrate comprises molecularly bonding the oxide layer to the handle substrate.
18. The method of claim 12, wherein providing the bonding layer on the surface of the single crystal ingot comprises providing an adhesive layer on the surface of the single crystal ingot, and wherein transferring the piezoelectric layer of the single crystal ingot adjacent the bonding layer to the handle substrate comprises adhering the adhesive layer to the handle substrate.
19. The method of claim 11, further comprising fabricating a semiconductor device in or on the pseudo-substrate prior to bonding the piezoelectric layer of the pseudo-substrate to the final substrate.
20. The method of claim 19, wherein the semiconductor device comprises at least one device selected from among the group consisting of an electronic device, an optoelectronic device, a hyper frequency device, a micro-electro-mechanical system (MEMS) device, and a micro-opto-electro-mechanical system (MOEMS) device.
21. The method of claim 11, wherein removing the handle substrate of the pseudo-substrate from the piezoelectric layer comprises in-depth weakening of the pseudo-substrate by ion implantation, and splitting of the pseudo-substrate.
22. The method of claim 11, wherein the handle substrate comprises a silicon substrate.
23. The method of claim 11, wherein the piezoelectric material comprises LiNbO.sub.3 or LiTaO.sub.3.
24. A structure, comprising: a pseudo-substrate including a thin piezoelectric layer bonded to a handle substrate with a bonding layer therebetween; and a final substrate molecularly bonded to the thin piezoelectric layer on a side thereof opposite the handle substrate with an oxide layer disposed between the thin piezoelectric layer and the final substrate.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0033] The invention will be described in more detail hereafter using exemplary embodiments described in relation with the following figures, wherein:
[0034]
[0035]
[0036]
[0037]
[0038]
[0039]
[0040]
DETAILED DESCRIPTION
[0041]
[0042] As shown in portions 1a and 1b of
[0043] Next, as illustrated in
[0044] According to the invention, and as illustrated in
[0045] In this embodiment of the invention, the attachment is performed using a layer of an adhesive 108, in particular, a ceramic-based adhesive. The adhesive 108 and the handle substrate 102 are preferably both chosen with matching coefficients of thermal expansion with respect to the single crystal slice 105. The use of the adhesive 108 has the particular advantage that the cut single crystal slice 105 can be attached to the handle substrate 102 without having to go through any polishing step of its surfaces 106, 107, as the adhesive layer 108 compensates for the surface roughness of the slice 105.
[0046] According to further variants of the invention, the pseudo-substrate 109 can be chamfered and/or a flat and/or a notch can be provided.
[0047] Portions 2a to 2c of
[0048] Next, as illustrated in portion 2b of
[0049] In a variant of the second embodiment, as illustrated in portion 2c of
[0050] The semiconductor assemblies 109, 109, 111 or 112 can then serve as the basis for the fabrication of semiconductor devices as illustrated in
[0051] In portion 3a of
[0052] As illustrated in
[0053] As illustrated in
[0054] Instead of fabricating an LED device, the inventive semiconductor assemblies may be used for any other power device with a vertical structure.
[0055]
[0056]
[0057] According to a variant of the invention, and as illustrated in portion 4c of
[0058] According to further variants of the inventive method, the pseudo-substrate 409 is then treated similarly to a wafer and undergoes several preparation and finishing steps, such as chamfering, cutting a flat or a notch, and/or polishing the free single crystal surface 406, in order to improve the quality of the surface 406 for a subsequent epitaxial growth.
[0059] The pseudo-substrate 409 can also be polished on one of its free surfaces 406, 404, or double-side polished, for example, in order to adjust the thickness of the single crystal slice 405, or the total thickness of the pseudo-substrate 409. Similarly to the first embodiment, the slice 405 of SiC of the second embodiment can be thinned to a thickness in the range of approximately 50 m to 100 m to form a thinned slice 405 within thinned surface 406.
[0060] The thinning step can be followed by a step of chemical vapor deposition (CVD) in order to obtain the active part of an electronic component. This is schematically illustrated by a layer 410 in portion 4d of
[0061] According to further variants of the fourth embodiment of the invention, and similarly to the previous three embodiments as illustrated in
[0062]
[0063] Portion 5a of
[0064] In the fifth embodiment, as illustrated in portion 5b of
[0065] According to a variant of the invention, the stiffening layer 509 now provides enough mechanical stability to cut a thin slice 505 of the single crystal ingot 501, whose thickness can be even below the critical thickness, as illustrated in portion 5c of
[0066] Following a variant of the inventive method, and as illustrated in portion 5d of
[0067] According to variants of the inventive method, the pseudo-substrate 511 can then be treated similarly to a wafer and undergo several preparation and finishing steps, such as chamfering, cutting a flat or a notch, and/or also removing the stiffener 509, which, in this case, is then only used as a temporary substrate for obtaining a slice 505 thinner than the critical thickness of the single crystal material. As illustrated in portion 5e of
[0068]
[0069] Portion 6a of
[0070] According to a variant of the inventive method, in the sixth embodiment, as illustrated in portion 6b of
[0071] In a variant of this embodiment, the stiffener could be a refractory metal such as W, Mo, or the like, chemically and physically stable at least under 900 C. In the variant of a layer 608 of a refractory metal, the layer 608 can have a thickness about 100 m and can be deposited, e.g., by chemical vapor deposition (CVD).
[0072] According to a variant of the invention, the deposited layer 608 is a stiffener that now provides enough mechanical stability to cut a thin slice 605 of the single crystal ingot 601, whose thickness can be even below the critical thickness, as illustrated in portion 6c of
[0073] Following a variant of the inventive method, the thin slice 605 forming the self-standing structure 609 with the oxide layer 608 could now be attached to the handle substrate 602 by its free single crystal surface 606 using an adhesive such as a ceramic or a graphite-based adhesive, resulting in a pseudo-substrate similar to the intermediate pseudo-substrate 511 of the fifth embodiment illustrated in portion 5d of
[0074] However, in the sixth embodiment, and as illustrated in portion 6d of
[0075] According to variants of the inventive method, the pseudo-substrate 610 can now be treated similarly to a wafer and undergo several preparation and finishing steps such as chamfering, cutting a flat or a notch, and/or also thinning and/or polishing the free surface 606 of the single crystal material or the back side 604 of the handle substrate 602.
[0076] According to variants of the invention, and similarly to the four embodiments illustrated in
[0077]
[0078] In the seventh embodiment, like in the second embodiment, the thinned layer 105 is a layer of GaN. In particular, the back side surface 107 corresponds to the Ga face of the GaN thinned layer 105, and the polished thinned surface 106 corresponds to the N face of the GaN thinned layer 105. In the seventh embodiment, the substrate 102 can be sapphire instead of an Si wafer like in the first and second embodiments, with a matching coefficient of thermal expansion (CTE) relatively to the GaN material of the thinned layer 105. Furthermore, in the seventh embodiment, the free thinned surface 106 is polished such that it surface roughness is compatible with a direct bonding.
[0079] As illustrated in portion 7a of
[0080] Next, as illustrated in portion 7b of
[0081] In an alternative, illustrated by portions 7c and 7d of
[0082] In yet another alternative to the seventh embodiment, the thinned layer 105 could be a slice of SiC instead of GaN. In this case, the free surface 107 corresponds to the Si face of the SiC thinned layer 105, and the polished surface 106 corresponds to the C face of the SiC thinned layer 105. Other materials can be chosen like in the previous embodiments, provided that the CTEs match one another, as explained above.
[0083] In the embodiments described previously, and their variants, the final assemblies 109, 109, 111, 112, 203, 205, 409, 411, 511, 512, 610, 704 and 706 have all the advantage that the efficiency of usage of an initial ingot of an expensive material has been improved with respect to prior art wafering methods, in particular, with respect to the method disclosed in EP 1 324 385 A2. One reason is that instead of manufacturing a wafer from a single crystal ingot, which requires extensive polishing and thinning steps, according to the inventive method, a slice of the ingot can already be cut at a thickness of approximately the critical thickness below which the slice is no longer mechanically stable if taken alone, or at a thickness even below the critical thickness, such that it is possible to work directly on a thinner single crystal slice compared to prior art methods without needing to polish the slice beforehand. Thus, starting from a single crystal ingot, up to about 30% to about 50% more semiconductor assemblies can be provided compared to the prior art.