SENSOR MODULE

Abstract

A sensor module comprises a master sensor unit for sensing a first environmental parameter, a slave sensor unit for sensing a second environmental parameter, a common substrate on which the master sensor unit and the slave sensor unit are mounted, and a digital bus interface for a communication between the master sensor unit and the slave sensor unit. The master sensor unit comprises a non-volatile memory for storing calibration data and configuration data of the master sensor unit and the slave sensor unit. The master sensor unit is embodied as a first chip, and the slave sensor unit is embodied as a second chip. Such sensor module is compact, robust and versatile.

Claims

1. Sensor module, comprising a master sensor unit configured to sense a first environmental parameter, a slave sensor unit configured to sense a second environmental parameter, a common substrate on which the master sensor unit and the slave sensor unit are mounted, a digital bus interface for a communication between the master sensor unit and the slave sensor unit, wherein the master sensor unit comprises a non-volatile memory configured to store calibration data and configuration data of the master sensor unit and the slave sensor unit, and wherein the master sensor unit is embodied as a first chip, and the slave sensor unit is embodied as a second chip.

2. Sensor module according to claim 1, comprising a set of slave sensor units, each slave sensor unit of the set being configured to sense an environmental parameter different to the environmental parameters sensed by the one or more of the other slave sensor units of the set, each slave sensor unit of the set being embodied as an individual chip.

3. Sensor module according to claim 1, wherein the master sensor unit and the at least one slave sensor unit are configured to operate synchronously, based on a common clock with a common clock period and common phase for each sensor unit, preferably wherein the master sensor unit is configured to receive one external time reference, in particular from a quartz, and is configured to derive the common clock from the received external time reference, preferably wherein the master sensor unit is configured to supply the common clock to all slave sensor units.

4. Sensor module according to claim 3, wherein the common clock and a reset signal are supplied to the at least one slave sensor unit via a combined signal over the digital bus interface on a single pin, wherein a reset pulse is derived from the combined signal in the at least one slave sensor unit if the common clock period deviates from a nominal common clock period in a defined way.

5. Sensor module according to claim 4, wherein the at least one slave sensor unit (2) comprises a reset sequence detector, wherein the reset sequence detector generates the reset pulse when detecting in the combined signal a high pulse that is longer than a nominal high time directly followed by a low pulse that is shorter than a nominal low time.

6. Sensor module according to claim 4, wherein the combined signal over the digital bus interface is additionally used to provide a supply voltage to the at least one slave sensor unit, preferably wherein a cumulated duration of high pulses in the combined signal is longer than a cumulated duration of low pulses.

7. Sensor module according to claim 1, the master sensor unit comprising a measurement sequence unit configured to trigger a sequence of measurements by the sensor units, in particular wherein the measurement sequence unit is configured to trigger the sequence of measurements by the sensor units synchronously, preferably based on the common clock applied by all sensor units, preferably based on a frequency of multiple integers of the common clock period, in particular wherein the measurement sequence unit is configured to trigger the measurements of all sensor units at the same time, in particular wherein the measurement sequence unit is configured to initiate measurements of a sensor unit dependent on a value measured by a different sensor unit.

8. Sensor module according to claim 1, comprising an interface for the master sensor unit to communicate with one or more units external to the sensor module, wherein the sensor module is configured to communicate with the one or more external units exclusively via the interface for the master sensor unit, wherein all slave sensor units are connected to the master sensor unit by means of the same digital bus interface, wherein a protocol of the digital bus interface is configured to make each slave sensor unit exclusively communicate with the master sensor unit, preferably wherein the digital bus interface is a two-wire interface or a single-wire interface.

9. Sensor module according to claim 1, the master sensor unit comprising a humidity sensor, in particular a combined humidity and temperature sensor, in particular wherein the temperature sensor is arranged and configured to determine a temperature ambient of the sensor module.

10. Sensor module according to claim 1, wherein the slave sensor unit comprises one of a gas sensor; in particular one of a MOX-based gas sensor; an optical gas sensor, a photoacoustic gas sensor; a thermal gas sensor; an electrochemical gas sensor in particular a solid EC gas sensor or a room temperature organic liquid EC gas sensor; an aerosol concentration sensor in particular a PM sensor; in particular an optical particle counter; a humidity sensor; preferably wherein another slave sensor unit of the set comprises one of a gas sensor; in particular one of a MOX-based gas sensor; an optical gas sensor, a photoacoustic gas sensor; a thermal gas sensor; an electrochemical gas sensor in particular a solid EC gas sensor or a room temperature organic liquid EC gas sensor; an aerosol concentration sensor in particular a PM sensor; in particular an optical particle counter; a humidity sensor; preferably wherein a further slave sensor unit of the set comprises one of a gas sensor; in particular one of a MOX-based gas sensor; an optical gas sensor, a photoacoustic gas sensor; a thermal gas sensor; an electrochemical gas sensor in particular a solid EC gas sensor or a room temperature organic liquid EC gas sensor; an aerosol concentration sensor in particular a PM sensor; in particular an optical particle counter; a humidity sensor.

11. Sensor module according to claim 1, comprising a housing for the master sensor unit and the at least one slave sensor unit, wherein the housing comprises at least one opening arranged and configured to enable a medium to access the sensor units for enabling the sensor units to sense the corresponding environmental parameters, in particular wherein the housing comprises at least two openings arranged and configured to enable a medium to access the sensor units for enabling the sensor units to sense the corresponding environmental parameters, in particular wherein the housing comprises one opening per sensor unit each opening being arranged and configured to enable a medium to access the sensor units for enabling the sensor units to sense the corresponding environmental parameters.

12. Sensor module according to claim 1, the master sensor unit comprising a power management unit for generating an internal supply voltage and a supply voltage for the digital bus interface, and the slave sensor unit comprising a power management unit for generating an internal supply voltage.

13. Sensor module according to claim 1, the master sensor unit comprising a processing unit for processing signals measured by the sensor units, in particular the processing unit being configured to combine measured signals of different sensor units yielding a processed signal, in particular the processing unit being configured to use a temperature value measured by one of the sensor units to perform a temperature compensation on a signal of a different physical quantity measured by another one of the sensor units, and/or in particular the processing unit being configured to use a relative humidity value measured by one of the sensor units to perform a humidity compensation on a signal of a different physical quantity measured by the another one of the sensor units.

14. Sensor module according to claim 1, the master sensor unit comprising a memory for storing a measured signal or a processed signal of a sensor unit, in particular in combination with a time stamp related to a time of the measurement.

15. Sensor module according to claim 1, the master sensor unit comprising a self-test unit configured to execute a test sequence on at least one sensor unit during manufacturing or application of the sensor module.

16. Sensor module according to claim 1, the slave sensor unit comprising an analog front-end electronics for interfacing sensor signals, and an analog-to-digital converter and preferably a MEMS sensor.

17. Sensor module according to claim 1, the slave sensor unit not comprising a clock, a reset and/or memory for calibration and/or configuration data.

18. Sensor module according to claim 1, the slave sensor unit comprising a unique unit identifier, and the digital bus interface comprising a protocol to address each slave sensor unit separately by means of the unique unit identifier.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The embodiments defined above and further aspects, features and advantages of the present invention can also be derived from the examples of embodiments to be described hereinafter and are explained with reference to the drawings. In the drawings, it is illustrated in

[0051] FIG. 1 a schematic view of a sensor module according to an embodiment of the present invention,

[0052] FIG. 2 a block diagram of a sensor module according to an embodiment of the present invention,

[0053] FIG. 3 a block diagram of a sensor module according to an embodiment of the present invention,

[0054] FIG. 4 timing of clock and measurements as used in a sensor module according to an embodiment of the present invention,

[0055] FIG. 5 a combined signal for common clock and reset signal used to derive a reset pulse, and

[0056] FIG. 6 a block diagram of a usage of the combined signal for the common clock, the reset pulse and a supply voltage (power-over-clock).

DETAILED DESCRIPTION OF THE DRAWINGS

[0057] FIG. 1 shows a schematic view of a first embodiment of the sensor module with a master sensor unit 1 and two slave sensor units 2 on a common substrate 3. The master sensor unit 1 and the slave sensor units 2 are integrated in three separate chips, preferably semiconductor chips. The common substrate 3 may be a printed circuit board or any other support for mounting the chips on. The number of slave sensor units 2 may be one, two or more.

[0058] Each slave sensor unit 2 communicates with the master sensor unit 1 via a digital bus interface 4. The digital bus interface 4 is a low pin-count digital interface, preferably a two-wire or one-wire interface. The communication via the digital bus interface 4 comprises at least signals measured by the slave sensor units 2 and start/stop conditions for the measurements. It may as well comprise a clock signal for synchronizing the communication and the measurements of the master sensor unit 1 and the slave sensor units 2. The clock signal can e.g. be generated by a quartz, which may be located internal in the master sensor unit 1, or the signal of which may be supplied from external to the sensor module, and preferably to the master sensor unit 1.

[0059] The master sensor unit 1 and the slave sensor units 2 are arranged in a housing 5, which protects the chips and yields a robust sensor module. The housing 5 may be made of plastic or metal, or it may be an encapsulation, e.g. comprising a moulding compound. The housing 5 comprises at least one opening 6 for the sensor units 1, 2 to be able to sense physical quantities of an environment of the sensor module. In one embodiment, the housing 5 comprises one common opening 6 for all sensor units 1, 2. In a different embodiment, there are separate openings 6 for several or all of the sensor units 1, 2 in the housing.

[0060] The sensed physical quantities may comprise a variety of quantities, e.g. relative humidity, temperature, gas concentration or aerosol concentration, preferably all of the ambient. In a preferred embodiment, the master sensor unit 1 comprises a combined sensor for relative humidity and temperature, one slave sensor unit 2 comprises a 4-pixel MOX gas sensor, and the other slave sensor unit 2 comprises an electrochemical CO2 sensor. An extension to more slave sensor units 2 is possible, with e.g. an optical particle counter as additional slave sensor unit 2. The described setup and communication make it possible to integrate common sensor units into the sensor module as slave sensor units 2 which would otherwise be difficult or impossible to be integrated in a small package together with the sensor, a processor and a memory of the master sensor unit 1.

[0061] The master sensor unit 1 receives a power supplied from externally via one or more of pins 7. The pins 7 are also used to receive and supply control signals and measured signals and hence represent an interface for the master sensor unit 1 to communicate with an external unit. In one embodiment, the master sensor unit 1 comprises a power management unit for generating an internal supply voltage and a supply voltage for the digital bus interface 4. The internal supply voltage may also be provided to the slave sensor units 2 such that they do not necessarily require a separate power management unit.

[0062] FIG. 2 shows a block diagram of a sensor module according to an embodiment of the present invention with a master sensor unit 1 and one slave sensor unit 2 as well as their respective subunits 1x, 3x for the master sensor unit 1, and 2x for the slave sensor unit 2. A possible extension to more than one slave sensor units 2 is indicated through the dashed lines at the right of FIG. 2. In this embodiment, the master sensor unit 1 and the slave sensor unit 2 are fed by a common external supply voltage 8 (VDDIO).

[0063] The master sensor unit 1 receives and transmits signals via a digital or analog input and output line 9 (D/A IO), also referred to as interface for the master sensor unit 1. The input signals may be control signals for performing specific measurement routines. The output signals may be signals of one or more physical quantities measured by the sensor units 1 and 2, or they comprise a combined or processed signal from more than one of the sensor units 1 and 2, or a control signal, such as an alarm. The master sensor unit 1 communicates with the slave sensor unit 2 via a digital bus interface 4. For this purpose, the master sensor unit 1 comprises a digital master interface 30, and the slave sensor unit comprises a digital slave interface 26.

[0064] The master sensor unit 1 may comprise an oscillator 31 for deriving a common clock from for the master sensor unit 1 and the slave sensor unit 2. The common clock signal preferably is transmitted to the slave sensor unit 2 via the digital bus interface 4. The master sensor unit 1 comprises a sensitive element 11, which may be sensitive to relative humidity and/or temperature. In a different embodiment, the sensitive element 11 is a capacitive CO2 sensor. The master sensor unit 1 further comprises a non-volatile memory 12 for storing calibration data of the master sensor unit 1 and the slave sensor unit 2, and a non-volatile memory 13 for storing configuration data of both the master sensor unit 1 and the slave sensor unit 2. Non-volatile memories 12 and 13 may be represented by a common non-volatile memory having the various data stored in a common memory structure. Calibration data may be stored in the form of look-up tables which facilitate different operations on a measured signal. Accordingly, calibration data may include correcting factors for a sensor response, linearization parameters, interpolation parameters, or compensation parameters e.g. for temperature.

[0065] For processing the signals measured by the different sensor units 1, 2, the master sensor unit 1 comprises a processing unit 14, which may, for example, be a hardwired logic. The processing unit 14 is configured to perform the operations mentioned above on the measured signal, e.g. by using look-up tables provided by the non-volatile memories 12 and 13. The measured signal and/or the processed signal is stored in a memory 18.

[0066] The master sensor unit 1 additionally comprises a power management unit 15 for generating a supply voltage for the digital bus interface 4. It may also provide a supply voltage different from VDDIO for other subunits, such as the sensitive element 11.

[0067] Advantageously, the master sensor unit 1 comprises a measurement sequence unit 16 for controlling a sequence of measurements by the sensor units 1 and 2. The measurement sequence unit 16 may e.g. ensure a right order of measurements by the different sensor units 1, 2, or it may apply conditions for a specific sensor unit 1, 2 to provide a measurement value, or it may apply different sampling rates for different sensor units 1, 2.

[0068] Also, the master sensor unit 1 preferably comprises a self-test unit 17 configured to execute a test sequence on at least one sensor unit 1, 2 during manufacturing or application of the sensor module. The self-test unit 17 may apply a certain measurement routine to a specific sensor unit 1, 2, compare the measured data with a stored reference, and output a signal indicating a possible defect of the specific sensor unit 1, 2.

[0069] Preferably, the master sensor unit 1 comprises a power-on reset 32 generation to reset the processing unit 14 and/or the volatile memory 18 to an initial state.

[0070] In comparison with the master sensor unit 1, the slave sensor unit 2 is of limited functionality. It is sufficient that it comprises a MEMS sensor 21, e.g. a MOX gas sensor or an electrochemical gas sensor, analog front-end electronics 22 such as a readout for interfacing sensor signals, and an analog-to-digital converter 23. Hence, the slave sensor unit 2 may be a common MEMS chip.

[0071] Advantageously, the slave sensor unit 2 comprises a non-volatile memory 24 for storing a unique unit identification number. This facilitates addressing each slave sensor unit 2 separately via the digital bus interface 4.

[0072] The slave sensor unit 2 may also comprise a power management unit 25 for generating an internal supply voltage derived from the common external supply voltage 8 (VDDIO), for supplying power to its analog as well as its digital parts.

[0073] FIG. 3 illustrates a block diagram of a sensor module according to another embodiment of the present invention. The sensor module of FIG. 3 only differs from the sensor module of FIG. 2 in that the power supply in the slave sensor unit 2 is realized different. Instead of the power management unit 25 of FIG. 2 responsible for powering analog and digital parts of the slave sensor unit 2, in the embodiment of FIG. 3, a power management unit 25a is provided for generating an internal supply voltage derived from the common external supply voltage 8 (VDDIO), but limited to supplying power to the analog parts of the slave sensor unit 2 only. Instead, powering of the digital parts of the slave sensor unit 2 is achieved by means of different power management unit 25b, which derives the supply voltage for the digital parts from the digital bus interface 4. Hence, in this embodiment, the power management unit 15 of the master sensor unit 1 supplies a supply voltagepreferably different from VDDIO but derived therefromto the slave sensor unit 2 via the digital bus interface 4.

[0074] FIG. 4 illustrates the timing of clock and measurements as used in a sensor module according to an embodiment of the present invention. Such timing may be used in any of the embodiments of the sensor modules according to FIGS. 1 to 3. A clock of the master is shown in the first graph over time. The period of the clock of the master is referred to by (2). The second graph shows a clock of a first slave sensor unit, the period of which clock is equal to the period of the master clock. The third graph shows a clock of a second slave sensor unit, the period of which clock is equal to the period of the master clock and the clock of the first slave sensor unit. Accordingly, it is preferred that all sensor units, i.e. the master sensor unit and any slave sensor unit are operated under the same clock signal, i.e. are operated under a common clock with a defined common clock period (5) and a common phase: Hence, all clocks are in phase.

[0075] As to the timing of measurements triggered or taken by the individual sensor units, reference (1) indicates such points in time of measurement strobes, i.e. all bold strokes in FIG. 4 represent a measurement strobe within a sequence of measurements taken by the sensor units. Accordingly, the sensor of the master sensor unit takes measurements/is triggered by the measurement sequence unit to take measurements every second clock period. The sensor of the first slave sensor unit takes measurements/is triggered by the measurement sequence unit of the master sensor unit to take measurements every third clock period. The sensor of the second slave sensor unit takes measurements/is triggered by the measurement sequence unit of the master sensor unit to take measurements every fourth clock period. Accordingly, the measurements of the various sensors in the master sensor unit and the slave sensor units are taken synchronously, i.e. based on the common clock, and of a frequency of multiple integers of the common clock period.

[0076] FIG. 5 shows a combined signal 40 for common clock and reset signal 41 used to derive a reset pulse 42. The combined signal 40 is supplied from the master sensor unit to any slave sensor unit via the digital interface bus. The combined signal 40 may be transmitted via a single pin, which is shared for reset and clock signals. The reset pulse for the slave sensor unit is generated on-chip if the clock timing deviates from a nominal clock timing in a specific way.

[0077] FIG. 5 depicts a possible implementation of common clock and reset signal in one combined signal. The upper part of FIG. 5 shows a situation where no reset pulse from the combined signal 40 is generated since the clock timing corresponds to the nominal clock timing with nominal high time T.sub.high,nom and nominal low time T.sub.low,nom.

[0078] The lower part of FIG. 5 shows a situation where a high pulse in the combined signal 40 is longer than the nominal high time T.sub.high,nom, and this high pulse is directly followed by a low pulse that is shorter than the nominal low time T.sub.low,nom. Such sequence of a high pulse and a low pulse, called a reset sequence, is interpreted as a reset pulse 42, and the slave sensor unit is reset.

[0079] FIG. 6 shows a block diagram of a usage of the combined signal 40 for the common clock 43, the reset signal 41 and additionally a supply voltage 44. Such combination or usage of signals is also called power-over-clock. A reset sequence detector 45 evaluates the combined signal 40 supplied to the slave sensor unit. If the reset sequence detector 45 detects a reset sequence, for instance defined as in depicted in FIG. 5, it generates a reset pulse. In addition to the common clock 43 and the reset signal 41, also the supply voltage 44 for the slave sensor unit is taken from the combined signal 40. In this way, a dedicated pin for the supply voltage is not needed. Providing the supply voltage 44 via the combined signal 40 is facilitated since the combined signal 40 is high for most of the time, i.e. a cumulated duration of the high pulses is longer than a cumulated duration of the low pulses. Also the reset sequence as defined above is compatible with a power-over-clock scheme where the supply voltage for the slave sensor unit is provided through the combined signal together with the common clock. The combined signal may be low-pass filtered for these purposes.