RC-snubber element with high dielectric strength

Abstract

In an electrical circuit arrangement, which is formed by an RC-snubber element monolithically integrated into a semiconductor substrate, a first capacitor and a resistor of the RC-snubber element are vertically formed in a semiconductor region of a first type of doping of the semiconductor substrate. At least one further capacitor is connected in series with the first capacitor. The further capacitor is integrated laterally with the first capacitor in a semiconductor region of a second type of doping, which adjoins the semiconductor region of the first type of doping, and by virtue of the different type of doping electrically insulates the further capacitor from the semiconductor region of the first type of doping. This circuit arrangement forms a low inductance RC-snubber element with high dielectric strength, which has high heat dissipation and integration density.

Claims

1. An electrical circuit arrangement, which is formed by an RC-snubber element, which is monolithically integrated into a semiconductor substrate, in which a first capacitor (C.sub.vert) and a resistor (R) of the RC-snubber element are formed vertically in a semiconductor region of a first type of doping of the semiconductor substrate, and at least one further capacitor (C.sub.lat) is connected in series with the first capacitor (C.sub.vert), wherein the further capacitor (C.sub.lat) is integrated laterally in a semiconductor region of a second type of doping, which adjoins the semiconductor region of the first type of doping, and, by virtue of the different type of doping, electrically insulates the further capacitor (C.sub.lat) from the semiconductor region of the first type of doping.

2. The electrical circuit arrangement in accordance with claim 1, characterised in that, the semiconductor region of the second type of doping is formed as a well region in the semiconductor region of the first type of doping.

3. The electrical circuit arrangement in accordance with claim 1, characterised in that, the semiconductor region of the first type of doping extends from a front face of the semiconductor substrate, on which the capacitors (C.sub.vert, C.sub.lat) are formed, to a rear face of the semiconductor substrate, wherein the rear face is provided with a rear face metallisation, by way of which electrical contact can be made with the resistor (R) of the RC-snubber element, and at least one electrical contact is applied to the front face, by way of which electrical contact can be made with the at least one further capacitor (C.sub.lat).

4. The electrical circuit arrangement in accordance with claim 3, characterised in that, the semiconductor substrate for forming the capacitors (C.sub.vert, C.sub.lat) on the front face has in each case an arrangement of recesses, which are coated with an electrically insulating dielectric layer, or layer sequence, and are filled with an electrically conductive material.

5. The electrical circuit arrangement in accordance with claim 4, characterised in that, the capacitors (C.sub.vert, C.sub.lat) have a common electrically insulating dielectric layer, or layer sequence.

6. The electrical circuit arrangement in accordance with claim 4, characterised in that, the electrically insulating dielectric layer, or layer sequence, is formed from silicon dioxide and silicon nitride.

7. The electrical circuit arrangement in accordance with claim 1, characterised in that, balancing resistors are formed between the capacitors (C.sub.vert, C.sub.lat).

8. The electrical circuit arrangement in accordance with claim 2, characterised in that, a junction termination is formed around the well region.

9. The electrical circuit arrangement in accordance with claim 1, characterised in that, the semiconductor regions in the area of the capacitors (C.sub.vert, Q.sub.lat) have a doping of 5E18 cm.sup.3.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In what follows the proposed electrical circuit arrangement is explained in more detail by way of examples of embodiment, in conjunction with the figures. Here:

(2) FIG. 1 shows a cross-section through an electrical circuit arrangement, and an equivalent circuit diagram, in accordance with a first example of embodiment of the present invention;

(3) FIG. 2 shows a cross-section through an electrical circuit arrangement, and an equivalent circuit diagram, in accordance with a second example of embodiment of the present invention;

(4) FIG. 3 shows a cross-section through an electrical circuit arrangement, and an equivalent circuit diagram, in accordance with a third example of embodiment of the present invention;

(5) FIG. 4 shows a cross-section through an electrical circuit arrangement, and an equivalent circuit diagram, in accordance with a fourth example of embodiment of the present invention;

(6) FIG. 5 shows two examples of the arrangement of the vertical and one or a plurality of lateral capacitors in a plan view onto the electrical circuit arrangement in accordance with the present invention;

(7) FIG. 6 shows a cross-section through an electrical circuit arrangement, and an equivalent circuit diagram, in accordance with a fifth example of embodiment of the present invention;

(8) FIGS. 7A-D show an exemplary sequence of the steps in the method for the production of the proposed electrical circuit arrangement in a cross-sectional presentation.

WAYS FOR CARRYING OUT THE INVENTION

(9) In what follows, the proposed electrical circuit arrangement is described in more detail with the aid of a plurality of examples of embodiment, in which the RC-snubber element with the vertical capacitor, and one or a plurality of lateral capacitors, is designed as a semiconductor chip. To this end FIG. 1 shows a cross-sectional presentation of a first example of embodiment, together with a corresponding equivalent circuit diagram of this design. The RC-snubber element is formed by a series circuit of a resistor R, a vertical capacitor C.sub.vert, and a lateral capacitor C.sub.lat, as shown in the equivalent circuit diagram. For this purpose, a p.sup.+-doped well 2 and an n.sup.+-doped well 3 are introduced into the front face of the p-doped semiconductor substrate 1. In these wells trenches are formed, which are coated with a dielectric layer 4 and filled with an electrically conductive material 5, such as polysilicon. The two capacitors formed in this way are connected in series via metallisation 6, wherein electrical contact can be made with the lateral capacitor C.sub.lat via a corresponding front face electrode 7. A p.sup.+-layer is located on the rear face of the semiconductor substrate 1 to form a p.sup.+-contact 8, to which rear face metallisation 9 is applied. This rear face metallisation forms the rear face electrode for purposes of making contact with the RC-snubber element. By virtue of the n.sup.+-doping of the well region 3 of the lateral capacitor C.sub.lat, a pn-diode D.sub.iso,1 is formed, as shown in the equivalent circuit diagram. The individual components of this equivalent circuit diagram are also indicated in the cross-sectional presentation. The polarity of the capacitors is determined by a reverse polarity of the pn-diode D.sub.iso,1. By virtue of the p-doping of the semiconductor substrate 1 and the thickness of this substrate, the magnitude of the resistor R is specified and can be adjusted.

(10) Such an electrical circuit arrangement can also be implemented with dopings that are inverted compared to FIG. 1, as is shown schematically in FIG. 2 in a cross-sectional presentation, as well as in the corresponding equivalent circuit diagram.

(11) The proposed electrical circuit arrangement can also be implemented with more than one lateral capacitor. In this case, a plurality of lateral capacitors C.sub.lat are connected in series with the vertical capacitor C.sub.vert, as illustrated by the two lateral capacitors C.sub.lat in FIG. 3. Here the second lateral capacitor is formed in the same way as the first lateral capacitor in an n.sup.+-doped well 3 in the semiconductor substrate. Here too, the individual capacitors are connected by way of appropriate metallisations 6. The blocking resistance of the pn-diode D.sub.iso,2, or D.sub.iso,n of the last lateral capacitor in the series circuit, must be sufficiently high to withstand the voltages that occur.

(12) Instead of making contact with just the last capacitor in the series circuit, each capacitor C.sub.vert, C.sub.lat can also be provided with a corresponding contact electrode 7, as shown, for example, in the cross-sectional presentation and the equivalent circuit diagram of FIG. 4. This option of making contact with the individual capacitors makes it possible, for example, to implement a charge pump or a capacitive voltage divider. Here the individual capacitors can also have different capacitance values.

(13) The individual capacitors can be arranged laterally in different ways. To this end FIG. 5 shows two examples of such an arrangement, highly schematised, in a plan view onto the semiconductor substrate. In the left-hand design with only one lateral capacitor C.sub.lat, this is symmetrically arranged within the region of the vertical capacitor C.sub.vert. In this figure, a junction termination 11 is also indicated, which is intended to prevent any breakthrough on the curvatures of the well for the lateral capacitor. The junction termination represents a barrier layer insulation of the pn-diodes with the aid of field rings. In the right-hand part of the figure an example of a design with four lateral capacitors is indicated.

(14) Finally, FIG. 6 shows another example of embodiment of the proposed electrical circuit arrangement, in which an additional n.sup.+-well 10 is introduced into the semiconductor substrate 1 so as to generate an additional pn-diode D.sub.iso,n. A series circuit of appropriate Zener diodes for high voltages for balancing purposes is also possible with the proposed circuit arrangement. The layout of the leakage currents of the individual pn-diodes can take place by way of the respective component areas. The introduction of additional poly resistors (R.sub.sym and R.sub.sym) between the individual capacitors is also possible for balancing purposes.

(15) The blocking resistance of the respective pn-diode can be adjusted by way of the doping and the width of the drift region (substrate thickness). Here a vertical extent corresponding to a substrate thickness of >200 m is preferred. The lateral extent, that is to say, the distances between the individual capacitors in the lateral direction, can be <200 m if the doping is suitably adjusted to avoid a PT-effect.

(16) The following table gives an example of the possible resistance range (respective minimum resistance) for different voltages with a substrate thickness of 650 m.

(17) TABLE-US-00001 R in cm.sup.2 0.03 0.07 0.16 0.7 1.2 1.8 2.9 4.2 6.8 U.sub.max 50 100 200 600 900 1200 1700 2300 3300 in V

(18) Lower resistances are also possible with the aid of correspondingly thinner substrates or epitaxy.

(19) In what follows an example of the production of an inventive electrical circuit arrangement with a vertical and a lateral capacitor as shown in FIG. 1 is briefly explained. First, a trench structure is created in the surface of the substrate 1 for each of the two capacitors with the aid of a mask. This serves to increase the surface area for the formation of capacitors and in the case of a silicon substrate can be done, for example, by means of dry etching (anisotropic). FIG. 7A shows an appropriate trench structure of the p-doped semiconductor substrate 1. This is followed by doping of the capacitor regions so as to generate the respective wells 2, 3. The well 2 for the vertical capacitor is p.sup.+-doped, for example by B-implantation or boron glass deposition. The n.sup.+-doping of the well 3 for the lateral capacitor can take place, for example, by means of P-implantation or POCl.sub.3-deposition. Annealing then takes place, during which the dopants are activated and the surface concentration is reduced. FIG. 7B shows the result of this doping step in cross-section. Implantation of a junction termination for the n.sup.+-doped well 3 is also possible. The next step is the deposition of the capacitor dielectric 4, and the filling of the trenches with polysilicon 5, as is schematically indicated in FIG. 7C. The capacitor dielectric 4 is created by thermal oxidation in combination with a silicon nitride deposition. There then follows the polysilicon deposition (e.g. doped in-situ) and the structuring of the deposited layer. Finally, contact holes are etched in to enable electrical contacts to be subsequently made. FIG. 7D shows the final electrode production and passivation. The front face is first metallised in conjunction with a structuring of the metal 6 and the polysilicon 5. This is followed by the metallisation of the rear face and the deposition of a passivation layer, for example using polyimide. The result is an electrical circuit arrangement as has been described in FIG. 1.

LIST OF REFERENCE SYMBOLS

(20) 1 Semiconductor substrate 2 Well for vertical capacitor 3 Well for lateral capacitor 4 Dielectric layer 5 Electrically conductive material 6 Metallisation 7 Contact electrode 8 p.sup.+-contact or n.sup.+-contact 9 Rear face metallisation 10 n.sup.+-doped well 11 Junction termination