METHOD OF IMPROVING READ CURRENT STABILITY IN ANALOG NON-VOLATILE MEMORY USING FINAL BAKE IN PREDETERMINED PROGRAM STATE

Abstract

A method of improving stability of a memory device having a controller configured to program each of a plurality of non-volatile memory cells within a range of programming states bounded by a minimum program state and a maximum program state. The method includes testing the memory cells to confirm the memory cells are operational, programming each of the memory cells to a mid-program state, and baking the memory device at a high temperature while the memory cells are programmed to the mid-program state. Each memory cell has a first threshold voltage when programmed in the minimum program state, a second threshold voltage when programmed in the maximum program state, and a third threshold voltage when programmed in the mid-program state. The third threshold voltage is substantially at a mid-point between the first and second threshold voltages, and corresponds to a substantially logarithmic mid-point of read currents.

Claims

1. A method of improving stability of a memory device that includes a plurality of non-volatile memory cells and a controller configured to program each of the memory cells within a range of programming states bounded by a minimum program state and a maximum program state, the method comprising: testing the memory cells to confirm the memory cells are operational; programming each of the memory cells to a mid-program state; and baking the memory device at a high temperature while the memory cells are programmed to the mid-program state; wherein, for each of the memory cells: the memory cell has a first threshold voltage when programmed in the minimum program state, the memory cell has a second threshold voltage when programmed in the maximum program state, and the memory cell has a third threshold voltage when programmed in the mid-program state, wherein the third threshold voltage is substantially at a mid-point between the first and second threshold voltages.

2. The method of claim 1, wherein each of the memory cells comprises: spaced apart source and drain regions formed in a semiconductor substrate, with a channel region of the substrate extending there between, a floating gate disposed vertically over and insulated from a first portion of the channel region, a select gate disposed vertically over and insulated from a second portion of the channel region, and a control gate disposed vertically over and insulated from the floating gate.

3. The method of claim 2, wherein each of the memory cells further comprises: an erase gate disposed over and insulated from the source region.

4. A method of improving stability of a memory device that includes a plurality of non-volatile memory cells each including at least a floating gate disposed over and insulated from a channel region of a semiconductor substrate and a control gate disposed over and insulated from the floating gate, and a controller configured to program each of the memory cells within a range of programming states bounded by a minimum program state and a maximum program state, and to read each of the memory cells using a read voltage applied to the control gate, the method comprising: testing the memory cells to confirm the memory cells are operational; programming each of the memory cells to a mid-program state; and baking the memory device at a high temperature while the memory cells are programmed to the mid-program state; wherein, for each of the memory cells: the memory cell produces a first read current during a read operation using the read voltage applied to the control gate when programmed in the minimum program state, the memory cell produces a second read current during a read operation using the read voltage applied to the control gate when programmed in the maximum program state, and the memory cell produces a third read current during a read operation using the read voltage applied to the control gate when programmed in the mid-program state, wherein the third read current is substantially at a logarithmic mid-point between the first and second read currents.

5. The method of claim 4, wherein each of the memory cells comprises: spaced apart source and drain regions formed in a semiconductor substrate, with the channel region of the substrate extending there between, the floating gate is disposed vertically over and insulated from a first portion of the channel region, a select gate disposed vertically over and insulated from a second portion of the channel region.

6. The method of claim 5, wherein each of the memory cells further comprises: an erase gate disposed over and insulated from the source region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG. 1 is a side cross sectional view of a memory cell of the prior art.

[0015] FIG. 2 is a diagram illustrating the components of a memory device.

[0016] FIG. 3 is a graph illustrating the memory cell operating range in terms of read current and threshold voltage Vt in the subthreshold operating range.

[0017] FIG. 4 is a flow diagram showing the steps of programming and baking the memory cells.

[0018] FIG. 5 is a graph illustrating an example of I-V characteristics of a memory cell inside the operating range.

DETAILED DESCRIPTION OF THE INVENTION

[0019] The present invention is a technique for stabilizing the read current of non-volatile memory cells of the type of FIG. 1 to improve read operation accuracy and memory retention longevity. The read stabilization technique involves programing the finished and operational memory cell to a predetermined program state before performing a final high temperature bake process. Specifically, during the memory device testing process, the memory array in the device can undergo many thermal operations with various data patterns. However, once the memory device testing is complete, all the memory cells are then programmed to a predetermined mid-program state, which is then followed by a final, high temperature bake of the memory device. It has been discovered that by performing this final, high temperature bake while the memory cells are programmed to the mid-program state, memory cell threshold voltage (Vt) shift over time, and thus read operation current drift over time, is reduced.

[0020] The desired mid-program state is a function of the controller configuration for the memory array, which can be better understood from the architecture of an exemplary memory device as illustrated in FIG. 2. The memory device includes an array 50 of the non-volatile memory cells 10, which can be segregated into two separate planes (Plane A 52a and Plane B 52b). The memory cells 10 can be of the type shown in FIG. 1, formed on a single chip, arranged in a plurality of rows and columns in the semiconductor substrate 12. Adjacent to the array of non-volatile memory cells are address decoders (e.g. XDEC 54), a source line driver (e.g. SLDRV 56), a column decoder (e.g. YMUX 58), a high voltage row decoder (e.g. HVDEC 60) and a bit line controller (BLINHCTL 62), which are used to decode addresses and supply the various voltages to the various memory cell gates and regions during read, program, and erase operations for selected memory cells. Column decoder 58 includes a sense amplifier containing circuitry for measuring the currents on the bit lines during a read operation. Controller 66 (containing control circuitry) controls the various device elements to implement each operation (program, erase, read) on target memory cells. Charge pump CHRGPMP 64 provides the various voltages used to read, program and erase the memory cells under the control of the controller 66. Controller 66 is configured to operate the memory device to program, erase and read the memory cells 10.

[0021] It is the controller 66 that dictates the minimum and maximum program states of the memory cells that are usable during normal user operation. The minimum program state is that programming state to which each of the memory cells can be programmed (i.e., the most erased state), under the control of the controller 66 during normal user operation, for which the lowest number of electrons are located on the floating gate 20 and the memory cell produces the highest (maximum) source/drain current during a normal read operation. The maximum program state is that programming state to which each of the memory cells can be programmed, under the control of the controller 66 during normal user operation, for which the highest number of electrons are located on the floating gate 20 and the memory cell produces the lowest (minimum) source/drain current during a normal read operation.

[0022] The mid-program state that is used during the final device high temperature bake operation is preferably that program state that produces a read current during a read operation that is logarithmically the substantial mid-point between the minimum and the maximum read currents for the maximum and minimum program states, respectively, of the defined programming operating range as dictated by the controller 66. The mid-program state can be determined by means of either threshold voltage Vt or read current as a parameter. The memory cell is a MOSFET transistor, and thus Vt and read current are directly related via basic transistor equations, therefore, the memory cell operating range can be determined in terms of either read current or Vt. An example of memory cell current-voltage (I-V) characteristics which demonstrate the relationship between Vt and read current is shown in FIG. 3, where the two curves represent the I-V characteristics for the minimum and maximum program states for the memory cell, respectively. In this non-limiting example, placing a voltage on the control gate at or above the threshold voltage will result in a read current (between the source and drain regions) during a read operation that is 1 A or greater, which is considered to be the amount of current in this example indicative that the conductive path between the source/drain regions is created. The rightward inflection of the current-voltage (I-V) curves at 1 A in FIG. 3 indicates that is the read current which is achieved when the voltage on the control gate has reached threshold voltage Vt.

[0023] In the example of FIG. 3, the right-hand curve (Curve A) is the I-V curve for the exemplary memory cell in its maximum programmed state of its analog operating range, and the left-hand curve (Curve B) is the I-V curve for the exemplary memory cell in its minimum programmed state of its analog operating range. The controller for this memory cell is configured to use a read voltage on the control gate of 1.2 V, which means this memory cell is read in a subthreshold state (i.e., using subthreshold current to detect the program state of the memory cell). Given the two I-V curves for maximum programmed and minimum programmed states, the operating range of the read current for this memory cell as operated by the controller is between 100 nA and 100 pA. The range of programming states corresponds to a Vt range of about 0.3V (between about 1.3V and about 1.6V). A read instability of the programmed memory cell can be represented either in terms of Vt variations, or in terms of read current variations during read operations. As set forth below, either Vt or read current can be used as a parameter to quantify the solution of read current fluctuation reduction. Therefore, the mid-program state is defined as program state that corresponds to substantially a halfway in terms of Vt for the minimum and the maximum program states achievable during normal operation, and corresponds to logarithmically the substantial mid-point between the minimum and the maximum read currents for the maximum and minimum program states, respectively.

[0024] There are three major stages to implementing this read stabilization technique, as illustrated in FIG. 4. First (step 1), the memory device, including the memory cells 10 and their controller 66, are tested to the point that they are operational and no further high temperature bake operations are needed to complete the testing of the device. Second (step 2), all the memory cells 10 are programmed to substantially the mid-program state. Third (step 3), the memory device including all the memory cells 10 programmed to the mid-program state are subjected to a final high temperature bake process. FIG. 5 shows an example of the memory cell I-V characteristic curve (Curve C) for a memory cell described above with respect to FIG. 3 programmed to substantially a mid-program state. Its threshold voltage Vt is about 1.48V, which is substantially at a mid-point between Vt_min and Vt_max for the minimum and maximum programmed states, respectively (i.e., the mid-point threshold voltage is substantially half way between Vt_min and Vt_max). Similarly, the read current of the memory cell when the read voltage of 1.2 V is placed on the control gate during a read operation is about 3 nA, which is logarithmically the substantial mid-point between 100 nA and 100 pA for the minimum and maximum programmed states, respectively (i.e., the mid-point read current is substantially half way between 100 nA and 100 pA on a logarithmic scale).

[0025] The high bake temperature is an elevated temperature which exceeds the highest operating temperature endured by the memory device during normal use. For example, the final high temperature bake process can include baking the memory device for 24 hours at 175 C. if specification for the highest operating temperature for the product under user conditions is 150 C. The minimum bake time depends on bake temperature and can be shorter at higher temperatures. Preferably, for the memory cell shown in FIG. 1, the bake time can be up to 24 hours at a bake temperature of 175 C. In general, the longer bake time, the better improvement effect on read instability reduction. As a practical example, one can set assembled parts for one-day bake at 175 C. if chosen package allows such high temperature treatment. Once the memory device, packaging and final testing and bake are complete, the memory device will operate with improved read stability under user conditions.

[0026] It is to be understood that the present invention is not limited to the embodiment(s) described above and illustrated herein, but encompasses any and all variations falling within the scope of any claims. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more of the claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Further, as is apparent from the claims and specification, not all method steps may need to be performed in the exact order illustrated or claimed unless specified.