STACKING INTEGRATED CIRCUITS CONTAINING SERIALIZER AND DESERIALIZER BLOCKS USING THROUGH VIA

Abstract

Methods and systems for stacking multiple chips with high speed serializer/deserializer blocks are presented. These methods make use of Through Via (TV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serializer/deserializer blocks, using the TVs.

Claims

1. A system comprising: a die stack, wherein the die stack includes at least: a first die, a second die, a third die, the second die is stacked vertically on top of the first die, and the third die is stacked horizontally in relation to the first die and/or the second die; one or more Redistribution Layer(s); one or more Through Via(s); one or more Serial I/O(s); one or more contact pad(s), wherein said one or more contact pad(s) is/are located along at least one edge of the first die; one or more passive component(s); and a substrate, wherein said first die and/or said second die and/or said third die includes said one or more Through Via(s) and said one or more Serial I/O(s), said one or more Serial I/O(s) is/are configured to communicate through said one or more Through Via(s) and/or through said one or more Redistribution Layer(s), said one or more Through Via(s) is/are configured to route and connect to said one or more contact pad(s) on said die stack which is coupled to said substrate, and said one or more passive component(s) is/are coupled to said substrate.

2. A system comprising: a plurality of dies, wherein said plurality of dies include at least a first die and a second die; one or more Redistribution Layer(s); one or more Through Via(s); one or more memory block(s); one or more Serial I/O(s); and one or more contact pad(s), wherein said one or more die(s) contain(s) said one or more memory block(s) and/or Serial I/O(s), said plurality of dies are formed in a vertical stack configuration by being stacked one on top of another, said one or more Through Via(s) is/are placed in said one or more memory block(s) and/or Serial I/O(s), said first die and said second die are stacked directly in contact with one another, said first die and said second die are stacked where said one or more Redistribution Layer(s) are not stacked between them, said plurality of dies are coupled to said one or more Redistribution Layer(s), said one or more contact pad(s) is/are placed on said one or more Redistribution Layer(s), said plurality of dies are coupled to said one or more contact pad(s), and said plurality of dies are coupled to said one or more Redistribution Layer(s).

3. The system according to claim 1, further comprising: one or more wirebond(s), wherein said first die and/or said second die is wirebonded to said substrate and/or said one or more contact pad(s).

4. The system according to claim 1, wherein said first die and said second die are stacked where said one or more Redistribution Layer(s) are not stacked between them.

5. The system according to claim 2, further comprising: one or more wirebond(s), wherein one of said a plurality of dies is/are wirebonded to said substrate and/or said one or more contact pad(s) and/or said one or more Redistribution Layer(s).

6. The system according to claim 2, wherein said plurality of dies comprises of memory blocks.

7. The system according to claim 2, wherein one of said plurality of dies is a non-memory die.

8. The system according to claim 2, wherein only one of said plurality of dies comprises of said one or more Serial I/O(s).

9. The system according to claim 2, wherein at least one die of said plurality of dies has no Through Via(s).

10. The system according to claim 1, wherein at least one die of said plurality of dies has no Through Via(s).

11. A system comprising: a plurality of dies, wherein said plurality of dies include at least a first die, a second die and a third die; one or more Through Via(s); one or more memory block(s); and one or more Serial I/O(s), wherein one of said plurality of die(s) contains said one or more memory block(s) and/or Serial I/O(s), said plurality of dies are formed in a vertical stack configuration by being stacked one on top of another, said second die is stacked on top of first die, said third die is stacked on top of second die, said one or more serial I/O(s) comprises of at least a first type of serial I/O(s) and a second type of serial I/O(s), said first type of serial I/O(s) is a different type as compared to said second type of serial I/O(s), said first die contains said first type of serial I/O(s) and said second type of serial I/O(s), said second die contains said first type of serial I/O(s) and/or said Through Via(s), said third die contains said one or more Through Via(s) and said one or more memory block(s), said first die is configured to communicate with said second die through said first type of serial I/O(s), and said third die is configured to communicate with said second die through said first type of serial I/O(s).

12. The system according to claim 11, wherein at least one die of said plurality of dies has no Through Via(s).

13. The system according to claim 11, wherein at least one die of said plurality of dies contains said one or more Through Via(s).

14. The s stem according to claim 11, wherein said plurality of dies contains no Through Via(s).

15. The system according to claim 11, wherein said first type of serial I/O(s) and/or said second type of serial I/O(s) is situated on the periphery of said plurality of dies.

16. The system according to claim 11, wherein said plurality of dies are coupled to each other using micro bumps and/or metal bonding.

17. The system according to claim 11, wherein said first die is surrounded by molding compound.

18. The system according to claim 11, wherein said first type of serial I/O(s) is configured to communicate with said second type of serial I/O(s).

19. The system according to claim 11, wherein said first die contains a memory block.

20. The system according to claim 11, wherein said plurality of dies contains more than two or more different types of serial I/O(s).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIG. 1 shows an example of chip with wirebonded package.

[0018] FIG. 2 shows an example of chip with Flip Chip package.

[0019] FIG. 3 shows an example of stacked die packing of two chips of the same size using wirebond.

[0020] FIG. 4 shows an example of stacked die packing of two chips with a separate SER/DES die in the same package using wirebond.

[0021] FIG. 5 shows an example of Trough Silicon Via (TSV) on the SER/DES blocks of a chip placed at the peripheries of the chip.

[0022] FIG. 6 shows three stacked chips connected to substrate via TSVs.

[0023] FIG. 7 shows redistribution layer (Interposer) that is used to route and connected TSVs and Pads.

[0024] FIG. 8 shows two chips with TSVs connected to each other through a redistribution layer (Interposer).

[0025] FIG. 9 shows TSVs of one chip connected to the pads of another chip through a redistribution layer (Interposer).

[0026] FIG. 10 shows the location of test pads at the very edge of dice, when they are stacked on each other.

[0027] FIG. 11A is a side view of an interposer having formed therein a TSV, in accordance with one embodiment of the present invention.

[0028] FIG. 11B is a side view of an interposer having disposed therein a passive component, in accordance with one embodiment of the present invention.

[0029] FIG. 11C is a side view of an interposer having a multitude of solder balls disposed on its top surface, in accordance with one embodiment of the present invention.

[0030] FIG. 11D is a side view of an interposer having an adhesive layer formed on its top surface, in accordance with one embodiment of the present invention.

[0031] FIG. 12A illustrates dies 1707 with TSV 650 stacked on the top of a Ser/Des die/substrate 1708 where TSV 780 and RDL 706 is used to connect the contact pad 704 to TSV 780 and die/substrate 1708 is coupled to die/substrate 1700 using solder bumps 782 in accordance with at least one embodiment of the present invention.

[0032] FIG. 12B illustrates die/substrate 1708, where wirebond 709 is used to couple the die/substrate contact pad 704 to die/substrate 1700 contact pad 704 in accordance with at least one embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] To create a more compact and space efficient integrated circuit, it is necessary to be able to stack multiple dice on top of each other. Two general methods are possible for interconnecting the stacked dice to each other and for connecting those dice to the pins or solder balls of the 3D chip package. One method is to use wirebond, meaning that to use wires to connect chips to each other or to the pins of the 3D package as shown in FIG. 3 and FIG. 4. The wirebond technique is not very useful for high speed SER/DES due to creation of inductance and capacitance.

[0034] Another technique is to use Through Silicon Via (TSV) to connect multiple stacked dice to each other or to the external pins. FIG. 8 shows an example of TSVs (801, 803) of two dice (802, 804) connected to each other. While FIG. 9 shows the contact pads (901) of one die (902) is connected to the TSVs (903) of another die (904) using RDLs (906). FIG. 9 illustrates an interposer (substrate) (905). TSVs has so far been only used for lower speed integrated circuits. This patent extends the TSV technology for usage with high speed SER/DES circuits. Doing so would eliminate the need for wirebond and would create a more compact package with superior electrical and thermal characteristics.

[0035] And, finally, to test dice which are stacked on each other, test pads need to be created for each die. The test pads must be located at the extreme periphery or edge of dice. FIG. 10 shows two dice (1001, 1003) are stacked on top of each other, They both have TSVs (1005) and the test pads (1002, 1004) are placed at the edge of these dice.

[0036] In order to successfully use TSV for the SER/DES circuits a number of rules have to be followed. This patent provides the techniques for using TSV in high speed SER/DES block of chips that could be used for connecting the SER/DES circuit to external pins.

[0037] The first technique is to have the SER/DES blocks that use TSV at one or more peripheries of the die. FIG. 5 is an example of such method in which four SER/DES blocks (501) are used at the four peripheries of the die (503) and the SER/DES blocks are equipped with TSVs (502) that can be used to pass through lower dice and get connected to external pins or other dice.

[0038] The second technique is to try to limit the SER/DES blocks that use TSV to one or more peripheries of the die and rotate the upper and lower stacked dice by 90 degrees or have the SER/DES staggered so that the SER/DES blocks of those dice will not block each other. This method makes the TSV creation and routing in the interposer layer much easier.

[0039] The third technique is to use a redistribution layer (RDL) or interposer when TSVs of the lower and upper die can't be aligned to each other. Redistribution layer (RDL) is used to route and connect TSV to contact pad. The trace routes can be of any shape, angle or material. There could be solder resist on the top of RDL and adhesive such as (BCB), etc. FIG. 6 shows an example in which the TSVs (602, 603, 604 and 605) of 3 stacked dice are aligned to each other and therefore no RDL is required. FIG. 6 illustrates three stacked chips connected to a substrate having a die (601) and an interposer (substrate) (606). While FIG. 7 shows an example, in which the TSVs of the two dice (706, 708) are not aligned to each other and therefore an RDL (707) is required between two dice (706, 708) to route the TSVs. The RDL may contain TSV, blind via, buried via, or any combination of via. The RDL may or may not contain plans, or passive elements such as capacitors. FIG. 8 shows another example of a RDL (806) that is used to connect the via (801) of the top die (802) to the via (803) of the bottom die (804). FIG. 8 illustrates an interposer (substrate) (805).

[0040] FIG. 11A is a side view of interposer 707 shown as including a TSV 750, in accordance with one embodiment of the present invention. FIG. 11B is a sideview of interposer 707 shown as including a passive component, such as capacitor 752, in accordance with one embodiment of the present invention. FIG. 11C is a sideview of interposer 707 shown as including solder balls 754 on its top surface, in accordance with one embodiment of the present invention. FIG. 11D is a sideview of interposer 707 shown as including adhesive layer 756 on its top surface, in accordance with one embodiment of the present invention.

[0041] The fourth technique is the method for aligning stacked dice. Dice can be aligned using fiducials of any type, such as cross, square, circle, +, , =, etc, or any text character. Fiducials can be used on the interposer and/or dice for the purpose of alignment. The interposer and dice can have one, two or as many Fiducials, as needed.

[0042] The fifth technique is to create (deposit) contact pads on RDL to create a contact point for the other dice TSV. This pad can of any material, size or shape. A circular contact pad (704) is shown in FIG. 7 that resides in the RDL (707). The contact pad (704) is used to connect the TSV of the upper layer dice (708) to the trace (705) on the RDL and subsequently to the TSV of the lower die (702).

[0043] The sixth technique is use tear drops for connecting traces on the RDL to TSVs for the purposes of reinforcement and stress reduction. FIG. 7 shows an example of a tear drop (709) on the TSV of the lower die (702).

[0044] The seventh technique is mix wirebond and TSV in stacked chips. Wirebond could be used for low speed digital circuits, while TSV could be used for the high speed SER/DES circuits. For example, FIG. 12A shows dies 1707 with TSV 650 stacked on the top of a Ser/Des die/substrate 1708 where TSV 780 and RDL 706 is used to connect the contact pad 704 to TSV 780 and die/substrate 1708 is coupled to die/substrate 1700 using solder bumps 782. In another example, FIG. 12B shows die/substrate 1708, where wirebond 709 is used to couple the die/substrate contact pad 704 to die/substrate 1700 contact pad 704.

[0045] The eight technique is to place the test pads for testing a dies that uses TSV at the extreme periphery of the die.

[0046] Any variations of the above are also intended to be covered by the application here.