ANALOG INTEGRATED CIRCUIT WITH IMPROVED TRANSISTOR LIFETIME AND METHOD FOR MANUFACTURING THE SAME

Abstract

In one aspect, a method for manufacturing an analog integrated circuit with improved transistor lifetime includes steps of: providing a P-type substrate; forming N+ source/drain regions; forming a P.sup.+ isolation island to separate a high voltage I/O transistor and low voltage core transistor; patterning a SiON dielectric layer on one side of the P.sup.+ isolation island for the high voltage I/O transistor; patterning a SiO.sub.2 dielectric layer on the other side of the P.sup.+ isolation island for the low voltage core transistor; forming a gate structure for the low voltage core transistor and high voltage I/O transistor; forming a gate polysilicon layer on a top portion of each of the SiO.sub.2 and SiON dielectric layers; forming a SiON passivation layer with open holes; and forming a source electrode, a gate electrode and a drain electrode for each of the low voltage core transistor and high voltage I/O transistor.

Claims

1. An analog integrated circuit with improved transistor lifetime comprising: a substrate of a first conductivity type; a plurality of source/drain regions of a second conductivity type; a first gate oxide of a high voltage (input/output) I/O transistor; a second gate oxide of a low voltage core transistor; an isolation island of the first conductivity type to separate the high voltage I/O transistor and low voltage core transistor; a gate polysilicon formed on a top portion of each of the first gate oxide and second gate oxide; a SiON passivation layer; and a drain electrode, source electrode and gate electrode for each of the low voltage core transistor and high voltage I/O transistor, wherein the first gate oxide is a SiON dielectric layer, which is used to improve the lifetime of the I/O transistor device in the analog integrated circuit; and the second gate oxide is a SiO.sub.2 dielectric layer, which is used to remain high noise robustness in the analog integrated circuits.

2. The analog integrated circuit with improved transistor lifetime of claim 1, wherein the substrate is a P-type substrate.

3. The analog integrated circuit with improved transistor lifetime of claim 1, wherein the source/drain regions are N.sup.+ source/drain regions.

4. The analog integrated circuit with improved transistor lifetime of claim 1, wherein the isolation island is a heavily doped P-type region to separate the low voltage core transistor device from the high voltage I/O transistor device.

5. The analog integrated circuit with improved transistor lifetime of claim 1, wherein the SiON passivation layer has a plurality of open holes on top of the drain/source regions and the gate polysilicon for both the high voltage I/O transistor and low voltage core transistor.

6. The analog integrated circuit with improved transistor lifetime of claim 5, wherein the drain/source electrodes and gate electrode are formed when metal is filled into the open holes on top of the drain/source regions and the gate polysilicon for both the high voltage I/O transistor and low voltage core transistor.

7. A manufacturing method for an analog integrated circuit with improved transistor lifetime comprising steps of: providing a substrate of a first conductivity type; forming a plurality of source/drain regions of a second conductivity type at the top portion of the substrate; forming an isolation island to separate a high voltage (input/output) I/O transistor and a low voltage core transistor; depositing and patterning a SiON dielectric layer on one side of the P.sup.+ isolation island for the high voltage I/O transistor; depositing and patterning a SiO.sub.2 dielectric layer on the other side of the P.sup.+ isolation island for the low voltage core transistor; forming a gate structure for the low voltage core transistor and the high voltage I/O transistor by patterning the SiO.sub.2 and SiON dielectric layers; forming a gate polysilicon layer on a top portion of each of the SiO.sub.2 and SiON dielectric layers; forming a SiON passivation layer with a plurality of open holes on top of both the high voltage I/O transistor and low voltage core transistor; forming a source electrode, a gate electrode and a drain electrode for the low voltage core transistor; and forming a source electrode, a gate electrode and a drain electrode for the high voltage I/O transistor.

8. The manufacturing method for an analog integrated circuit with improved transistor lifetime of claim 7, wherein the step of providing a substrate of a first conductivity includes the step of diffusing or implanting P-type dopants, such as boron or aluminum ions to create a P well or a P-type substrate.

9. The manufacturing method for an analog integrated circuit with improved transistor lifetime of claim 7, wherein the step of forming a plurality of source/drain regions of a second conductivity type includes the step of diffusing or implanting N-type dopants, such as nitrogen or phosphorus ions to create N.sup.+ regions in the substrate for both the low voltage core transistor and high voltage I/O transistor.

10. The manufacturing method for an analog integrated circuit with improved transistor lifetime of claim 7, wherein the step of forming an isolation island includes the step of diffusing or implanting P-type dopants, such as boron or aluminum ions to create the P.sup.+ isolation island.

11. The manufacturing method for an analog integrated circuit with improved transistor lifetime of claim 7, wherein the step of depositing and patterning a SiON dielectric layer on a high voltage I/O transistor includes steps of conducting thermal oxidation or deposition of SiON dielectric layer on top of the substrate, and etching away the SiON dielectric layer on the low voltage core transistor side.

12. The manufacturing method for an analog integrated circuit with improved transistor lifetime of claim 11, wherein the step of etching away the SiON dielectric layer on the low voltage core transistor side includes the step of conducting a dry etching technique to etch away the SiO.sub.2 dielectric layer on the high voltage I/O transistor side.

13. The manufacturing method for an analog integrated circuit with improved transistor lifetime of claim 7, wherein the step of depositing and patterning a SiO.sub.2 dielectric layer on a low voltage core transistor includes steps of conducting thermal oxidation or deposition of SiO.sub.2 dielectric layer on top of the substrate, and etching away the SiO.sub.2 dielectric layer on the high voltage I/O transistor side.

14. The manufacturing method for an analog integrated circuit with improved transistor lifetime of claim 13, wherein the step of etching away the SiO.sub.2 dielectric layer on the high voltage I/O transistor side includes a step of conducting a dry etching technique to etch away the SiO.sub.2 dielectric layer on the high voltage I/O transistor side.

15. The manufacturing method for an analog integrated circuit with improved transistor lifetime of claim 7, wherein the step of forming a source electrode, a gate electrode and a drain electrode for the low voltage core transistor includes the step of filling metal into the open holes of the SiON passivation layer on top of the source, the gate and the drain regions of the low voltage core transistor.

16. The manufacturing method for an analog integrated circuit with improved transistor lifetime of claim 7, wherein the step of forming a source electrode, a gate electrode and a drain electrode for the high voltage I/O transistor includes the step of filling metal into the open holes of the SiON passivation layer on top of the source, the gate and the drain regions of the high voltage I/O transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG. 1 is a cross-section view of the analog integrated circuit with improved transistor lifetime in the present invention.

[0024] FIGS. 2A-2E illustrate cross-section views of a method for manufacturing an analog integrated circuit with improved transistor lifetime in the present invention.

[0025] FIG. 3 illustrates a flow diagram of a method for manufacturing an analog integrated circuit with improved transistor lifetime in the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0026] The detailed description set forth below is intended as a description of the presently exemplary device provided in accordance with aspects of the present invention and is not intended to represent the only forms in which the present invention may be prepared or utilized. It is to be understood, rather, that the same or equivalent functions and components may be accomplished by different embodiments that are also intended to be encompassed within the spirit and scope of the invention.

[0027] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood to one of ordinary skill in the art to which this invention belongs. Although any methods, devices and materials similar or equivalent to those described can be used in the practice or testing of the invention, the exemplary methods, devices and materials are now described.

[0028] All publications mentioned are incorporated by reference for the purpose of describing and disclosing, for example, the designs and methodologies that are described in the publications that might be used in connection with the presently described invention. The publications listed or discussed above, below and throughout the text are provided solely for their disclosure prior to the filing date of the present application. Nothing herein is to be construed as an admission that the inventors are not entitled to antedate such disclosure by virtue of prior invention.

[0029] As used in the description herein and throughout the claims that follow, the meaning of a, an, and the includes reference to the plural unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the claims that follow, the terms comprise or comprising, include or including, have or having, contain or containing and the like are to be understood to be open-ended, i.e., to mean including but not limited to. As used in the description herein and throughout the claims that follow, the meaning of in includes in and on unless the context clearly dictates otherwise.

[0030] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items.

[0031] In one aspect, as shown in FIG. 1, an analog integrated circuit with improved transistor lifetime may include a substrate 101, an N.sup.+ drain/source region 102, a P.sup.+ isolation island 103, a SiON dielectric gate oxide layer 104 for a high voltage I/O transistor, an SiO.sub.2 dielectric gate oxide layer 105 for a low voltage core transistor, a gate polysilicon 106, an SiON passivation layer 107, a source electrode 108 for the low voltage core transistor, a gate electrode 109 for the low voltage core transistor, a drain electrode 110 for the low voltage core transistor, a drain electrode 111 for the high voltage I/O transistor, a gate electrode 112 for the high voltage I/O transistor, and a source electrode 113 for the high voltage I/O transistor.

[0032] In one embodiment, the substrate 101 is either a P well or a P-type substrate, and the N.sup.+ drain/source region 102 is a heavily doped N-type region, and connected with the drain/source electrode on each side. The P.sup.+ isolation island 103 is a heavily doped P-type region to isolate the low voltage core transistor device from the high voltage I/O transistor device.

[0033] It is important to note that the gate oxide 104 for a high voltage I/O transistor device is a SiON dielectric layer, which is used to improve the lifetime of the I/O transistor device in analog integrated circuit. On the other hand, the gate oxide 105 for the low voltage core transistor device is SiO.sub.2 dielectric layer, which is just the same as traditional method to remain the high noise robustness of analog integrated circuits.

[0034] In a further embodiment, the gate polysilicon 106 is located on a top portion of the gate oxide layer for the gate signal conduction, and the SiON passivation layer 107 is located on top of the transistor to protect it from an outer environment. It is noted that the source electrode 108 is a metal filled into the hole of SiON passivation 107, which is located on top of the N.sup.+ source region in the low voltage core transistor; the gate electrode 109 is a metal filled into the hole of SiON passivation 107, which is located on top of the gate polysilicon 106 in the low voltage core transistor; and the drain electrode 110 is a metal filled into the hole of SiON passivation 107, which is located on top of the N.sup.+ drain region in low voltage core transistor.

[0035] Likewise, on the high voltage I/O transistor side, the drain electrode 111 is a metal filled into the hole of SiON passivation 107, which is located on top of the N.sup.+ drain region in the high voltage I/O transistor; the gate electrode 112 is a metal filled into the hole of SiON passivation 107, which is located on top of the gate polysilicon in the high voltage I/O transistor; and the source electrode 113 is a metal filled into the hole of SiON passivation 107, which is located on top of the N.sup.+ drain region in the high voltage I/O transistor.

[0036] In another aspect, as shown in FIGS. 2A to 2E, a method for manufacturing an analog integrated circuit with improved transistor lifetime may include steps of: providing a P-type substrate (201); forming a plurality of N.sup.+ source/drain regions at the top portion of the substrate (202); forming a P.sup.+ island to separate a high voltage I/O transistor and a low voltage core transistor (203); depositing and patterning a SiON dielectric layer on one side of the P.sup.+ isolation island for the high voltage I/O transistor (204); depositing and patterning a SiO.sub.2 dielectric layer on the other side of the P.sup.+ isolation island for the low voltage core transistor (205); forming a gate structure for the low voltage core transistor and the high voltage I/O transistor by patterning the SiO.sub.2 and SiON dielectric layers (206); forming a gate polysilicon layer on a top portion of each of the SiO.sub.2 and SiON dielectric layers (207); forming a SiON passivation layer with a plurality of open holes on top of both the high voltage I/O transistor and low voltage core transistor (208); forming a source electrode, a gate electrode and a drain electrode for the low voltage core transistor (209); and forming a source electrode, a gate electrode and a drain electrode for the high voltage I/O transistor (210).

[0037] In one embodiment, the step of providing a P-type substrate (201) may include the step of diffusing or implanting P-type dopants, such as boron or aluminum ions to create a P well or a P-type substrate. The step of forming a plurality of N.sup.+ source/drain regions (202) may include the step of diffusing or implanting N-type dopants, such as nitrogen or phosphorus ions to create N.sup.+ regions in the substrate for both the low voltage core transistor and high voltage I/O transistor.

[0038] In another embodiment, the step of forming a P.sup.+ isolation island (203) may include the step of diffusing or implanting P-type dopants, such as boron or aluminum ions to create the P.sup.+ isolation island, which is used to separate the low voltage core transistor from the high voltage I/O transistor.

[0039] In still another embodiment, the step of depositing and patterning a SiON dielectric layer on a high voltage I/O transistor (204) may include steps of conducting thermal oxidation or deposition of SiON dielectric layer on top of the substrate, and etching away the SiON dielectric layer on the low voltage core transistor side. In a further embodiment, the etching techniques may include dry etching techniques.

[0040] Likewise, the step of depositing and patterning a SiO.sub.2 dielectric layer on a low voltage core transistor (205) may include steps of conducting thermal oxidation or deposition of SiO.sub.2 dielectric layer on top of the substrate, and etching away the SiO.sub.2 dielectric layer on the high voltage I/O transistor side. In a further embodiment, the etching techniques may include dry etching techniques.

[0041] In a still a further embodiment, the step of forming a source electrode, a gate electrode and a drain electrode for the low voltage core transistor (209) may include the step of filling metal into the open holes of the SiON passivation layer on top of the source, the gate and the drain regions of the low voltage core transistor.

[0042] Likewise, the step of forming a source electrode, a gate electrode and a drain electrode for the high voltage I/O transistor (210) may include the step of filling metal into the open holes of the SiON passivation layer on top of the source, the gate and the drain regions of the high voltage I/O transistor.

[0043] It is important to note that in the invention, the SiON dielectric layer is used to form the gate oxide layer for the high voltage I/O transistor 104. Instead of traditional SiO.sub.2 based gate oxide layer for both high voltage I/O transistor and low voltage core transistor, the SiON dielectric layer is used in the present invention to improve the lifetime of the high voltage I/O transistor for the analog integrated circuit. On the other hand, the high noise-resistant performance for the low voltage core transistor can be remained because of the SiO.sub.2 dielectric layer on the low voltage side.

[0044] The present invention is advantageous because the analog integrated circuit has different gate oxide layers for the high voltage I/O transistor device and low voltage core transistor device. More specifically, the gate oxide layer 104 for the high voltage I/O transistor device uses the SiON dielectric layer to improve the lifetime, while the SiO.sub.2 dielectric layer 105 is used for the low voltage core transistor device for the noise resistance. Since the SiN dangling bond in SiON gate oxide layer 104 has a higher activation energy than SiH dangling bond in SiO.sub.2 gate oxide layer 105, in metal-oxide-semiconductor field effect transistors, the use of SiON dielectric layer as the gate oxide layer can improve the device lifetime by two orders of magnitude.

[0045] Having described the invention by the description and illustrations above, it should be understood that these are exemplary of the invention and are not to be considered as limiting. Accordingly, the invention is not to be considered as limited by the foregoing description, but includes any equivalent.