Oxide semiconductor device and method for manufacturing same
10896978 ยท 2021-01-19
Assignee
Inventors
Cpc classification
H01L29/66969
ELECTRICITY
H01L29/786
ELECTRICITY
International classification
H01L29/786
ELECTRICITY
Abstract
In an oxide semiconductor device including an active layer region constituted by an oxide semiconductor, stability when a stress is applied is improved. The oxide semiconductor device includes an active layer region constituted by an oxide semiconductor of indium (In), gallium (Ga), and zinc (Zn), wherein the active layer region contains an element selected from titanium (Ti), zirconium (Zr), and hafnium (Hf) that are Group 4 elements, or carbon (C), silicon (Si), germanium (Ge), and tin (Sn) that are Group 14 elements at a number density in a range of 110.sup.16 to 110.sup.20 cm.sup.3.
Claims
1. An oxide semiconductor device comprising: an active layer region constituted by an oxide semiconductor of indium (In), gallium (Ga), and zinc (Zn), wherein the active layer region contains an element selected from titanium (Ti), zirconium (Zr), and hafnium (Hf) that are Group 4 elements, or carbon (C), silicon (Si), germanium (Ge), and tin (Sn) that are Group 14 elements at a number density in a range of 110.sup.16 to 110.sup.20 cm.sup.3.
2. The oxide semiconductor device according to claim 1, wherein the active layer region is a region that is irradiated with a laser having a wavelength of 400 nm or less and annealed.
3. A method for manufacturing an oxide semiconductor device including an active layer region constituted by an oxide semiconductor of indium (In), gallium (Ga), and zinc (Zn), the method comprising the steps of: implanting an ion of an element selected from titanium (Ti), zirconium (Zr), and hafnium (Hf) that are Group 4 elements, or carbon (C), silicon (Si), germanium (Ge), and tin (Sn) that are Group 14 elements at a number density in a range of 110.sup.16 to 110.sup.20 cm.sup.3 into the active layer region; and irradiating the active layer region into which the ion is implanted, with a laser having a wavelength of 400 nm or less to anneal the active layer region.
Description
BRIEF DESCRIPTION OF DRAWINGS
(1)
(2)
(3)
DESCRIPTION OF EMBODIMENT
(4) Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
(5) With regard to materials of the respective terminals, for example, the gate 11, the source 14, and the drain 15 are constituted by TiN, and the gate insulation film 12 and the passivation film 16 are constituted by SiO.sub.2. As will be described later, the channel layer 13 serving as an active layer region is constituted by an oxide semiconductor of In, Ga, and Zn (IGZO) into which a specific element is implanted. The TFT 1 has the function of applying voltage to the gate 11 to control a current flowing to the channel layer 13 and switch the current between the source 14 and the drain 15.
(6) The elements implanted into the channel layer 13 are Ti, Zr, and Hf that are Group 4 elements or C, Si, Ge, and Sn that are Group 14 elements. Hereinafter, although a description will be made by taking the case where Si is implanted as an example, each of the elements mentioned above can achieve the same effect. With regard to the element implantation amount, the element in an amount that allows a material other than a bulk material to function as an impurity is implanted into the oxide semiconductor and, with this, it is possible to improve a TFT characteristic resulting from a defect caused by oxygen deficiency, particularly stability of a threshold voltage. The preferable element implantation amount is a number density in a range of 110.sup.16 to 110.sup.20 cm.sup.3.
(7) Hereinafter, a specific process example (Example 1) for obtaining the TFT 1 having the constitution shown in
(8) Next, the gate insulation film 12 is formed by depositing S.sub.iO.sub.2 using the plasma CVD (gas SiH.sub.4, O.sub.2, Ar). The material of the gate insulation film 12 is not limited to SiO.sub.2 and may also be a silicon nitride film or Al.sub.2O.sub.3.
(9) Thereafter, by using a target of an IGZO (In:Ga:Zn=1:1:1), the channel layer 13 is deposited by sputtering. As an example of deposition conditions, a film thickness was set to 50 nm, pressure was set to 5 m Torr and O.sub.2 partial pressure was set to 16% in an Ar/O.sub.2 atmosphere. In this deposition, it is possible to use, e.g., a rotary magnet sputtering apparatus. The element ratio of the IGZO in the channel layer 13 is not limited to the above-described ratio (In:Ga:Zn=1:1:1).
(10) Note that the above-described O.sub.2 partial pressure of 16% is a condition under which an amount of oxygen deficiency is equal to or less than 110.sup.17 cm.sup.3 after anneal at 400 C. in a water vapor atmosphere that is performed later. On the other hand, in a conventional IGZO film (channel layer) into which the element is not implanted, deposition is performed at the O.sub.2 partial pressure of 2%. In this case, the amount of oxygen deficiency after anneal is performed at 400 C. is about 110.sup.18 cm.sup.3.
(11) After the deposition described above, Si is implanted into the channel layer 13 of the IGZO by using an ion implantation apparatus. As an example of implantation conditions, a Si.sup.+ ion was used, an energy was set to 40 keV, and a dose amount was set to 110.sup.13 cm.sup.2. With this, a Si atom was implanted into the IGZO film at a density of 110.sup.18 cm.sup.3. The density of the Si atom in the IGZO is set to 110.sup.16 to 110.sup.20 cm.sup.3 and is preferably set to 110.sup.17 to 110.sup.19 cm.sup.3.
(12) After the implantation of Si, anneal is performed for one hour at 400 C. in a wet atmosphere (H.sub.2O/O.sub.2=100/900 sccm). The anneal temperature is not limited to 400 C., is from 300 C. to 800 C. and is preferably from 350 C. to 500 C. The atmosphere in which the anneal is performed is not limited to the wet atmosphere and may also be an oxygen atmosphere.
(13) The IGZO film into which Si is implanted is patterned by photolithography and etching after being subjected to the above-described anneal, and the island-shaped channel layer 13 is thereby formed.
(14) Thereafter, TiN forming the source 14 and the drain 15 is deposited to a thickness of, e.g., 150 nm, and the source 14 and the drain 15 are formed by photolithography and etching. The material of the source 14 and the drain 15 is not limited to Ti and may also be Al, Ti, Mo, or W. Thereafter, SiO.sub.2 forming the passivation film 16 is deposited by the plasma CVD or the like, and a connection terminal is then formed so as to be able to come into electrical contact with the individual terminals (the source 14, the drain 15, and the gate 11) by photolithography and etching.
(15) In a test, it was observed that the thus obtained TFT 1 (see
(16)
(17) The test result described above indicates that the stability of the operation of the TFT is improved by implanting a predetermined amount of Si into the IGZO film of the active layer region. The above-described result is obtained because, instead of a carrier resulting from the oxygen deficiency, Si functions as a dopant to supply an electron serving as the carrier, and a deep level trap in the band gap of the IGZO that formed due to the oxygen deficiency is reduced.
(18) Next, another process example (Example 2) will be described. In this example, local laser anneal that used a XeF laser having a wavelength of 400 nm or less was performed before the anneal in the wet atmosphere in the above-described process example (Example 1). The other part of the process is identical to that of Example 1.
(19) A laser energy density in laser anneal was set to 150 mJ/cm.sup.2 per irradiation, and anneal was performed by superimposing one irradiation on another. The area of an annealed region was set to 60 m60 m, and the region was annealed such that the active layer region serving as the channel layer 13 of the TFT was included in the region. The pattern of the gate 11 was used for the alignment of the laser irradiation. Note that it is not possible to use the gate 11 for the alignment in the case where a top gate TFT is produced. However, by forming some alignment patterns flexibly, it becomes possible to perform local laser anneal on the active layer region with high accuracy.
(20)
(21) The hysteresis voltage (V) of the vertical axis of the graph represents a deviation between a voltage characteristic in the case where the gate voltage is swept from negative voltage to positive voltage and a voltage characteristic determined by sweeping the gate voltage from positive voltage to negative voltage and, specifically, the hysteresis voltage was evaluated as a difference between the threshold voltages determined from both of the voltage characteristics.
(22) As is clear from
(23) As has been described thus far, with the oxide semiconductor device and the method for manufacturing the same according to the embodiment of the present invention, it is possible to improve the stability when the stress is applied and improve durability in outdoor use or use for a long period of time. In addition, it is possible to obtain the device having high stability by additionally performing the laser anneal on the active layer region.
REFERENCE SIGNS LIST
(24) 1 TFT 10 Glass substrate 11 Gate 12 Gate insulation film 13 Channel layer 14 Source 15 Drain 16 Passivation film