Abstract
Numerous embodiments of input circuitry for an analog neural memory in a deep learning artificial neural network are disclosed.
Claims
1. An input block for providing an input to a vector-by-matrix multiplication array in a neural memory system, the vector-by-matrix multiplication array comprising non-volatile memory cells arranged in rows and columns, the input block comprising: a global digital-to-analog converter; a plurality of row registers, each row register corresponding to a row in the array; and a plurality of row sample-and-hold buffers, each row sample-and-hold buffer corresponding to a row in the array; wherein when a row is selected, the global digital-to-analog converter converts a digital value stored in a row register corresponding to the selected row into an analog value that is sampled and held by the row sample-and-hold buffer corresponding to the selected row and applied to a line coupled to the selected row.
2. The input block of claim 1, wherein the global digital-to-analog converter comprises a linear digital-to-analog converter.
3. The input block of claim 1, wherein the global digital-to-analog converter comprises a logarithmic digital-to-analog converter.
4. The input block of claim 1, wherein the global digital-to-analog converter comprises a digital-to-analog converter for odd rows and another digital-to-analog converter for even rows.
5. The input block of claim 1, wherein the global digital-to-analog converter comprises a row decoder that selects the selected row in response to a row address.
6. The input block of claim 1, wherein each row sample-and-hold buffer comprises a switch and a capacitor, wherein when the switch is closed it applies an analog input to the capacitor.
7. The input block of claim 6, wherein each row sample-and-hold buffer further comprises a buffer for outputting a value reflective of a value stored in the capacitor.
8. An input block for providing an input to a vector-by-matrix multiplication array in a neural memory system, the vector-by-matrix multiplication array comprising non-volatile memory cells arranged in rows and columns, the input block comprising: a digital-to-analog converter; a voltage-to-current converter to generate a current responsive to an output of the digital-to-analog converter; and a current to voltage logarithmic converter for generating a voltage that is a function of a logarithm of the current.
9. The input block of claim 8, wherein the digital-to-analog converter comprises a 2D thermometer code current digital-to-analog converter.
10. The input block of claim 8, wherein the digital-to-analog converter comprises a configurable successive approximation register.
11. The input block of claim 8, wherein the voltage-to-current converter comprises an operational amplifier, and NMOS transistor, and a resistor.
12. The input block of claim 8, wherein the current to voltage logarithmic converter comprises a switch and an NMOS transistor.
13. The input block of claim 8, wherein the current-to-voltage logarithmic converter comprises a plurality of switches and a memory cell.
14. The input block of claim 13, wherein the current-to-voltage logarithmic converter comprises an NMOS transistor.
15. An input block for generating an input to a vector-by-matrix multiplication array in a neural network memory system, the vector-by-matrix multiplication array comprising non-volatile memory cells arranged in rows and columns, the input block comprising: a current digital-to-analog converter to generate a current; and a current to voltage logarithmic converter to generate a voltage that is a function of a logarithm of the generated current.
16. The input block of claim 15, wherein the digital-to-analog converter comprises a 2D thermometer code current digital-to-analog converter.
17. The input block of claim 15, wherein the digital-to-analog converter comprises a successive approximation register.
18. The input block of claim 15, wherein the current to voltage logarithmic converter comprises a switch and an NMOS transistor.
19. The input block of claim 15, wherein the current-to-voltage logarithmic converter comprises a plurality of switches and a memory cell.
20. The input block of claim 19, wherein the current-to-voltage logarithmic converter comprises an NMOS transistor.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0097] FIG. 1 is a diagram that illustrates an artificial neural network.
[0098] FIG. 2 depicts a prior art split gate flash memory cell.
[0099] FIG. 3 depicts another prior art split gate flash memory cell.
[0100] FIG. 4 depicts another prior art split gate flash memory cell.
[0101] FIG. 5 depicts another prior art split gate flash memory cell.
[0102] FIG. 6 is a diagram illustrating the different levels of an exemplary artificial neural network utilizing one or more non-volatile memory arrays.
[0103] FIG. 7 is a block diagram illustrating a vector-by-matrix multiplication system.
[0104] FIG. 8 is a block diagram illustrates an exemplary artificial neural network utilizing one or more vector-by-matrix multiplication systems.
[0105] FIG. 9 depicts another embodiment of a vector-by-matrix multiplication system.
[0106] FIG. 10 depicts another embodiment of a vector-by-matrix multiplication system.
[0107] FIG. 11 depicts another embodiment of a vector-by-matrix multiplication system.
[0108] FIG. 12 depicts another embodiment of a vector-by-matrix multiplication system.
[0109] FIG. 13 depicts another embodiment of a vector-by-matrix multiplication system.
[0110] FIG. 14 depicts a prior art long short-term memory system.
[0111] FIG. 15 depicts an exemplary cell for use in a long short-term memory system.
[0112] FIG. 16 depicts an embodiment of the exemplary cell of FIG. 15.
[0113] FIG. 17 depicts another embodiment of the exemplary cell of FIG. 15.
[0114] FIG. 18 depicts a prior art gated recurrent unit system.
[0115] FIG. 19 depicts an exemplary cell for use in a gated recurrent unit system.
[0116] FIG. 20 depicts an embodiment of the exemplary cell of FIG. 19.
[0117] FIG. 21 depicts another embodiment of the exemplary cell of FIG. 19.
[0118] FIG. 22 depicts another embodiment of a vector-by-matrix multiplication system.
[0119] FIG. 23 depicts another embodiment of a vector-by-matrix multiplication system.
[0120] FIG. 24 depicts another embodiment of a vector-by-matrix multiplication system.
[0121] FIG. 25 depicts another embodiment of a vector-by-matrix multiplication system.
[0122] FIG. 26 depicts another embodiment of a vector-by-matrix multiplication system.
[0123] FIG. 27 depicts another embodiment of a vector-by-matrix multiplication system.
[0124] FIG. 28 depicts another embodiment of a vector-by-matrix multiplication system.
[0125] FIG. 29 depicts another embodiment of a vector-by-matrix multiplication system.
[0126] FIG. 30 depicts another embodiment of a vector-by-matrix multiplication system.
[0127] FIG. 31 depicts another embodiment of a vector-by-matrix multiplication system.
[0128] FIG. 32 depicts another embodiment of a vector-by-matrix multiplication system.
[0129] FIG. 33 depicts another embodiment of a vector-by-matrix multiplication system.
[0130] FIG. 34 depicts another embodiment of a vector-by-matrix multiplication system.
[0131] FIGS. 35A and 35B depicts embodiments of an input block.
[0132] FIG. 36 depicts another embodiment of an input block.
[0133] FIGS. 37A and 37B depict waveforms 3700 of sampling global row DAC with local row sample-and-hold actions.
[0134] FIG. 38 depicts a sample-and-hold buffer.
[0135] FIG. 39 depicts a sample-and-hold buffer.
[0136] FIGS. 40A and 40B depict input blocks.
[0137] FIGS. 41A and 41B depicts an input block.
[0138] FIG. 42 depicts an adjustable 2D thermometer code digital-to-analog converter.
[0139] FIG. 43 depicts a reference sub-circuit.
[0140] FIG. 44 depicts a configurable SAR (successive approximation register) analog-to-digital converter.
[0141] FIG. 45 depicts a voltage-to-current converter.
[0142] FIG. 46 depicts a logarithmic current-to-voltage converter.
[0143] FIG. 47 depicts a logarithmic current-to-voltage converter.
[0144] FIG. 48 depicts a logarithmic current-to-voltage converter.
DETAILED DESCRIPTION OF THE INVENTION
[0145] The artificial neural networks of the present invention utilize a combination of CMOS technology and non-volatile memory arrays.
[0146] VMM System Overview
[0147] FIG. 34 depicts a block diagram of VMM system 3400. VMM system 3400 comprises VMM array 3401, row decoder 3402, high voltage decoder 3403, column decoder 3404, bit line drivers 3405, input circuit 3406, output circuit 3407, control logic 3408, and bias generator 3409. VMM system 3400 further comprises high voltage generation block 3410, which comprises charge pump 3411, charge pump regulator 3412, and high voltage analog precision level generator 3413. VMM system 3400 further comprises (program/erase, or weight tuning) algorithm controller 3414, analog circuitry 3415, control engine 3416 (that may include special functions such as arithmetic functions, activation functions, embedded microcontroller logic, without limitation), and test control logic 3417. The systems and methods described below can be implemented in VMM system 3400.
[0148] The input circuit 3406 may include circuits such as a DAC (digital to analog converter), DPC (digital to pulses converter, digital to time modulated pulse converter), AAC (analog to analog converter, such as a current to voltage converter, logarithmic converter), PAC (pulse to analog level converter), or any other type of converters. The input circuit 3406 may implement normalization, linear or non-linear up/down scaling functions, or arithmetic functions. The input circuit 3406 may implement a temperature compensation function for input levels. The input circuit 3406 may implement an activation function such as ReLU or sigmoid. The output circuit 3407 may include circuits such as a ADC (analog to digital converter, to convert neuron analog output to digital bits), AAC (analog to analog converter, such as a current to voltage converter, logarithmic converter), APC (analog to pulse(s) converter, analog to time modulated pulse converter), or any other type of converters. The output circuit 3407 may implement an activation function such as rectified linear activation function (ReLU) or sigmoid. The output circuit 3407 may implement statistic normalization, regularization, up/down scaling/gain functions, statistical rounding, or arithmetic functions (e.g., add, subtract, divide, multiply, shift, log) for neuron outputs. The output circuit 3407 may implement a temperature compensation function for neuron outputs or array outputs (such as bitline output) so as to keep power consumption of the array approximately constant or to improve precision of the array (neuron) outputs such as by keeping the IV slope approximately the same.
[0149] FIG. 35A depicts input block 3500 to be used to provide inputs to VMM array 3506. Input block 3500 comprises global digital-to-analog converter (DAC) 3501; row registers 3502-0 through 3502-n, each corresponding to a one of the rows numbered 0 through n in the array; digital comparator blocks 3503-0 through 3503-n; row sample-and-hold buffers 3504-0 through 3504-n, each corresponding to one of the rows numbered 0 through n; and output signals 3505-0 through 3505-n, each corresponding to one of the rows numbered 0 through n, and denoted CGIN0, CGIN1 . . . , CGINn−1 and CGINn, respectively. Signal GDACsup is the global DAC signal supplied by the global DAC 3501. The signals CGIN0-n couples to the row inputs of the array 3506.
[0150] Digital comparator blocks 3503 compare the value stored in the associated row register 3502 against CLKCOUNTx, which is a result of counting a clock signal during an interval; if it matches, then the corresponding row S/H 3504 is enabled to sample the value from the global DAC 3501 into the respective row S/H buffer. This technique will be referred to as global row DAC sampling. Each row in VMM array 3506 has a corresponding row register 3502, digital comparator block 3503, and row S/H 3504.
[0151] During operation, row registers 3502-0 through 3502-n are loaded with digital input bits DINx (where x is the number of bits, such as 8 or 16 bits) for that particular row and receives a clock signal, CLK. The CLK signal is used to load in the data from the DINx into the row registers 3502-x. Global digital-to-analog converter 3501 is shared by all rows, and in a time-multiplexed fashion, performs a digital-to-analog conversion on the digital bits DINx stored in a particular row register 3502. The conversion is done by comparing the digital input bits of a particular row versus CLKCOUNTx, which is digital counting value, by each of the digital comparator blocks 3503). When the digital counting values of the global DAC 3501 match the contents of the respective row register 3502, the corresponding row sample-and-hold buffer 3503 for that row samples the analog output from global digital-to-analog converter 3501 and holds that value, which is then applied as output signal 3505 for that particular row. Output signal 3504 can be applied, for example, to a control gate line or a word line during a programming operation in that particular row, in the manner described above with respect to other Figures.
[0152] In another embodiment, the row sample-and-hold buffer 3504 can be shared between multiple rows by time multiplexing the row sample-and-hold buffers.
[0153] FIG. 35B depicts input block 3550 to be used to provide inputs to VMM array 3556. Input block 3550 comprises global digital-to-analog converter (DAC) 3551; row registers 3552-0 through 3552-n, each corresponding to a respective one of the rows numbered 0 through n in the VMM array; digital multiplexer (mux) blocks 3553-0 through 3553-n, each corresponding to a respective one of the rows numbered 0 through n; row sample-and-hold (S/H) buffers 3553-0 through 3553-n, each corresponding to a respective one of the rows numbered 0 through n; and output signals 3554-0 through 3554-n, denoted CGIN0, CGIN1 . . . , CGINn−1 and CGINn, respectively, each corresponding to a respective one of the rows numbered 0 through n. The digital mux blocks 3553 are used to multiplex out the data of the row registers 3552 into the bus GDAC_DINx, which is applied as an input to the global DAC 3551. The corresponding row S/H buffer samples the value from the global DAC into the local S/H. Each row has its own row register 3552, S/H buffer 3553m and output signal 3554.
[0154] During operation, row registers 3552-0 through 3552-n are loaded with digital input bits DINx (where x is the number of bits, such as 8 or 16 bits) for that particular row and receives a clock signal, CLK. The CLK signal is used to load in the data from the DINx into the row registers 3552-x. Global digital-to-analog converter 3551 is shared by all rows, and in a time-multiplexed fashion, performs a digital-to-analog conversion on the digital bits DINx stored in a particular row register 3552. The conversion is done by multiplexing the data of the row registers into the data input (bus GDAC_DINx) of the global DAC 3551. The multiplexing of the row register data into the data input bus GDAC_DINx is enabled by the signal EN-x 3557-x for each row. The corresponding row sample-and-hold buffer 3554 samples the analog output from global digital-to-analog converter 3551 and holds that value, which is then applied as output signal 3555 for that particular row. Output signal 3555 can be applied, for example, to a control gate line or a word line during a programming operation in that particular row, in the manner described above with respect to other Figures. In another embodiment, the row sample-and-hold buffer 35554 can be shared between multiple rows by time multiplexing the row sample-and-hold buffers.
[0155] FIG. 36 depicts input block 3600 to be used to provide inputs to VMM array 3606. Input block 3600 is similar to input block 3500 but also provides a row decoder function to select one or more rows for an operation. Input block 3600 comprises global digital-to-analog converter and row decoder 3601; row registers 3602-0 through 3602-n, each corresponding to a respective one of the rows numbered 0 through n in the VMM array; digital comparator blocks 3603 through 3603-n each corresponding to a respective one of the rows numbered 0 through n in the VMM array; row sample-and-hold buffers 3604-0 through 3604-n; and output signals 3605-0 through 3605-n, denoted CGIN0, CGIN1 . . . , CGINn−1 and CGINn, respectively, each corresponding to a respective one of the rows numbered 0 through n. The digital comparator blocks 3603 compare the value stored in the respective row register 3602 against CLKCOUNTx, which is a counting value. When the digital counting values of the global DAC 3501 match the contents of the respective row register 3602. the respective row S/H buffer 3604 samples the value from the global DAC 3601 into the respective S/H buffer 3604. Each row has its own row register 3602, digital comparator block 3603, and row S/H buffer 3604.
[0156] During operation, row registers 3602-0 through 3602-n are loaded with digital input bits DINx (where x is the number of bits, such as 8 or 16 bits) for the associated row and receives a clock signal, CLK. The CLK signal is used to load in the data from the DINx into the row registers 3602-x. Global digital-to-analog converter a 3601 (which consists of a plurality of global digital-to-analog converters, such as 3601-0 and 3601-1) is shared by all rows. In one embodiment, global DAC 3601-0 operates on even rows and global DAC and row decoder 3601-1 operates on odd rows. Global digital-to-analog converter 3601 receives a row addresses through the row data-in bus GDAC_DINx and selects the corresponding (rows. It then performs a digital-to-analog conversion on the digital bits DINx stored in the relevant row register(s) 3602 (through the GDAC_DINx bus). The corresponding row(s) sample-and-hold buffer 3604 for that row(s) samples the analog output from global digital-to-analog converter 3601 and holds that value, which is then applied as output signal 3605 for that particular row. Output signal 3605 can be applied, for example, to a control gate line or a word line during a programming operation in that particular row or rows, in the manner described above with respect to other Figures.
[0157] FIG. 37A depicts waveforms 3700 that illustrate exemplary linear voltage levels for exemplary sample-and-hold actions by row sample-and-hold buffer 3504 in FIG. 35A, row sample-and-hold buffer 3554 in FIG. 35B or row sample-and-hold buffer 3604 in FIG. 36. This is suitable for memory cells operating in linear region. The signal GDACsup 3701 is the supplied voltage from the global linear DAC such as from the circuit blocks 3501 in FIG. 35A, 3551 in FIG. 35B, 3601x in FIG. 36. It shows the linear steps to illustrate this is a linear DAC.
[0158] FIG. 37B depicts waveforms 3720 that illustrate exemplary logarithmic voltage levels for exemplary sample-and-hold actions by row sample-and-hold buffer 3504 in FIG. 35A, row sample-and-hold buffer 3554 in FIG. 35B or row sample-and-hold buffer 3604 in FIG. 36. This is suitable for memory cells operating in sub threshold region. Alternatively, the global DAC voltage waveform can be done for memory cells operating in saturation region. The signal GDACsup 3721 is the supplied voltage from the global (sub threshold, linear, saturation) DAC such as from the circuit blocks 3501 in FIG. 35A, 3551 in FIG. 35B, 3601x in FIG. 36. It shows the log steps to illustrate this is a log DAC.
[0159] FIG. 38 depicts sample-and-hold buffer 3800, which can be used for row sample-and-hold buffer 3504 in FIG. 35A, row sample-and-hold buffer 3554 in FIG. 35B, or row sample-and-hold buffer 3604 in FIG. 36. Sample-and-hold buffer 3800 comprises switch 3801, capacitor 3802, and buffer 3803, the buffer 3803 can be done as a unity buffer using an operation amplifier. During operation, switch 3801 is closed (enabled, such as by the true result of the comparison of the digital comparator and the digital counting values), which allows an analog value (global DAC value) to be stored (held) in capacitor 3802. A value reflective of that stored value can then be output from buffer 3803 which drives a respective row input of the array. Capacitor 3802 can be an actual capacitor, or it can be an intrinsic capacitance found in a wire, for example.
[0160] FIG. 39 depicts sample-and-hold buffer 3900, which can be used for row sample-and-hold buffer 3504 in FIG. 35A, row sample-and-hold buffer 3554 in FIG. 35B or row sample-and-hold buffer 3604 in FIG. 36. Sample-and-hold buffer 3900 comprises switch 3901 and capacitor 3902. During operation, switch 3901 is closed (enabled, such as by the true result of the comparison of the digital comparator and the digital counting value), which allows an analog value to be stored (held) in capacitor 3902. A value reflective of that value can then be output from capacitor 3902. Capacitor 3902 can be an actual capacitor, or it can be an intrinsic capacitance found in a wire, for example.
[0161] FIG. 40A depicts input block 4000. Input block 4000 comprises digital-to-analog converter 4001, voltage-to-current converter 4002, and current to voltage logarithmic converter 4003. Input block 4000 can be added to any of the preceding input blocks when it is desired to have an input voltage that varies according to a logarithmic function, which is useful, for example, if the memory cells in a WM array are operating in the sub-threshold range. Digital-to-analog converter receives a digital input, DINx, and generates an analog voltage, Vout. Voltage-to-current converter 4002 linearly converts analog voltage Vout into a current Iout. Current to voltage logarithmic converter 4003 converts the current Iout into a voltage Vlog according to a logarithmic function: For example, Vlog=A*log(Iout), where A is a constant. The input block 4000 can be used as a global DAC as in FIGS. 35A, 35B and 36. It can generate waveforms 3720 shown in FIG. 37B. For the global DAC in FIG. 35A, CLK is used to generate the DAC output voltages in a stepwise fashion from for example 0 to 256 steps for 8 bit DAC. For global DAC in FIGS. 35B and 36, DINx is used to generate the DAC output voltage.
[0162] FIG. 40B depicts input block 4020. Input block 4020 comprises a digital-to-analog converter, which can be used as the global DAC. This can be used for example for memory cells operating in linear region. The input block 4020 can be used as a global DAC as in FIGS. 35 and 36. It can generate waveforms 3700 shown in FIG. 37A,
[0163] FIG. 41A depicts input block 4100. Input block 4100 comprises current digital-to-analog converter 4101 and current to voltage logarithmic converter 4102. Input block 4100 can be added to any of the preceding input blocks when it is desired to have an input voltage that varies according to a logarithmic function, which is useful, for example, if the memory cells in a VMM array are operating in the sub-threshold range. Current digital-to-analog converter 4101 receives a digital input, DINx, as in previous examples and generates an analog current, Iout. Current to voltage logarithmic converter 4102 converts the current Iout into a voltage Vlog, for example using a memory cell or a MOS transistor, according to a logarithmic function: For example, Vlog=A*log(Iout)+Vlogoffset, where A is a constant and Vlogoffset is another constant, for example, to take care of the turn on or off voltage of the memory cell or some other offset voltage from array or decoding circuitry or the input/output circuit itself
[0164] FIG. 41B depicts input block 4120. Input block 4120 comprises current digital-to-analog converter 4121 and current to voltage linear converter 4122. Input block 4120 can be added to any of the preceding input blocks when it is desired to have an input voltage that varies according to a linear function, which is useful, for example, if the memory cells in a VMM array are operating in the linear range. Current digital-to-analog converter 4121 receives a digital input, DINx, as in previous examples and generates an analog current, Iout. Current to voltage linear converter 4122 converts the current Iout into a voltage Vlin, for example using a memory cell or a MOS transistor, according to a linear function: For example, Vlin=A*Iout+Vlinoffet, where A is a constant and Vlogoffset is another constant, for example to take care of the turn on or off voltage of the memory cell or some other offset voltage from array or decoding circuitry or the input/output circuit itself.
[0165] FIG. 42 depicts adjustable 2D thermometer code current digital-to-analog converter 4200. Adjustable 2D thermometer code current digital-to-analog converter 4200 comprises control logic 4202 and 2D array 4205 comprising an array of i rows and j columns of devices 4206, where a particular device 4206 is noted by the label 4206-(row)(column). The particular devices 4206 may be current mirrors. As shown, there are 16 current mirrors (devices 4206) in the 2D array 4205. The adjustable 2D thermometer code current digital-to-analog converter 4200 converts a 4 digital input code into an output current 4201, Iout, with value from 1 to 16 times Ibiasunit which is provided from the bias source 4204.
[0166] For example, bias source 4204 can provide a current Ibiasunit of 1 nA, which is mirrored into devices 4206. Here, the first row consists of devices 4206-11 to 4206-1j and is enabled sequentially from left to right, one device 4206 at a time. Then the next row is enabled in a sequential manner from left to right to add to the first row, meaning 5 then 6 then 7 then 8 devices 4206 are enabled. Hence, by sequentially enabling devices 4206, any transistor mismatch associated with conventional binary decoding can be reduced. The sum of the enabled devices 4206 is then output as an output current 4201. The shown 4×4 2D thermometer code current digital-to-analog converter 4200 could be any other dimension such as 32×32 or 8×32.
[0167] FIG. 43 depicts reference sub-circuit 4300, which is can be used for device 4206 in FIG. 42. Reference sub-circuit 4300 comprises NMOS transistors 4301 and 4302, configured as shown. The transistor 4302 is a current mirror bias transistor and transistor 4301 is an enabling transistor (to enable the bias transistor 4302 to be connected to output node OUTPUT), master bias current that is used to mirror to the transistor 4302 is not shown.
[0168] FIG. 44 depicts a SAR (successive approximation register) digital-to-analog converter 4400. This circuit is a digital-to-analog converter that relies upon charge redistribution using binary capacitors. It includes a binary CDAC (DAC basing on capacitors) 4401, op-amp/comparator 4402, and SAR logic 4403. GndV is a low voltage reference level, for example, ground level. This is, for example, used in FIGS. 40A and 40B.
[0169] FIG. 45 depicts voltage-to-current converter 4500, which comprises op amp 4501, NMOS transistor 4501, and resistor 4503, configured as shown. Voltage-to-current converter 4500 receives input voltage VIN and generates output current IOUT. This, for example, can be used in combination with DAC circuit 4400 to convert voltage into current. This current can be used to convert to a voltage using a log I to V converter such as in FIG. 46/47/48.
[0170] FIG. 46 depicts logarithmic current-to-voltage converter 4600. Logarithmic current-to-voltage converter 4600 comprises switch 4601 and NMOS transistor 4602, configured as shown. The NMOS 4602 operates in the sub-threshold region. Logarithmic current-to-voltage converter 4600 receives input I-in and generates output Vlog.
[0171] FIG. 47 depicts logarithmic current-to-voltage converter 4700. Logarithmic current-to-voltage converter 4700 comprises switches 4701 and 4702 and memory cell 4703, configured as shown. The memory cell 4703 operates in the sub-threshold region. Logarithmic current-to-voltage converter 4600 receives input I-in and generates output Vlog.
[0172] FIG. 48 depicts logarithmic current-to-voltage converter 4800. Logarithmic current-to-voltage converter 4800 comprises switches 4801 and 4802, NMOS transistor 4803, and memory cell 4804, configured as shown. The memory cell 4804 operates in the sub-threshold region. The transistor 4803 imposes a constant bias on the drain of memory cell 4804. Logarithmic current-to-voltage converter 4600 receives input I-in and generates output Vlog. In FIGS. 47 and 48, the log I to V conversion is done to replicate the log I vs V slope of the memory cell current. The cell output current is then=K*I-in, the input current is from the output of the log DAC, which basically represent the value of the input activation (row value). K is determined by the floating charge in the memory cell, which basically represents the weight in neural network.
[0173] It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed therebetween) and “indirectly on” (intermediate materials, elements or space disposed therebetween). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed therebetween) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.
