SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method therefor. In the semiconductor structure, a semiconductor substrate, a heterojunction and an in-situ insulation layer are disposed from bottom to top, a trench is provided in the in-situ insulation layer, and a transition layer is located on at least an in-situ insulation layer, the p-type semiconductor layer is located in the trench and on the gate region of the transition layer, and the heavily doped n-type layer is located on at least one of the p-type semiconductor layer in the gate region, the source region of the heterojunction, or the drain region of the heterojunction.

Claims

1. A semiconductor structure, comprising: a semiconductor substrate, a heterojunction, and an in-situ insulation layer disposed from bottom to top; a trench penetrating through the in-situ insulation layer; a transition layer located on at least the in-situ insulation layer; a p-type semiconductor layer located in the trench and on a gate region of the transition layer; a heavily doped n-type layer located on at least one of the p-type semiconductor layer in the gate region, a source region of the heterojunction, or a drain region of the heterojunction.

2. The semiconductor structure according to claim 1, wherein, a material of the heavily doped n-type layer comprises a Group III nitride material.

3. The semiconductor structure according to claim 1, wherein, the transition layer is further located in the trench.

4. The semiconductor structure according to claim 1, wherein, the p-type semiconductor layer is further provided on a non-gate region of transition layer.

5. The semiconductor structure according to claim 1, wherein, the heterojunction comprises a channel layer and a barrier layer disposed from bottom to top.

6. The semiconductor structure according to claim 5, wherein the heavily doped n-type layer contacts the channel layer or the barrier layer.

7. The semiconductor structure according to claim 1, wherein the heterojunction comprises a Group III nitride material.

8. The semiconductor structure according to claim 1, wherein, at least one of: the in-situ insulation layer is a single-layer structure, wherein a material of the single-layer structure comprises: one of or a mixture of SiN and AlN; or the in-situ insulation layer is a multi-layer structure, wherein the multi-layer structure comprises a SiN layer and an AlN layer disposed from bottom to top, or comprises an AlN layer and a SiN layer disposed from bottom to top, or comprises a SiN layer, an AlN layer and a SiN layer disposed from bottom to top; or the transition layer is a single-layer structure, and a material of the single-layer structure comprises: one of or a mixture of two or more of AlN, SiAlN, and AlGaN; or the transition layer is a multi-layer layer, wherein the multi-layer structure comprises: at least two layers of an AlN layer, a SiAlN layer, or an AlGaN layer.

9. The semiconductor structure according to claim 1, further comprising: a gate electrode located on the heavily doped n-type layer in the gate region, a source electrode located on the heavily doped n-type layer in the source region, and a drain electrode on the heavily doped n-type layer in the drain region.

10. A method of manufacturing a semiconductor structure, comprising: providing a semiconductor substrate, wherein a heterojunction is formed on the semiconductor substrate; forming an in-situ insulation layer on the heterojunction; forming a trench penetrating through the in-situ insulation layer; forming a transition layer in the trench and on the in-situ insulation layer , and a p-type semiconductor layer on the transition layer; forming a heavily doped n-type layer on at least one of the p-type semiconductor layer in a gate region, a source region of the heterojunction, or a drain region of the heterojunction.

11. (canceled)

12. The method of manufacturing semiconductor structure according to claim 10, further comprising: patterning the p-type semiconductor layer, and retaining the p-type semiconductor layer in the gate region.

13. The method of manufacturing semiconductor structure according to claim 10, wherein, the heterojunction comprises a channel layer and a barrier layer disposed from bottom to top.

14. The method of manufacturing semiconductor structure according to claim 13, wherein the heavily doped n-type layer contacts the channel layer or the barrier layer.

15. (canceled)

16. The method of manufacturing semiconductor structure according to claim 10, wherein, at least one of: the in-situ insulation layer is a single-layer structure, wherein a material of the single-layer structure comprises: one of or a mixture of SiN and A1N; or the in-situ insulation layer is a multi-layer structure, wherein the multi-layer structure comprises a SiN layer and an AlN layer disposed from bottom to top, or comprises an AlN layer and a SiN layer disposed from bottom to top, or comprises a SiN layer, an AlN layer and a SiN layer; or the transition layer is a single-layer structure, and a material of the single-layer structure comprises: one of or a mixture of two or more of AlN, SiAlN, and AlGaN; or the transition layer is a multi-layer layer, wherein the multi-layer structure comprises: at least two layers of an AlN layer, a SiAlN layer, or an AlGaN layer.

17. The method for manufacturing semiconductor structure according to claim 10, further comprising: forming a gate electrode on the heavily doped n-type layer in the gate region, forming a source electrode on heavily doped n-type layer in the source region, and forming a drain electrode on heavily doped n-type layer in the drain region.

18. A method of manufacturing a semiconductor structure, comprising: providing a semiconductor substrate, wherein a heterojunction is formed on the semiconductor substrate; forming an in-situ insulation layer on the heterojunction and a transition layer on the in-situ insulation layer; forming a trench penetrating through the in-situ insulation layer and the transition layer; forming a p-type semiconductor layer in the trench and on the transition layer; forming a heavily doped n-type layer on at least one of the p-type semiconductor layer in a gate region, a source region of the heterojunction, or a drain region of the heterojunction.

19. (canceled)

20. The method of manufacturing semiconductor structure according to claim 18, further comprising: patterning the p-type semiconductor layer, and retaining the p-type semiconductor layer in the gate region.

21. The method of manufacturing semiconductor structure according to claim 18, wherein, the heterojunction comprises a channel layer and a barrier layer disposed from bottom to top.

22. The method of manufacturing semiconductor structure according to claim 21, wherein the heavily doped n-type layer contacts the channel layer or the barrier layer.

23. (canceled)

24. The method of manufacturing semiconductor structure according to claim 18, wherein, at least one of: the in-situ insulation layer is a single-layer structure, wherein a material of the single-layer structure comprises: one of or a mixture of SiN and A1N; or the in-situ insulation layer is a multi-layer structure, wherein the multi-layer structure comprises a SiN layer and an AlN layer disposed from bottom to top, or comprises an AlN layer and a SiN layer disposed from bottom to top, or comprises a SiN layer, an AlN layer and a SiN layer disposed from bottom to top; or the transition layer is a single-layer structure, and the material of the single-layer structure comprises: one of or a mixture of two or more of AlN, SiAlN, and AlGaN; or the transition layer is a multi-layer layer, wherein the multi-layer structure comprises: at least two layers of an AlN layer, a SiAlN layer, and or AlGaN layer.

25. (canceled)

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0059] FIG. 1 is a structural diagram of a semiconductor structure according to a first embodiment of the present disclosure;

[0060] FIG. 2 is a flowchart of a method of manufacturing the semiconductor structure provided in the first embodiment of the present disclosure;

[0061] FIGS. 3 to 5 are schematic diagrams illustrating intermediate structures corresponding to the process of FIG. 2;

[0062] FIG. 6 is a structural diagram of a semiconductor structure according to a second embodiment of the present disclosure;

[0063] FIG. 7 is a structural diagram of a semiconductor structure according to a third embodiment of the present disclosure;

[0064] FIG. 8 is a flowchart of a method of manufacturing the semiconductor structure provided in the third embodiment of the present disclosure;

[0065] FIG. 9 is a structural diagram of a semiconductor structure according to a fourth embodiment of the present disclosure;

[0066] FIG. 10 is a structural diagram of a semiconductor structure according to a fifth embodiment of the present disclosure;

[0067] FIG. 11 is a flowchart of a method of manufacturing the semiconductor structure provided in the fifth embodiment of the present disclosure;

[0068] FIG. 12 is a schematic diagram illustrating an intermediate structure corresponding to the process of FIG. 11;

[0069] FIG. 13 is a structural diagram of a semiconductor structure according to a sixth embodiment of the present disclosure;

[0070] FIG. 14 is a structural diagram of a semiconductor structure according to a seventh embodiment of the present disclosure;

[0071] FIG. 15 is a structural diagram of a semiconductor structure according to an eighth embodiment of the present disclosure;

[0072] To facilitate the understanding of the present disclosure, all reference signs present in the present disclosure are listed below: [0073] semiconductor structures 1, 2, 3, 4, 5, 6, 7, 8 [0074] semiconductor substrate 10 [0075] in-situ insulation layer 12 [0076] transition layer 14 [0077] heavily doped n-type layer 16 [0078] source electrode17b [0079] channel layer 11a [0080] heterojunction 11 [0081] trench 13 [0082] p-type semiconductor layer 15 [0083] gate electrode 17a [0084] drain electrode 17c [0085] barrier layer 11b

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0086] In order to make the above-mentioned objects, features and advantages of the present disclosure more obvious and understandable, embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0087] FIG. 1 is a structural diagram of a semiconductor structure according to a first embodiment of the present disclosure.

[0088] Referring to FIG. 1, the semiconductor structure 1 includes: [0089] a semiconductor substrate 10, a heterojunction 11, and an in-situ insulation layer 12 disposed from bottom to top; [0090] a trench 13 (referring to FIG. 4) penetrating through in-situ insulation layer 12; [0091] a transition layer 14 located in the trench 13 and on the in-situ insulation layer 12; [0092] a p-type semiconductor layer 15 located on the transition layer 14; [0093] a heavily doped n-type layer 16 located on the p-type semiconductor layer 15 in the gate region, and on a source region and a drain region of the heterojunction 11; [0094] a gate electrode 17a located on the heavily doped n-type layer 16 in the gate region, a source electrode 17b located on the heavily doped n-type layer 16 in the source region, and a drain electrode 17c located on the heavily doped n-type layer 16 in the drain region.

[0095] The material of the semiconductor substrate 10 may include sapphire, silicon carbide, silicon, GaN or diamond.

[0096] The heterojunction 11 may include a channel layer 11a and a barrier layer 11b disposed from bottom to top. Two-dimensional electron gas may be formed at the interface between the channel layer 11a and the barrier layer 11b. In an example, the channel layer 11a is an intrinsic GaN layer, and the barrier layer 11b is an n-type AlGaN layer. In other examples, the combination of the channel layer 11a and the barrier layer 11b may also be GaN/AlN, GaN/InN, GaN/InAlGaN, GaAs/AlGaAs, GaN/InAlN or InN/InAlN. In addition to that the heterojunction 11 includes one channel layer 11a and one barrier layer 11b as shown in FIG. 1, the heterojunction 11 may include multiple channel layers 11a and multiple barrier layers 11b, which are distributed alternately; or the heterojunction 11 includes one channel layer 11a and two or more barrier layers 11b to form a multi-barrier structure.

[0097] A nucleation layer and a buffer layer (not shown in figures) may also be provided between the heterojunction 11 and the semiconductor substrate 10. A material of the nucleation layer may include, for example, A1N, AlGaN, or the like, and a material of the buffer layer may include at least one of A1N, GaN, AlGaN or AlInGaN. The nucleation layer may alleviate the problems of lattice mismatch and thermal mismatch between epitaxially-growing semiconductor layers for example, the channel layer 11a in the heterojunction 11 and the semiconductor substrate 10; and the buffer layer may decrease a dislocation density and a defect density of the epitaxially-growing semi-conductor layer so as to improve crystal quality.

[0098] The in-situ insulation layer 12 is an insulation layer formed by an in-situ growth process. One of the functions of the in-situ insulation layer 12 is to electrically insulate the gate electrode 17a outside the trench 13 and the barrier layer 11b. In the HEMT structure, the in-situ insulation layer 12 can also suppress the current collapse effect.

[0099] In an example, the in-situ insulation layer 12 is a single-layer structure, and the material of the single-layer structure includes: one of or a mixture of SiN and A1N. In another example, the in-situ insulation layer 12 is a multi-layer structure, and the multi-layer structure may include, from bottom to top, a SiN layer and an A1N layer; or include, from bottom to top, an A1N layer and a SiN layer; or include, from bottom to top, a SiN layer, an A1N layer and a SiN layer.

[0100] The transition layer 14 may be formed using an in-situ growth process. In an example, the in-situ insulation layer 14 is a single-layer structure, and the material of the single-layer structure includes: one of or a mixture of two or more of A1N, SiA1N, and AlGaN. In another example, the transition layer 14 is a multi-layer structure, and the multi-layer structure may include at least two layers of an AlN layer, a SiAlN layer, and an AlGaN layer. The transition layer 14 made of the above material can solve the problem that the p-type Group III nitride material cannot grow on the in-situ insulation layer 12, so that the p-type semiconductor layer 15 can be formed outside the trench 13.

[0101] The p-type semiconductor layer 15 can be made of a Group III nitride material, such as at least one of GaN, AlGaN, or AlInGaN, where the p-type doped ions can be magnesium ions to deplete the two-dimensional electron gas under the gate region, so as to form enhanced devices.

[0102] In the embodiment shown in FIG. 1, there is a concave region of the p-type semiconductor layer 15 corresponding to the trench 13, and a portion of the gate electrode 17a is located in the concave region. In some embodiments, the upper surface of the p-type semiconductor layer 15 and the lower surface of the gate electrode 17a may also be flat.

[0103] In FIG. 1, the source electrode 17b and the drain electrode 17c are in contact with the barrier layer 11b, and an ohmic contact may be formed both between the source electrode 17b and the barrier layer 11b and between the drain electrode 17c and the barrier layer 11b by heavily doped n-type layer 16. An ohmic contact is also formed between the gate electrode 17a and the p-type semiconductor layer 15 by the heavily doped n-type layer 16. The material of the source electrode 17b, the drain electrode 17c, and the gate electrode 17a can be metal, such as Ti/Al/Ni/Au, Ni/Au and other existing conductive materials. The heavily doped n-type layer 16 can make an ohmic contact layer be directly formed between the source electrode 17b and the source region of the heterojunction 11, between the drain electrode 17c and the drain region of the heterojunction 11, and between the gate electrode 17a and the p-type semiconductor layer 15 in the gate region, without high temperature annealing.

[0104] In some embodiments, an n-type ion heavily doped layer 16 may also be provided on at least one of the p-type semiconductor layer 15 in the gate region, the source region of heterojunction 11, or the drain region of the heterojunction 11. By high temperature annealing, an ohmic contact layer may be formed between the gate electrode 17a and the p-type semiconductor layer 15 in the gate region without the heavily doped n-type layer 16, between the source electrode 17b and the source region of the heterojunction 11 without the heavily doped n-type layer 16, and between the drain electrode 17c and the drain region of the heterojunction 11 without the heavily doped n-type layer 16.

[0105] In the heavily doped n-type layer 16, the n-type ions may include at least one of kinds of Si ions, Ge ions, Sn ions, Se ions or Te ions. For different n-type ions, the doping concentration can be greater than 1E19/cm.sup.3. The heavily doped n-type layer 16 may include a Group III nitride material, such as at least one of GaN, AlGaN, or AlInGaN.

[0106] In the semiconductor structure 1, the in-situ insulation layer 12 and the transition layer 14 can reduce the gate leakage current leaked from the channel to the gate electrode 17a, so the thickness of the barrier layer 11b in the heterojunction 11 can be smaller, which can decrease threshold voltage; in addition, because the in-situ insulation layer 12 is provided, the surface resistance can be reduced, the concentration of the two-dimensional electron gas is increased, and therefore the control ability of the gate to the channel is improved, and the working current is increased.

[0107] In order to verify the technical effect of the present disclosure, taking the thickness of the barrier layer 11b as 5 nm as an example. By comparing a semiconductor structure with 5 nm Al.sub.0.25GaN barrier layer/GaN channel layer and a semiconductor structure with 5 nm in-situ SiN layer/5 nm Al.sub.0.25GaN barrier layer/GaN channel layer, it is found that the sheet resistance (surface resistance) between the source electrode 17b and the drain electrode 17c can be reduced from 2300 Ω/❏ to 325 Ω/❏, and the two-dimensional electron gas concentration in the heterojunction 11 can be increased from 2.4E12/cm.sup.2 to 1.03E13/cm.sup.2.

[0108] In addition, in the existing HEMT structure with the AlGaN barrier layer/GaN channel layer, the thickness of the barrier layer 11b is from 15 nm to 25 nm to ensure the generation of a sufficient concentration of two-dimensional electron gas. In the present disclosure, when the thickness of the barrier layer 11b ranges is from 1 nm to 15 nm, a sufficient concentration of two-dimensional electron gas can be generated. In an example, the thickness of the barrier layer 11b can be controlled to be less than 10 nm.

[0109] FIG. 2 is a flowchart of a method of manufacturing semiconductor structure provided in the first embodiment of the present disclosure; and FIGS. 3 to 5 are schematic diagrams illustrating intermediate structures corresponding to the process of FIG. 2.

[0110] First, referring to step S1 in FIG. 2 and FIG. 3, a semiconductor substrate 10 is provided, and a heterojunction 11 is formed on the semiconductor substrate 10.

[0111] The material of the semiconductor substrate 10 may include sapphire, silicon carbide, silicon, GaN or diamond.

[0112] The heterojunction 11 may include a channel layer 11a and a barrier layer 11b disposed from bottom to top. In an example, the channel layer 11a is an intrinsic GaN layer, and the barrier layer 11b is an n-type AlGaN layer. In other examples, the combination of the channel layer 11a and the barrier layer 11b may also be GaN/A1N, GaN/InN, GaN/InAlGaN, GaAs/A1GaAs, GaN/InAlN or InN/InAlN. Forming process for the channel layer 11a and the barrier layer 11b may include: Atomic Layer Deposition (ALD), or Chemical Vapor Deposition (CVD), or molecular beam epitaxial (MBE), or Plasma Enhanced Chemical Vapor Deposition (PECVD), or Low Pressure Chemical Vapor Deposition (LPCVD), or Metal-Organic Chemical Vapor Deposition (MOCVD), or a combination thereof.

[0113] In addition to that the heterojunction 11 shown in FIG. 1 includes one channel layer 11a and one barrier layer 11b, the heterojunction 11 may also include multiple channel layers 11a and multiple barrier layers 11b, which are distributed alternately; or the heterojunction 11 includes one channel layer 11a and two or more barrier layers 11b to form a multi-barrier structure.

[0114] Before the heterojunction 11 is formed on the semiconductor substrate 10, a nucleation layer and a buffer layer (not shown in figures) may also be provided on the semiconductor substrate 10 in sequence. A material of the nucleation layer may include, for example, AlN, AlGaN, or the like, and a material of the buffer layer may include at least one of A1N, GaN, AlGaN or AlInGaN. The formation method of the buffer layer may be the same as the formation method of the heterojunction 11. The nucleation layer may alleviate the problems of lattice mismatch and thermal mismatch between epitaxially-growing semiconductor layers for example, the channel layer 11a in the heterojunction 11 and the semiconductor substrate 10; and the buffer layer may decrease a dislocation density and a defect density of the epitaxially-growing semi-conductor layer so as to improve crystal quality.

[0115] The sheet resistance (surface resistance) of the structure shown in FIG. 3 is tested, and the size is 2300 Ω/❏.

[0116] Next, referring to step S2 in FIG. 2 and FIG. 4, an in-situ insulation layer 12 is formed on the heterojunction 11.

[0117] The in-situ insulation layer 12 is an insulation layer formed by an in-situ growth process. In an example, the in-situ insulation layer 12 is a single-layer structure, and the material of the single-layer structure includes: one of or a mixture of SiN and A1N. In another example, the in-situ insulation layer 12 is a multi-layer structure, and the multi-layer structure may include, from bottom to top, a SiN layer and an A1N layer; or include, from bottom to top, an A1N layer and a SiN layer; or include, from bottom to top, a SiN layer, an A1N layer and a SiN layer.

[0118] Then, referring to step S3 in FIG. 2 and FIG. 4, a trench 13 penetrating through the in-situ insulation layer 12 is formed.

[0119] The trench 13 can be formed by dry etching or wet etching. Specifically, a patterned mask layer is first formed on the in-situ insulation layer 12. The mask layer may be a photoresist layer, which is patterned by a process of exposing first and then developing. The gas for dry etching can be CF.sub.4, C.sub.3 F.sub.8, etc., and the solution for wet etching can be hot phosphoric acid.

[0120] The sheet resistance (surface resistance) of the structure shown in FIG. 4 is tested, and the size is 325 Ω/❏.

[0121] Next, referring to step S4 in FIG. 2 and FIG. 5, a transition layer 14 and a p-type semiconductor layer 15 are sequentially formed in the trench 13 and on in-situ insulation layer 12.

[0122] The transition layer 14 may be formed using an in-situ growth process. In an example, the in-situ insulation layer 14 is a single-layer structure, and the material of the single-layer structure includes: one of or a mixture of two or more of A1N, SiA1N, and AlGaN. In another example, the transition layer 14 is a multi-layer structure, and the multi-layer structure may include at least two layers of an AlN layer, a SiAlN layer, and an AlGaN layer.

[0123] The material of the p-type semiconductor layer 15 includes Group III nitride, for example, at least one of GaN, AlGaN, or AlInGaN, where the p-type doped ions may be magnesium ions. For the formation process of the p-type semiconductor layer 15, reference may be made to the formation process of the channel layer 11a and the barrier layer 11b.

[0124] In this embodiment, the p-type semiconductor layer 15 has a concave region corresponding to the trench 13. In some embodiments, the upper surface of the p-type semiconductor layer 15 may also be flat.

[0125] Then, referring to step S5 in FIG. 2 and FIG. 1, a heavily doped n-type layer 16 is provided on the p-type semiconductor layer 15 in the gate region, and on the source region and the drain region of the heterojunction 11.

[0126] The material of the heavily doped n-type layer 16 may include Group III nitride, such as at least one of GaN, AlGaN, or AlInGaN, where the n-type doped ions may include at least one kind of Si ions, Ge ions, Sn ions, Se ions or Te ions. The formation process of the heavily doped n-type layer 16 can be referred to the formation process of the channel layer 11a and the barrier layer 11b. The n-type ions can be doped while growing, or the n-type ions can be injected after epitaxial growth.

[0127] In some embodiments, a heavily doped n-type layer 16 may also be provided on at least one of the p-type semiconductor layer 15 in the gate region, the source region of heterojunction 11, or the drain region of the heterojunction 11.

[0128] Next, referring to step S6 in FIG. 2 and FIG. 1, a gate electrode 17a is formed on the heavily doped n-type layer 16 in the gate region, a source electrode 17b is formed on the heavily doped n-type layer 16 in the source region, and a drain electrode 17c is formed in the heavily doped n-type layer 16 in the drain region.

[0129] The material of the source electrode 17b, the drain electrode 17c, and the gate electrode 17a can be metal, such as existing conductive materials such as Ti/Al/Ni/Au, Ni/Au, etc., and the source electrode 17b, the drain electrode 17c, and the gate electrode 17a can be correspondingly formed by physical vapor deposition or chemical vapor deposition.

[0130] In this embodiment, because there is a concave region of the p-type semiconductor layer 15 corresponding to the trench 13, a portion of the gate electrode 17a is located in the concave region. In some embodiments, the upper surface of the p-type semiconductor layer 15 and the lower surface of the gate electrode 17a may also be flat.

[0131] FIG. 6 is a structural diagram of a semiconductor structure according to a second embodiment of the present disclosure.

[0132] Referring to FIG. 6 and FIG. 1, the semiconductor structure 2 of the second embodiment is substantially the same as the semiconductor structure 1 of the first embodiment, except that the source electrode 17b and the drain electrode 17c are in contact with the channel layer 11a; and ohmic contact is formed, by using the heavily doped n-type ion layer 16, between the source electrode 17b and the channel layer 11a, and between drain electrode 17c and the channel layer 11a.

[0133] Correspondingly, the manufacturing method of the semiconductor structure 2 of the second embodiment is substantially the same as the manufacturing method of the semiconductor structure 1 of the first embodiment, the difference includes that in step S5, before the heavily doped n-type layer 16 is formed on the source region of the heterojunction 11 and the drain region of the heterojunction 11, the p-type semiconductor layer 15, the transition layer 14, the in-situ insulation layer 12 and the barrier layer 11b in the source region and the drain region are removed to expose the channel layer 11a. The heavily doped n-type layer 16 enables that an ohmic contact layer is directly formed without high temperature thermal annealing between the source electrode 17b and the channel layer 11a, and between the drain electrode 17c and the channel layer 11a.

[0134] In some embodiments, the source electrode 17b and the drain electrode 17c are in contact with the channel layer 11a, and ohmic contact is formed, by using the heavily doped n-type ion layer 16, between the source electrode 17b and the channel layer 11a, and between drain electrode 17c and the channel layer 11a. By high temperature annealing, an ohmic contact layer may be formed between the source electrode 17b and channel layer 11a without the heavily doped n-type layer 16, or between the drain electrode 17c and the channel layer 11a without the heavily doped n-type layer 16.

[0135] FIG. 7 is a structural diagram of a semiconductor structure according to a third embodiment of the present disclosure. FIG. 8 is a flowchart of a method of manufacturing the semiconductor structure provided by the third embodiment of the present disclosure.

[0136] Referring to FIG. 7, FIG. 1 and FIG. 6, the semiconductor structure 3 of the third embodiment is substantially the same as the semiconductor structures 1 and 2 of the first and second embodiments, the difference includes that: on the transition layer 14, the p-type semiconductor layer 15 is only provided in the gate region.

[0137] Correspondingly, referring to FIG. 8 and FIG. 2, the manufacturing method of the semiconductor structure 3 of the third embodiment is substantially the same as the manufacturing methods of the semiconductor structures 1 and 2 of the first embodiment and the second embodiment, and the difference includes that step S4' further includes a step of patterning the p-type semiconductor layer 15. In other words, step S4' includes: sequentially forming the transition layer 14 and the p-type semiconductor layer 15 in the trench 13 and on the in-situ insulation layer 12; patterning the p-type semiconductor layer 15 to only retain the p-type semiconductor layer 15 in the gate region.

[0138] Patterning p-type semiconductor layer 15 can be implemented by dry etching or wet etching. Compared with the method of patterning the p-type semiconductor layer 15 formed directly on the barrier layer 11b, the in-situ insulation layer 12 and the transition layer 14 can prevent the barrier layer 11b from being damaged by over-etching during the patterning process.

[0139] FIG. 9 is a structural diagram of a semiconductor structure according to a fourth embodiment of the present disclosure. Referring to FIG. 9, FIG. 1, FIG. 6 and FIG. 7, the semiconductor structure 4 of the fourth embodiment is substantially the same as the semiconductor structures 1, 2, and 3 of the first, second, and third embodiments, except that the semiconductor structure 4 is a semiconductor structure in progress, the gate electrode 17a, the source electrode 17b and the drain electrode 17c are not formed.

[0140] Correspondingly, the manufacturing method of the semiconductor structure 4 of the fourth embodiment is substantially the same as the manufacturing method of the semiconductor structures 1, 2, and 3 of the first, second, and third embodiments, and the difference includes that step S6 is omitted.

[0141] The semiconductor structure 4 can also be produced and sold as a semi-finished product.

[0142] FIG. 10 is a structural diagram of a semiconductor structure according to a fifth embodiment of the present disclosure. FIG. 11 is a flowchart of a method of manufacturing the semiconductor structure provided by the fifth embodiment of the present disclosure. FIG. 12 is a schematic diagram illustrating an intermediate structure corresponding to the process of FIG. 11.

[0143] Referring to FIG. 10, the semiconductor structure 5 includes: [0144] a semiconductor substrate 10, a heterojunction 11, an in-situ insulation layer 12 and a transition layer 14 disposed from bottom to top; [0145] a trench 13 penetrating through the in-situ insulation layer 12 and the transition layer 14; [0146] a p-type semiconductor layer 15 located in the trench 13 and on the transition layer 14; [0147] a heavily doped n-type layer 16 located on the p-type semiconductor layer 15 in the gate region, and on the source region and the drain region of the heterojunction 11; [0148] a gate electrode 17a located on the heavily doped n-type layer 16 in the gate region, a source electrode 17b located on the heavily doped n-type layer 16 in the source region, and a drain electrode 17c located on the heavily doped n-type layer 16 in the drain region.

[0149] Referring to FIG. 10, FIG. 12 and FIG. 1, the semiconductor structure 5 of the fifth embodiment is substantially the same as the semiconductor structure 1 of the first embodiment, the difference includes that the trench 13 penetrates through the in-situ insulation layer 12 and the transition layer 14, that is, the transition layer 14 is located on the in-situ insulation layer12 outside the trench 13.

[0150] Correspondingly, referring to FIG. 11, FIG. 12 and FIG. 2, the manufacturing method of the semiconductor structure 5 of the fifth embodiment is substantially the same as the manufacturing method of the semiconductor structure 1 of the first embodiment, the difference includes that step S2' includes: the in-situ insulation layer 12 and the transition layer 14 are sequentially formed on the heterojunction 11; the step S3' includes: forming a trench 13 penetrating through the in-situ insulation layer 12 and the transition layer 14; the step S4" includes: forming a p-type semiconductor layer 15 in the trench 13 and on the transition layer 14.

[0151] In FIG. 10, the source electrode 17b and the drain electrode 17c are in contact with the barrier layer 11b, and an ohmic contact may be formed both between the source electrode 17b and the barrier layer 11b and between the drain electrode 17c and the barrier layer 11b by heavily doped n-type layer 16. An ohmic contact is also formed between the gate electrode 17a and the p-type semiconductor layer 15 by the heavily doped n-type layer 16. The heavily doped n-type layer 16 can make an ohmic contact layer be directly formed between the source electrode 17b and the source region of the heterojunction 11, between the drain electrode 17c and the drain region of the heterojunction 11, and between the gate electrode 17a and the p-type semiconductor layer 15 in the gate region, without high temperature annealing.

[0152] In some embodiments, an n-type ion heavily doped layer 16 may also be provided on at least one of the p-type semiconductor layer 15 in the gate region, the source region of heterojunction 11, or the drain region of the heterojunction 11. By high temperature annealing, an ohmic contact layer may be formed between the gate electrode 17a and the p-type semiconductor layer 15 in the gate region without the heavily doped n-type layer 16, between the source electrode 17b and the source region of the heterojunction 11 without the heavily doped n-type layer 16, and between the drain electrode 17c and the drain region of the heterojunction 11 without the heavily doped n-type layer 16.

[0153] In the semiconductor structure 5, the in-situ insulation layer 12 and the transition layer 14 can reduce the gate leakage current leaked from the channel to the gate electrode 17a, so the thickness of the barrier layer 11b in the heterojunction 11 can be smaller, which can decrease threshold voltage; in addition, because in-situ insulation layer 12 is provided, the sheet resistance can be reduced, the concentration of the two-dimensional electron gas is increased, and therefore the control ability of the gate to the channel is improved, and the working current is increased.

[0154] In addition, in the existing HEMT structure of the AlGaN barrier layer/GaN channel layer, the thickness of the barrier layer 11b is from 15 nm to 25 nm to ensure the generation of a sufficient concentration of two-dimensional electron gas. In the present disclosure, when the thickness of the barrier layer 11b range is from 1 nm to 15 nm, a sufficient concentration of two-dimensional electron gas can be generated. In an example, the thickness of the barrier layer 11b can be controlled to be less than 10 nm.

[0155] FIG. 13 is a structural diagram of a semiconductor structure according to a sixth embodiment of the present disclosure;

[0156] Referring to FIG. 13 and FIG. 10, the semiconductor structure 6 of the sixth embodiment is substantially the same as the semiconductor structure 5 of the fifth embodiment, except that the source electrode 17b and the drain electrode 17c are in contact with the channel layer 11a; and ohmic contact is formed, by using the heavily doped n-type ion layer 16, between the source electrode 17b and the channel layer 11a, and between drain electrode 17c and the channel layer 11a.

[0157] Correspondingly, the manufacturing method of the semiconductor structure 6 of the sixth embodiment is substantially the same as the manufacturing method of the semiconductor structure 5 of the fifth embodiment, the difference includes that in step S5 , before the heavily doped n-type layer 16 is formed on the source region of the heterojunction 11 and the drain region of the heterojunction 11, the p-type semiconductor layer 15, the transition layer 14, the in-situ insulation layer 12 and the barrier layer 11b in the source region and the drain region are removed to expose the channel layer 11a . The heavily doped n-type layer 16 enables that an ohmic contact layer is directly formed without high temperature thermal annealing between the source electrode 17b and the channel layer 11a, and between the drain electrode 17c and the channel layer 11a.

[0158] In some embodiments, the source electrode 17b and the drain electrode 17c are in contact with the channel layer 11a, and ohmic contact is formed, by using the heavily doped n-type layer 16, between the source electrode 17b and the channel layer 11a, or between drain electrode 17c and the channel layer 11a. By high temperature annealing, an ohmic contact layer may be formed between the source electrode 17b and channel layer 11a without the heavily doped n-type layer 16, or between the drain electrode 17c and the channel layer 11a without the heavily doped n-type layer 16.

[0159] FIG. 14 is a structural diagram of a semiconductor structure according to a seventh embodiment of the present disclosure;

[0160] Referring to FIG. 14, FIG. 10 and FIG. 13, the semiconductor structure 7 of the seventh embodiment is substantially the same as the semiconductor structures 5 and 6 of the fifth and sixth embodiments, the difference includes that: on the transition layer 14, the p-type semiconductor layer 15 is provided in the gate region.

[0161] Correspondingly, the manufacturing method of the semiconductor structure 7 of the seventh embodiment is substantially the same as the manufacturing methods of the semiconductor structures 5 and 6 of the fifth embodiment and the sixth embodiment, and the difference includes that step S4" further includes a step of patterning the p-type semiconductor layer 15. In other words, step S4" includes: forming the p-type semiconductor layer 15 in the trench 13 and on the transition layer 14; patterning the p-type semiconductor layer 15 to only retain the p-type semiconductor layer 15 in the gate region.

[0162] Patterning p-type semiconductor layer 15 can be implemented by dry etching or wet etching. Compared with the method of patterning the p-type semiconductor layer 15 formed directly on the barrier layer 11b, the in-situ insulation layer 12 and the transition layer 14 can prevent the barrier layer 11b from being damaged by over-etching during the patterning process.

[0163] FIG. 15 is a structural diagram of a semiconductor structure according to an eighth embodiment of the present disclosure; Referring to FIG. 15, FIG. 10, FIG. 13 and FIG. 14, the semiconductor structure 8 of the eighth embodiment is substantially the same as the semiconductor structures 5, 6, and 7 of the fifth, sixth, and seventh embodiments, except that the semiconductor structure 8 is a semiconductor structure in progress, the gate electrode 17a, the source electrode 17b and the drain electrode 17c are not formed.

[0164] Correspondingly, the manufacturing method of the semiconductor structure 8 of the eighth embodiment is substantially the same as the manufacturing method of the semiconductor structures 5, 6, and 7 of the fifth, sixth, and seventh embodiments, and the difference includes that step S6 is omitted.

[0165] The semiconductor structure 8 can also be produced and sold as a semi-finished product.

[0166] Although the present disclosure discloses the above contents, the present disclosure is not limited thereto. One of ordinary skill in the art can make various variants and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be set forth by the appended claims.