A semiconductor device includes a substrate including a first main surface; a semiconductor layer provided on the first main surface of the substrate; an electrically insulating layer provided on the semiconductor layer; a source electrode and a drain electrode that are provided on the semiconductor layer; and a gate electrode provided on the electrically insulating layer. The semiconductor layer has an electron transport layer provided on the substrate and including a first upper surface, and has an electron supply layer provided on the electron transport layer. A first opening and a second opening are each formed in the electron supply layer and the electron transport layer. A third opening connected to the first opening and a fourth opening connected to the second opening are each formed in the electrically insulating layer.

The present disclosure provides a semiconductor structure and a manufacturing method therefor. In the semiconductor structure, a semiconductor substrate, a heterojunction and an in-situ insulation layer are disposed from bottom to top, a trench is provided in the in-situ insulation layer, and a transition layer is located on at least an in-situ insulation layer, the p-type semiconductor layer is located in the trench and on the gate region of the transition layer, and the heavily doped n-type layer is located on at least one of the p-type semiconductor layer in the gate region, the source region of the heterojunction, or the drain region of the heterojunction.

A semiconductor body having a base carrier portion and a type III-nitride semiconductor portion is provided. The type III-nitride semiconductor portion includes a heterojunction and two-dimensional charge carrier gas. One or more ohmic contacts are formed in the type III-nitride semiconductor portion, the ohmic contacts forming an ohmic connection with the two-dimensional charge carrier gas. A gate structure is configured to control a conductive state of the two-dimensional charge carrier gas. Forming the one or more ohmic contacts comprises forming a structured laser-reflective mask on the upper surface of the type III-nitride semiconductor portion, implanting dopant atoms into the upper surface of the type III-nitride semiconductor portion, and performing a laser thermal anneal that activates the implanted dopant atoms.

A semiconductor device includes a junction field effect transistor (JFET) including a source electrode, a drain electrode, and a gate electrode, and a metal oxide semiconductor field effect transistor (MOSFET) including a source electrode, a drain electrode, and a gate electrode. The JFET and the MOSFET are cascode-connected such that the source electrode of the JFET and the drain electrode of the MOSFET are electrically connected. A gate voltage dependency of the JFET or a capacitance ratio of a mirror capacitance of the MOSFET to an input capacitance of the MOSFET is adjusted in a predetermined range.

A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer, recesses, a passivation layer and an etch mask layer. The group III-V body layer is disposed on the substrate. The group III-V barrier layer is disposed on the group III-V body layer in the active region and the isolation region. The recesses are disposed in the group III-V barrier layer in the active region and the isolation region, respectively. The passivation layer disposed in the recesses of the active region and the isolation region. The etch mask layer disposed between the passivation layer and the group III-V barrier layer in the active region, where the etch mask layer is spaced apart from bottoms of the recesses in the active region and the isolation region.

A semiconductor structure includes a substrate with a plurality of word line trenches and source/drain regions each adjacent to each word line trench; a word line located in the word line trench, which includes a first conductive layer located at a bottom of the word line trench, a single junction layer and a second conductive layer stacked in sequence, in which a projection of the word line on a sidewall of the word line trench and the projection of the source/drain region on the sidewall of the word line trench have an overlapping region with a preset height, and when a voltage applied to the word line is less than a preset voltage, a resistance of the single junction layer is greater than the preset resistance, to make the first conductive layer and the second conductive layer disconnected.

A High Electron Mobility Transistor (HEMT) device can include an AlN buffer layer on a substrate and an epi-GaN channel layer on the AlN buffer layer. An AlN barrier layer can be on the Epi-GaN channel layer to provide a channel region in the epi-GaN channel layer. A GaN drain region can be recessed into the epi-GaN channel layer at a first end of the channel region and a GaN source region can be recessed into the epi-GaN channel layer at a second end of the channel region opposite the first end of the channel region. A gate electrode can include a neck portion with a first width that extends a first distance above the AlN barrier layer between the GaN drain region and the GaN source region to a head portion of the gate electrode having a second width that is greater than the first width.

A semiconductor device includes a transistor. The transistor includes a gate electrode, a channel layer, a gate dielectric layer, a first source/drain region and a second source/drain region and a dielectric pattern. The channel layer is disposed on the gate electrode. The gate dielectric layer is located between the channel layer and the gate electrode. The first source/drain region and the second source/drain region are disposed on the channel layer at opposite sides of the gate electrode. The dielectric pattern is disposed on the channel layer. The first source/drain region covers a first sidewall and a first surface of the dielectric pattern, and a second sidewall opposite to the first sidewall of the dielectric pattern is protruded from a sidewall of the first source/drain region.

A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first gate electrode disposed on the substrate and located in a first region of the semiconductor device. The semiconductor device also includes a first sidewall structure covering the first gate electrode. The semiconductor device further includes a protective layer disposed between the first gate electrode and the first sidewall structure. In addition, the semiconductor device includes a second gate electrode disposed on the substrate and located in a second region of the semiconductor device. The semiconductor device also includes a second sidewall structure covering a lateral surface of the second gate electrode.

A Group III-Nitride quantum well laser including a distributed Bragg reflector (DBR). In some embodiments, the DBR includes Scandium. In some embodiments, the DBR includes Al.sub.1-xSc.sub.xN, which may have 0<x≤0.45.