ANTIFUSE-TYPE ONE TIME PROGRAMMING MEMORY CELL AND CELL ARRAY STRUCTURE WITH SAME

Abstract

An antifuse-type one time programming memory cell includes a select device, a following device and an antifuse transistor. A first terminal of the select device is connected with a bit line. A second terminal of the select device is connected with a first node. A select terminal of the select device is connected with a word line. A first terminal of the following device is connected with the first node. A second terminal of the following device is connected with a second node. A control terminal of the following device is connected with a following control line. A first drain/source terminal of the antifuse transistor is connected with the second node. A gate terminal of the antifuse transistor is connected with an antifuse control line. A second drain/source terminal of the antifuse transistor is in a floating state.

Claims

1. A cell array structure comprising a first antifuse-type one time programming memory cell, the first antifuse-type one time programming memory cell comprising: a first select device, wherein a first terminal of the first select device is connected with a first bit line, a second terminal of the first select device is connected with a first node, and a select terminal of the first select device is connected with a first word line; a first following device, wherein a first terminal of the first following device is connected with the first node, a second terminal of the first following device is connected with a second node, and a first control terminal of the first following device is connected with a first following control line; and a first antifuse transistor, wherein a first drain/source terminal of the first antifuse transistor is connected with the second node, a gate terminal of the first antifuse transistor is connected with a first antifuse control line, and a second drain/source terminal of the first antifuse transistor is in a floating state, wherein the first select device comprises a first select transistor and a second select transistor, wherein a first drain/source terminal of the first select transistor is connected with the first bit line, a gate terminal of the first select transistor is connected with the first word line, a second drain/source terminal of the first select transistor is connected with a first drain/source terminal of the second select transistor, a gate terminal of the second select transistor is connected with the first word line, and a second drain/source terminal of the second select transistor is connected with the first node.

2. The array structure as claimed in claim 1, further comprising a second antifuse-type one time programming memory cell, wherein the second antifuse-type one time programming memory cell comprises: a second select device, wherein a first terminal of the second select device is connected with a second bit line, a second terminal of the second select device is connected with a third node, and a select terminal of the second select device is connected with the first word line; a second following device, wherein a first terminal of the second following device is connected with the third node, a second terminal of the second following device is connected with a fourth node, and a first control terminal of the second following device is connected with the first following control line; and a second antifuse transistor, wherein a first drain/source terminal of the second antifuse transistor is connected with the fourth node, a gate terminal of the second antifuse transistor is connected with the first antifuse control line, and a second drain/source terminal of the second antifuse transistor is in the floating state.

3. The array structure as claimed in claim 2, further comprising a third antifuse-type one time programming memory cell, wherein the third antifuse-type one time programming memory cell comprises: a third select device, wherein a first terminal of the third select device is connected with the first bit line, a second terminal of the third select device is connected with a fifth node, and a select terminal of the third select device is connected with a second word line; a third following device, wherein a first terminal of the third following device is connected with the fifth node, a second terminal of the third following device is connected with a sixth node, and a first control terminal of the third following device is connected with a second following control line; and a third antifuse transistor, wherein a first drain/source terminal of the third antifuse transistor is connected with the sixth node, a gate terminal of the third antifuse transistor is connected with a second antifuse control line, and a second drain/source terminal of the third antifuse transistor is in the floating state.

4. The cell array structure as claimed in claim 1, wherein the first following device comprises a first following transistor, wherein a first drain/source terminal of the first following transistor is connected with the first node, a gate terminal of the first following transistor is connected with the first following control line, and a second drain/source terminal of the first following transistor is connected with the second node.

5. The cell array structure as claimed in claim 1, wherein when a program action is performed, the first bit line receives a ground voltage, the first word line receives an on voltage, the first following control line receives a first control voltage, and the first antifuse control line receives a program voltage, wherein when the program action is performed, the first select device is turned on, the first following device is in a conducting state, and a gate oxide layer of the first antifuse transistor is ruptured, so that the first antifuse-type one time programming memory cell is in a low-resistance storage state.

6. The cell array structure as claimed in claim 5, wherein the program voltage is higher than the first control voltage, and the first control voltage is higher than the on voltage.

7. The cell array structure as claimed in claim 1, wherein when a program inhibition action is performed, the first bit line receives a ground voltage, the first word line receives an off voltage, the first following control line receives a first control voltage, and the first antifuse control line receives a program voltage, wherein when the program inhibition action is performed, the first select device is turned off, the first following device is in a conducting state, and a gate oxide layer of the first antifuse transistor is not ruptured, so that the first antifuse-type one time programming memory cell is in a high-resistance storage state.

8. The cell array structure as claimed in claim 1, wherein the first following device comprises a first following transistor and a second following transistor, wherein a first drain/source terminal of the first following transistor is connected with the first node, a gate terminal of the first following transistor is connected with the first following control line, a second drain/source terminal of the first following transistor is connected with a first drain/source terminal of the second following transistor, a gate terminal of the second following transistor is connected with a second following control line, and a second drain/source terminal of the second following transistor is connected with the second node.

9. The cell array structure as claimed in claim 8, wherein when a program action is performed, the first bit line receives a ground voltage, the first word line receives an on voltage, the first following control line receives a first control voltage, the second following control line receives a second control voltage, and the first antifuse control line receives a program voltage, wherein when the program action is performed, the first select device is turned on, the first following transistor is in a conducting state, and a gate oxide layer of the first antifuse transistor is ruptured, so that the first antifuse-type one time programming memory cell is in a low-resistance storage state.

10. The cell array structure as claimed in claim 9, wherein the program voltage is higher than the second control voltage, the second control voltage is higher than or equal to the first control voltage, and the first control voltage is higher than the on voltage.

11. The cell array structure as claimed in claim 8, wherein when a program inhibition action is performed, the first bit line receives a ground voltage, the first word line receives an off voltage, the first following control line receives a first control voltage, the second following control line receives a second control voltage, and the first antifuse control line receives a program voltage, wherein when the program inhibition action is performed, the first select device is turned off, the first following device is in a conducting state, and a gate oxide layer of the first antifuse transistor is not ruptured, so that the first antifuse-type one time programming memory cell is in a high-resistance storage state.

12. A cell array structure comprising a first antifuse-type one time programming memory cell, the first antifuse-type one time programming memory cell comprising: a first select device, wherein a first terminal of the first select device is connected with a first bit line, a second terminal of the first select device is connected with a first node, and a select terminal of the first select device is connected with a first word line; a first following device, wherein a first terminal of the first following device is connected with the first node, a second terminal of the first following device is connected with a second node, a first control terminal of the first following device is connected with a first following control line, and a second control terminal of the first following device is connected with a second following control line; and a first antifuse transistor, wherein a first drain/source terminal of the first antifuse transistor is connected with the second node, a gate terminal of the first antifuse transistor is connected with a first antifuse control line, and a second drain/source terminal of the first antifuse transistor is in a floating state, wherein the first following device comprises a first following transistor and a second following transistor, wherein a first drain/source terminal of the first following transistor is connected with the first node, a gate terminal of the first following transistor is connected with the first following control line, a second drain/source terminal of the first following transistor is connected with a first drain/source terminal of the second following transistor, a gate terminal of the second following transistor is connected with the second following control line, and a second drain/source terminal of the second following transistor is connected with the second node.

13. The array structure as claimed in claim 12, further comprising a second antifuse-type one time programming memory cell, wherein the second antifuse-type one time programming memory cell comprises: a second select device, wherein a first terminal of the second select device is connected with a second bit line, a second terminal of the second select device is connected with a third node, and a select terminal of the second select device is connected with the first word line; a second following device, wherein a first terminal of the second following device is connected with the third node, a second terminal of the second following device is connected with a fourth node, a first control terminal of the second following device is connected with the first following control line, and a second control terminal of the second following device is connected with the second following control line; and a second antifuse transistor, wherein a first drain/source terminal of the second antifuse transistor is connected with the fourth node, a gate terminal of the second antifuse transistor is connected with the first antifuse control line, and a second drain/source terminal of the second antifuse transistor is in the floating state.

14. The array structure as claimed in claim 13, further comprising a third antifuse-type one time programming memory cell, wherein the third antifuse-type one time programming memory cell comprises: a third select device, wherein a first terminal of the third select device is connected with the first bit line, a second terminal of the third select device is connected with a fifth node, and a select terminal of the third select device is connected with a second word line; a third following device, wherein a first terminal of the third following device is connected with the fifth node, a second terminal of the third following device is connected with a sixth node, a first control terminal of the third following device is connected with a third following control line, and a second control terminal of the third following device is connected with a fourth following control line; and a third antifuse transistor, wherein a first drain/source terminal of the third antifuse transistor is connected with the sixth node, a gate terminal of the third antifuse transistor is connected with a second antifuse control line, and a second drain/source terminal of the third antifuse transistor is in the floating state.

15. The cell array structure as claimed in claim 12, wherein the first select device comprises a first select transistor, wherein a first drain/source terminal of the first select transistor is connected with the first bit line, a gate terminal of the first select transistor is connected with the first word line, and a second drain/source terminal of the first select transistor is connected with the first node.

16. The cell array structure as claimed in claim 12, wherein when a program action is performed, the first bit line receives a ground voltage, the first word line receives an on voltage, the first following control line receives a first control voltage, the second following control line receives a second control voltage, and the first antifuse control line receives a program voltage, wherein when the program action is performed, the first select device is turned on, the first following device is in a conducting state, and a gate oxide layer of the first antifuse transistor is ruptured, so that the first antifuse-type one time programming memory cell is in a low-resistance storage state.

17. The cell array structure as claimed in claim 16, wherein the program voltage is higher than the second control voltage, the second control voltage is higher than or equal to the first control voltage, and the first control voltage is higher than the on voltage.

18. The cell array structure as claimed in claim 12, wherein when a program inhibition action is performed, the first bit line receives a ground voltage, the first word line receives an off voltage, the first following control line receives a first control voltage, the second following control line receives a second control voltage, and the first antifuse control line receives a program voltage, wherein when the program inhibition action is performed, the first select device is turned off, the first following device is in a conducting state, and a gate oxide layer of the first antifuse transistor is not ruptured, so that the first antifuse-type one time programming memory cell is in a high-resistance storage state.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:

[0036] FIG. 1A (prior art) is a schematic circuit diagram illustrating a conventional antifuse-type OTP memory cell as shown in FIG. 1A;

[0037] FIG. 1B (prior art) schematically illustrates associated bias voltages for performing a program action on the conventional antifuse-type OTP memory cell as shown in FIG. 1A;

[0038] FIG. 1C (prior art) schematically illustrates associated bias voltages for performing a program inhibition action on the conventional antifuse-type OTP memory cell;

[0039] FIG. 2A (prior art) is a schematic circuit diagram illustrating another conventional antifuse-type OTP memory cell;

[0040] FIG. 2B (prior art) schematically illustrates associated bias voltages for performing a program action on the conventional antifuse-type OTP memory cell as shown in FIG. 2A;

[0041] FIG. 2C (prior art) schematically illustrates associated bias voltages for performing a program inhibition action on the conventional antifuse-type OTP memory cell as shown in FIG. 2A;

[0042] FIG. 2D (prior art) is a plot illustrating the relationship between the control voltage and the leakage current when the conventional antifuse-type OTP memory cell undergoes a program inhibition action;

[0043] FIG. 3A is a schematic circuit diagram illustrating an antifuse-type OTP memory cell according to a first embodiment of the present invention;

[0044] FIG. 3B schematically illustrates associated bias voltages for performing a program action on the antifuse-type OTP memory cell as shown in FIG. 3A;

[0045] FIG. 3C schematically illustrates associated bias voltages for performing a program inhibition action on the antifuse-type OTP memory cell as shown in FIG. 3A;

[0046] FIG. 4A is a schematic circuit diagram illustrating an antifuse-type OTP memory cell according to a second embodiment of the present invention;

[0047] FIG. 4B schematically illustrates associated bias voltages for performing a program action on the antifuse-type OTP memory cell as shown in FIG. 4A;

[0048] FIG. 4C schematically illustrates associated bias voltages for performing a program inhibition action on the antifuse-type OTP memory cell as shown in FIG. 4A;

[0049] FIG. 5 is a schematic circuit diagram illustrating a cell array structure with plural antifuse-type OTP memory cells of the second embodiment and associated bias voltages;

[0050] FIG. 6A is a schematic circuit diagram illustrating an antifuse-type OTP memory cell according to a third embodiment of the present invention;

[0051] FIG. 6B schematically illustrates associated bias voltages for performing a program action on the antifuse-type OTP memory cell as shown in FIG. 6A;

[0052] FIG. 6C schematically illustrates associated bias voltages for performing a program inhibition action on the antifuse-type OTP memory cell as shown in FIG. 6A; and

[0053] FIG. 7 is a schematic circuit diagram illustrating a cell array structure with plural antifuse-type OTP memory cells of the third embodiment and associated bias voltages.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0054] FIG. 3A is a schematic circuit diagram illustrating an antifuse-type OTP memory cell according to a first embodiment of the present invention. As shown in FIG. 3A, the antifuse-type OTP memory cell 300 comprises a select device 310, a following device 320 and an antifuse transistor M.sub.AF.

[0055] The connection relationships between associated components of the antifuse-type OTP memory cell 300 will be described as follows. The first terminal of the select device 310 is connected with a bit line BL. The select terminal of the select device 310 is connected with a word line WL. The second terminal of the select device 310 is connected with the node y. The first terminal of the following device 320 is connected with the node y. The plural control terminals of the following device 320 are connected with corresponding following control lines. For succinctness, only two following control lines FL1 and FL2 are shown. The second terminal of the following device 320 is connected with the node z. The first drain/source terminal of the antifuse transistor M.sub.AF is connected with the node z. The gate terminal of the antifuse transistor M.sub.AF is connected with an antifuse control line AF. The second drain/source terminal of the antifuse transistor M.sub.AF is in a floating state.

[0056] In this embodiment, the select device 310 comprises two select transistors M.sub.S1 and M.sub.S2, and the following device 320 comprises two following transistors M.sub.FL1 and M.sub.FL2. The connection relationships between associated components of the select device 310 will be described as follows. The first drain/source terminal of the select transistor M.sub.S1 is connected with the bit line BL. The gate terminal of the select transistor M.sub.S1 is connected with the word line WL. The second drain/source terminal of the select transistor M.sub.S1 is connected with the first drain/source terminal of the select transistor M.sub.S2. The gate terminal of the select transistor M.sub.S2 is connected with the word line WL. The second drain/source terminal of the select transistor M.sub.S2 is connected with the node y. The connection relationships between associated components of the following device 320 will be described as follows. The first drain/source terminal of the following transistor M.sub.FL1 is connected with the node y. The gate terminal of the following transistor M.sub.FL1 is connected with the following control line FL1. The second drain/source terminal of the following transistor M.sub.FL1 is connected with the first drain/source terminal of the following transistor M.sub.FL2. The gate terminal of the following transistor M.sub.FL2 is connected with the following control line FL2. The second drain/source terminal of the following transistor M.sub.FL2 is connected with the node z.

[0057] Since the second drain/source terminal of the antifuse transistor M.sub.AF is in the floating state, the antifuse transistor M.sub.AF can be considered as a capacitor. Moreover, since the antifuse-type OTP memory cell 300 includes four transistors and one capacitor, the antifuse-type OTP memory cell 300 can be referred as a 4T1C cell. A program action or a program inhibition action can be selectively performed on the antifuse-type OTP memory cell 300. The two select transistors M.sub.S1 and M.sub.S2 are to be turned on or turned off according to the program action or the program inhibition action is performed. The two following transistors M.sub.FL1 and M.sub.FL2 are to be turned on in a conducting state always in the program action and the program inhibition action. The bias voltages for performing the program action or a program inhibition will be described as follows. In one embodiment, the channel length of the transistors in the antifuse-type OTP memory cell 300 is 16 nm.

[0058] FIG. 3B schematically illustrates associated bias voltages for performing a program action on the conventional antifuse-type OTP memory cell in the first embodiment as shown in FIG. 3A. FIG. 3C schematically illustrates associated bias voltages for performing a program inhibition action on the conventional antifuse-type OTP memory cell in the first embodiment as shown in FIG. 3A.

[0059] Please refer to FIG. 3B. When the program action is performed, the bit line BL receives a ground voltage (0V), the antifuse control line AF receives a program voltage V.sub.PP, the word line WL receives an on voltage V.sub.ON, the following control line FL1 receives a first control voltage V.sub.FL1, and the following control line FL2 receives a second control voltage V.sub.FL2. For example, the program voltage V.sub.PP is 5V, the on voltage V.sub.ON is 1V, the first control voltage V.sub.FL1 is 1.5V, and the second control voltage V.sub.FL2 is 2V. In response to the on voltage V.sub.ON, the two select transistors M.sub.S1 and M.sub.S2 can be turned on. That is, in response to the on voltage V.sub.ON, the select device 310 can be turned on. In response to the two control voltages V.sub.FL1 and V.sub.FL2, the following transistors M.sub.FL1 and M.sub.FL2 are controlled to be in a conducting state, respectively. That is, the following device 320 is in the conducting state. Consequently, the region between the node y and the node z is conducted. In this embodiment, the program voltage V.sub.PP is higher than the second control voltage V.sub.FL2, the second control voltage V.sub.FL2 is higher than or equal to the first control voltage V.sub.FL1, and the first control voltage V.sub.FL1 is higher than the on voltage V.sub.ON.

[0060] When the select device 310 is turned on and the following device 320 is in the conducting state, the ground voltage (0V) of the bit line BL is transferred to the first drain/source terminal of the antifuse transistor M.sub.AF. Consequently, the voltage stress between the gate terminal and the first drain/source terminal of the antifuse transistor M.sub.AF is equal to the program voltage V.sub.PP. Under this circumstance, a gate oxide layer of the antifuse transistor M.sub.AF is ruptured, and the region between the gate terminal and the first drain/source terminal of the antifuse transistor M.sub.AF has a low resistance value. That is, the antifuse-type OTP memory cell 300 is in a low-resistance storage state.

[0061] Please refer to FIG. 3C. When the program inhibition action is performed, the bit line BL receives the ground voltage (0V), the antifuse control line AF receives the program voltage V.sub.PP, the word line WL receives an off voltage V.sub.OFF, the following control line FL1 receives the first control voltage V.sub.FL1, and the following control line FL2 receives the second control voltage V.sub.FL2. For example, the program voltage V.sub.PP is 5V, the off voltage V.sub.OFF is 0V, the first control voltage V.sub.FL1 is 1.5V, and the second control voltage V.sub.FL2 is 2V. In response to the off voltage V.sub.OFF, the two select transistors M.sub.S1 and M.sub.S2 are turned off. That is, in response to the off voltage V.sub.OFF, the select device 310 is turned off.

[0062] When the select device 310 is turned off and the following device 320 is in the conducting state (the two following transistors M.sub.FL1 and M.sub.FL2 are in the conducting state), the ground voltage (0V) of the bit line BL cannot be transferred to the first drain/source terminal of the antifuse transistor M.sub.AF. Consequently, the voltage stress between the gate terminal and the first drain/source terminal of the antifuse transistor M.sub.AF is very low. Under this circumstance, the gate oxide layer of the antifuse transistor M.sub.AF is not ruptured, and the region between the gate terminal and the first drain/source terminal of the antifuse transistor M.sub.AF is maintained at a high resistance value. That is, the antifuse-type OTP memory cell 300 is in a high-resistance storage state.

[0063] Please refer to FIG. 3C again. When the program inhibition action is performed, the select device 310 is turned off. Meanwhile, the voltage at the node y is expressed as: Vy=(V.sub.FL1−V.sub.tFL1), and the select device 310 generates a leakage current. For example, the leakage current includes a punch current I.sub.Punch and a gate induced drain leakage (GIDL) current I.sub.GIDL1. In addition, the voltage at the node z is expressed as: Vz=(V.sub.PP−V.sub.tAF), and the following transistor M.sub.FL2 of the following device 320 generates a leakage current, e.g., a gate induced drain leakage (GIDL) current I.sub.GIDL2. For example, V.sub.tFL1 is a threshold voltage of the following transistor M.sub.FL1 (e.g., about 0.7V), and V.sub.tAF is a threshold voltage of the antifuse transistor M.sub.AF (e.g., about 1V).

[0064] As mentioned above, by adjusting the magnitude of the first control voltage V.sub.FL1, the voltage Vy at the node y can be further adjusted. Consequently, the punch current I.sub.Punch and the gate induced drain leakage current I.sub.GIDL1 can be further adjusted. For example, in case that the first control voltage V.sub.FL1 is 1.5V, the voltage Vy at the node y is about 0.8V (i.e., 1.5V−0.7V=0.8V). Under this circumstance, the select device 310 hardly generates the punch current I.sub.Punch, and the gate induced drain leakage current I.sub.GIDL1 is very low (e.g., about 1 nA).

[0065] Similarly, by adjusting the magnitude of the second control voltage V.sub.FL2, the voltage difference between the second drain/source terminal of the following transistor M.sub.FL2 (i.e., the node z) and the gate terminal of the following transistor M.sub.FL2 can be further adjusted. Consequently, the gate induced drain leakage current I.sub.GIDL2 is further adjusted. For example, in case that the second control voltage V.sub.FL2 is 2V, the voltage Vz at the node z is about 4V (i.e., 5V−1V=4V), and the voltage difference between the second drain/source terminal of the following transistor M.sub.FL2 and the gate terminal of the following transistor M.sub.FL2 is about 2V (i.e., 4V−2V=2V). Under this circumstance, the gate induced drain leakage current I.sub.GIDL2 is very low (e.g., about 3 nA).

[0066] In this embodiment, the select device 310 includes two select transistors M.sub.S1 and M.sub.S2. The serially-connected select transistors M.sub.S1 and M.sub.S2 can make the effective channel length of the selection device 310 increase, so that the punch current I.sub.Punch is reduced.

[0067] Furthermore, due to variations in the semiconductor manufacturing process, the select device 310 may receive an off voltage V.sub.OFF but cannot be completely turned off, resulting in an increase in leakage current. Since the select device 310 includes two serially-connected select transistors M.sub.S1 and M.sub.S2, as long as any one of the select transistors M.sub.S1 and M.sub.S2 receives the off voltage V.sub.OFF and is completely turned off, the select device 310 can be completely turned off to block the leakage current path. That is to ay, the leakage current of the antifuse-type OTP memory cell 300 can be reduced when the program inhibition action is performed.

[0068] In the first embodiment, each of the select device 310 and the following device 320 comprise two serially-connected transistors. It is noted that numerous modifications and alterations may be made while retaining the teachings of the invention. For example, in case that the channel length of the transistor is shorter, the select device 310 or the following device 320 may comprise at least two serially-connected transistors. For example, in a variant example of the antifuse-type OTP memory cell, the select device comprises three transistors, and the following device comprises two transistors. The three transistors of the select device are serially connected between the bit line BL and the node y. The two transistors of the following device are serially connected between the node y and the node z. Consequently, the antifuse-type OTP memory cell can be referred as a 5T1C cell. The gate terminals of the three transistors of the select device are connected with the word line. The gate terminals of the two transistors of the following device are connected with two different following control lines, respectively.

[0069] In another embodiment, the select device comprises two select transistors, and the following device comprises three following transistors. The two select transistors of the select device are serially connected between the bit line BL and the node y. The three following transistors of the following device are serially connected between the node y and the node z. Consequently, the antifuse-type OTP memory cell can be referred as a 5T1C cell. The gate terminals of the two transistors of the select device are connected with the word line. The gate terminals of the three transistors of the following device are connected with three different following control lines, respectively.

[0070] In another embodiment, the select device comprises three select transistors, and the following device comprises three following transistors. The three select transistors of the select device are serially connected between the bit line BL and the node y. The three following transistors of the following device are serially connected between the node y and the node z. Consequently, the antifuse-type OTP memory cell can be referred as a 6T1C cell. The gate terminals of the three transistors of the select device are connected with the word line. The gate terminals of the three transistors of the following device are connected with three different following control lines, respectively.

[0071] When the leakage current of the antifuse-type OTP memory cell is in the acceptable range, the antifuse-type OTP memory cell with a 3TIC cell configuration is also feasible. Some examples will be described as follows.

[0072] FIG. 4A is a schematic circuit diagram illustrating an antifuse-type OTP memory cell according to a second embodiment of the present invention. As shown in FIG. 4A, the antifuse-type OTP memory cell 400 comprises a select device 410, a following device 420 and an antifuse transistor M.sub.AF.

[0073] The connection relationships between associated components of the antifuse-type OTP memory cell 400 will be described as follows. The first terminal of the select device 410 is connected with a bit line BL. The select terminal of the select device 410 is connected with a word line WL. The second terminal of the select device 410 is connected with the node y. The first terminal of the following device 420 is connected with the node y. The control terminal of the following device 420 connected with corresponding following control line FL1. The second terminal of the following device 420 is connected with the node z. The first drain/source terminal of the antifuse transistor M.sub.AF is connected with the node z. The gate terminal of the antifuse transistor M.sub.AF is connected with an antifuse control line AF. The second drain/source terminal of the antifuse transistor M.sub.AF is in a floating state.

[0074] In this embodiment, the select device 410 comprises two select transistors M.sub.S1 and M.sub.S2, and the following device 420 comprises a following transistor M.sub.FL1. The connection relationships between associated components of the select transistor 410 will be described as follows. The first drain/source terminal of the select transistor M.sub.S1 is connected with the bit line BL. The gate terminal of the select transistor M.sub.S1 is connected with the word line WL. The second drain/source terminal of the select transistor M.sub.S1 is connected with the first drain/source terminal of the select transistor M.sub.S2. The gate terminal of the select transistor M.sub.S2 is connected with the word line WL. The second terminal of the select transistor M.sub.S2 is connected with the node y. The connection relationships between associated components of the following device 420 will be described as follows. The first drain/source terminal of the following transistor M.sub.FL1 is connected with the node y. The gate terminal of the following transistor M.sub.FL1 is connected with the following control line FL1. The second drain/source terminal of the following transistor M.sub.FL1 is connected with the node z.

[0075] Since the second drain/source terminal of the antifuse transistor M.sub.AF is in the floating state, the antifuse transistor M.sub.AF can be considered as a capacitor. Moreover, since the antifuse-type OTP memory cell 400 includes three transistors and one capacitor, the antifuse-type OTP memory cell 400 can be referred as a 3T1C cell.

[0076] FIG. 4B schematically illustrates associated bias voltages for performing a program action on the antifuse-type OTP memory cell as shown in FIG. 4A. FIG. 4C schematically illustrates associated bias voltages for performing a program inhibition action on the antifuse-type OTP memory cell as shown in FIG. 4A.

[0077] Please refer to FIG. 4B. When the program action is performed, the bit line BL receives a ground voltage (0V), the antifuse control line AF receives a program voltage V.sub.PP, the word line WL receives an on voltage V.sub.ON, and the following control line FL1 receives a first control voltage V.sub.FL1. For example, the program voltage V.sub.PP is 5V, the on voltage V.sub.ON is 1.2V, and the first control voltage V.sub.FL1 is 2V. In response to the on voltage V.sub.ON, the two select transistors M.sub.S1 and M.sub.S2 are turned on. That is, in response to the on voltage V.sub.ON, the select device 410 is turned on. In response to the first control voltage V.sub.FL1, the following transistor M.sub.FL1 is controlled to be in the conducting state. That is, the following device 420 is in the conducting state. Consequently, the region between the node y and the node z is conducted. In this embodiment, the program voltage V.sub.PP is higher than the first control voltage V.sub.FL1, and the first control voltage V.sub.FL1 is higher than the on voltage V.sub.ON.

[0078] When the select device 410 is turned on and the following device 420 is in the conducting state, the ground voltage (0V) of the bit line BL is transferred to the first drain/source terminal of the antifuse transistor M.sub.AF. Consequently, the voltage stress between the gate terminal and the first drain/source terminal of the antifuse transistor M.sub.AF is equal to the program voltage V.sub.PP. Under this circumstance, a gate oxide layer of the antifuse transistor M.sub.AF is ruptured, and the region between the gate terminal and the first drain/source terminal of the antifuse transistor M.sub.AF has a low resistance value. That is, the antifuse-type OTP memory cell 400 is in a low-resistance storage state.

[0079] Please refer to FIG. 4C. When the program inhibition action is performed, the bit line BL receives the ground voltage (0V), the antifuse control line AF receives the program voltage V.sub.PP, the word line WL receives an off voltage V.sub.OFF, and the following control line FL1 receives the first control voltage V.sub.FL1. For example, the program voltage V.sub.PP is 5V, the off voltage V.sub.OFF is 0V, and the first control voltage V.sub.FL1 is 2V. In response to the off voltage V.sub.OFF, the two select transistors M.sub.S1 and M.sub.S2 are turned off. That is, in response to the off voltage V.sub.OFF, the select device 410 is turned off.

[0080] When the select device 410 is turned off and the following device 420 is in the conducting state, the ground voltage (0V) of the bit line BL cannot be transferred to the first drain/source terminal of the antifuse transistor M.sub.AF. Consequently, the voltage stress between the gate terminal and the first drain/source terminal of the antifuse transistor M.sub.AF is very low. Under this circumstance, the gate oxide layer of the antifuse transistor M.sub.AF is not ruptured, and the region between the gate terminal and the first drain/source terminal of the antifuse transistor M.sub.AF is maintained at a high resistance value. That is, the antifuse-type OTP memory cell 400 is in a high-resistance storage state.

[0081] Please refer to FIG. 4C again. When the program inhibition action is performed, the select device 410 is turned off. Meanwhile, the voltage at the node y is expressed as: Vy=(V.sub.FL1−V.sub.tFL1), and the select device 410 generates a leakage current. For example, the leakage current includes a punch current I.sub.Punch and a gate induced drain leakage (GIDL) current I.sub.GIDL1. In addition, the voltage at the node z is expressed as: Vz=(V.sub.PP−V.sub.tAF), and the following transistor M.sub.FL2 of the following device 420 generates a leakage current, e.g., a gate induced drain leakage (GIDL) current I.sub.GIDL2. For example, V.sub.tFL1 is a threshold voltage of the following transistor M.sub.FL1 (e.g., about 0.7V), and V.sub.tAF is a threshold voltage of the antifuse transistor M.sub.AF (e.g., about 1V).

[0082] As mentioned above, by adjusting the first control voltage V.sub.FL1, the voltage Vy at the node y can be further adjusted. Consequently, the punch current I.sub.Punch and the gate induced drain leakage current I.sub.GIDL1 are further adjusted. For example, in case that the first control voltage V.sub.FL1 is 2V, the voltage Vy at the node y is about 1.3V (i.e., 2V−0.7V=1.3V). Under this circumstance, the punch current I.sub.Punch is about 50 pA, and the gate induced drain leakage current I.sub.GIDL1 is about 7 nA.

[0083] Similarly, by adjusting the first control voltage V.sub.FL1, the voltage difference between the second drain/source terminal of the following transistor M.sub.FL1 (i.e., the node z) and the gate terminal of the following transistor M.sub.FL1 can be further adjusted. Consequently, the gate induced drain leakage current I.sub.GIDL2 is further adjusted. For example, in case that the first control voltage V.sub.FL1 is 2V, the voltage Vz at the node z is about 4V (i.e., 5V−1V=4V), and the voltage difference between the second drain/source terminal of the following transistor M.sub.FL1 and the gate terminal of the following transistor M.sub.FL1 is about 2V (i.e., 4V−2V=2V). Under this circumstance, the gate induced drain leakage current I.sub.GIDL2 is very low (e.g., about 3 nA).

[0084] FIG. 5 is a schematic circuit diagram illustrating a cell array structure with plural antifuse-type OTP memory cells of the second embodiment and associated bias voltages. The cell array structure comprises m×n antifuse-type OTP memory cells, wherein m and n are positive integers. For illustration, the cell array structure 450 of this embodiment comprises 2×2 antifuse-type OTP memory cells c11-c22. Each of the antifuse-type OTP memory cells c11-c22 has the structure as shown in FIG. 4A. For example, the antifuse-type OTP memory cell c11 comprises a select device 451, a following device 452 and an antifuse transistor M.sub.AF.

[0085] Please refer to the cell array structure 450 of FIG. 5. Both of the two antifuse-type OTP memory cells c11-c12 in the first row are connected with a first word line WL1, a first following control line FL1 and a first antifuse control line AF1. Moreover, the two antifuse-type OTP memory cells c11-c12 in the first row are connected with a first bit line BL1 and a second bit line BL2, respectively. Both of the two antifuse-type OTP memory cells c21-c22 in the second row are connected with a second word line WL2, a second following control line FL2 and a second antifuse control line AF2. Moreover, the two antifuse-type OTP memory cells c21-c22 in the second row are connected with a first bit line BL1 and a second bit line BL2, respectively.

[0086] Please refer to FIG. 5 again. The antifuse control lines AF1 and AF2 receive a program voltage V.sub.PP, the following control lines FL1 and FL2 receive a first control voltage V.sub.FL1, the first bit line BL1 receives a ground voltage (0V), the second bit line BL2 receives an inhibition voltage V.sub.INH, the first word line WL1 receives an on voltage V.sub.ON, and the second word line WL2 receives an off voltage V.sub.OFF. For example, the program voltage V.sub.PP is 5V, the first control voltage V.sub.FL1 is 2V, the on voltage V.sub.ON is 1.2V, the off voltage V.sub.OFF is 0V, and the inhibition voltage V.sub.INH is 1.2V.

[0087] Consequently, the first row connected to the first word line WL1 is a selected row, and the second row connected to the second word line WL2 is an unselected row. In addition, the two antifuse-type OTP memory cells c21-c22 in the second row are unselected cells. Moreover, the first bit line BL1 receives the ground voltage (0V), and the second bit line BL2 receives the inhibition voltage V.sub.INH. Consequently, the antifuse-type OTP memory cell c11 is a selected cell, and the antifuse-type OTP memory cell c12 is an unselected cell. Moreover, in the cell array structure 450, the selected cell c11 undergoes a program action, and the unselected cell c12 undergoes an inhibition action.

[0088] FIG. 6A is a schematic circuit diagram illustrating an antifuse-type OTP memory cell according to a third embodiment of the present invention. As shown in FIG. 6A, the antifuse-type OTP memory cell 500 comprises a select device 510, a following device 520 and an antifuse transistor M.sub.AF.

[0089] The connection relationships between associated components of the antifuse-type OTP memory cell 500 will be described as follows. The first terminal of the select device 510 is connected with a bit line BL. The select terminal of the select device 510 is connected with a word line WL. The second terminal of the select device 510 is connected with the node y. The first terminal of the following device 520 is connected with the node y. The plural control terminals of the following device 520 are connected with corresponding following control lines. For succinctness, only two following control lines FL1 and FL2 are shown. The second terminal of the following device 520 is connected with the node z. The first drain/source terminal of the antifuse transistor M.sub.AF is connected with the node z. The gate terminal of the antifuse transistor M.sub.AF is connected with an antifuse control line AF. The second drain/source terminal of the antifuse transistor M.sub.AF is in a floating state.

[0090] In this embodiment, the select device 510 comprises a select transistors M.sub.S1, and the following device 520 comprises two following transistors M.sub.FL1 and M.sub.FL2. The connection relationships between associated components of the select transistor 510 will be described as follows. The first drain/source terminal of the select transistor M.sub.S1 is connected with the bit line BL. The gate terminal of the select transistor M.sub.S1 is connected with the word line WL. The second drain/source terminal of the select transistor M.sub.S1 is connected with the node y. The connection relationships between associated components of the following device 520 will be described as follows. The first drain/source terminal of the following transistor M.sub.FL1 is connected with the node y. The gate terminal of the following transistor M.sub.FL1 is connected with the following control line FL1. The second drain/source terminal of the following transistor M.sub.FL1 is connected with the first drain/source terminal of the following transistor M.sub.FL2. The gate terminal of the following transistor M.sub.FL2 is connected with the following control line FL2. The second drain/source terminal of the following transistor M.sub.FL2 is connected with the node z.

[0091] Since the second drain/source terminal of the antifuse transistor M.sub.AF is in the floating state, the antifuse transistor M.sub.AF can be considered as a capacitor. Moreover, since the antifuse-type OTP memory cell 500 includes three transistors and one capacitor, the antifuse-type OTP memory cell 500 can be referred as a 3T1C cell.

[0092] FIG. 6B schematically illustrates associated bias voltages for performing a program action on the antifuse-type OTP memory cell as shown in FIG. 6A. FIG. 6C schematically illustrates associated bias voltages for performing a program inhibition action on the antifuse-type OTP memory cell as shown in FIG. 6A.

[0093] Please refer to FIG. 6B. When the program action is performed, the bit line BL receives a ground voltage (0V), the antifuse control line AF receives a program voltage V.sub.PP, the word line WL receives an on voltage V.sub.ON, the first following control line FL1 receives a first control voltage V.sub.FL1, and the second following control line FL2 receives a second control voltage V.sub.FL2. For example, the program voltage V.sub.PP is 5V, the on voltage V.sub.ON is 1V, the first control voltage V.sub.FL1 is 1.5V, and the second control voltage V.sub.FL2 is 2V. In response to the on voltage V.sub.ON, the select transistors M.sub.S1 is turned on. That is, in response to the on voltage V.sub.ON, the select device 510 is turned on. In response to the first control voltage V.sub.FL1 and the second control voltage V.sub.FL2, the following transistors M.sub.FL1 and the M.sub.FL2 are controlled to be in the conducting state. That is, the following device 520 is in the conducting state. Consequently, the region between the node y and the node z is conducted. In this embodiment, the program voltage V.sub.PP is higher than the second control voltage V.sub.FL2, the second control voltage V.sub.FL2 is higher than or equal to the first control voltage V.sub.FL1, and the first control voltage V.sub.FL1 is higher than the on voltage V.sub.ON.

[0094] When the select device 510 is turned on and the following device 520 is in the conducting state, the ground voltage (0V) of the bit line BL is transferred to the first drain/source terminal of the antifuse transistor M.sub.AF. Consequently, the voltage stress between the gate terminal and the first drain/source terminal of the antifuse transistor M.sub.AF is equal to the program voltage V.sub.PP. Under this circumstance, a gate oxide layer of the antifuse transistor M.sub.AF is ruptured, and the region between the gate terminal and the first drain/source terminal of the antifuse transistor M.sub.AF has a low resistance value. That is, the antifuse-type OTP memory cell 500 is in a low-resistance storage state.

[0095] Please refer to FIG. 6C. When the program inhibition action is performed, the bit line BL receives the ground voltage (0V), the antifuse control line AF receives the program voltage V.sub.PP, the word line WL receives the off voltage V.sub.OFF, the first following control line FL1 receives the first control voltage V.sub.FL1, and the second following control line FL2 receives the second control voltage V.sub.FL2. For example, the program voltage V.sub.PP is 5V, the off voltage V.sub.OFF is 0V, the first control voltage V.sub.FL1 is 1.5V, and the second control voltage V.sub.FL2 is 2V. In response to the off voltage V.sub.OFF, the two select transistors MS1 and MS2 are turned off. That is, in response to the off voltage V.sub.OFF, the select device 510 is turned off.

[0096] When the select device 510 is turned off and the following device 520 is in the conducting state, the ground voltage (0V) of the bit line BL cannot be transferred to the first drain/source terminal of the antifuse transistor M.sub.AF. Consequently, the voltage stress between the gate terminal and the first drain/source terminal of the antifuse transistor M.sub.AF is very low. Under this circumstance, the gate oxide layer of the antifuse transistor M.sub.AF is not ruptured, and the region between the gate terminal and the first drain/source terminal of the antifuse transistor M.sub.AF is maintained at a high resistance value. That is, the antifuse-type OTP memory cell 500 is in a high-resistance storage state.

[0097] Please refer to FIG. 6C again. When the program inhibition action is performed, the select device 510 is turned off. Meanwhile, the voltage at the node y is expressed as: Vy=(V.sub.FL1−V.sub.tFL1), and the select device 510 generates a leakage current. For example, the leakage current includes a punch current I.sub.Punch and a gate induced drain leakage (GIDL) current I.sub.GIDL1. In addition, the voltage at the node z is expressed as: Vz=(V.sub.PP−V.sub.tAF), and the following transistor M.sub.FL2 of the following device 520 generates a leakage current, e.g., a gate induced drain leakage (GIDL) current I.sub.GIDL2. For example, V.sub.tFL1 is a threshold voltage of the following transistor M.sub.FL1 (e.g., about 0.7V), and V.sub.tAF is a threshold voltage of the antifuse transistor M.sub.AF (e.g., about 1V).

[0098] As mentioned above, by adjusting the first control voltage V.sub.FL1, the voltage Vy at the node y can be further adjusted. Consequently, the punch current I.sub.Punch and the gate induced drain leakage current I.sub.GIDL1 are further adjusted. For example, in case that the first control voltage V.sub.FL1 is 1.5V, the voltage Vy at the node y is about 0.8V (i.e., 1.5V−0.7V=0.8V). Under this circumstance, the select device 510 hardly generates the punch current I.sub.Punch, and the gate induced drain leakage current I.sub.GIDL1 is very low (e.g., about 1 nA).

[0099] Similarly, by adjusting the magnitude of the second control voltage V.sub.FL2, the voltage difference between the second drain/source terminal of the following transistor M.sub.FL2 (i.e., the node z) and the gate terminal of the following transistor M.sub.FL2 can be further adjusted. Consequently, the gate induced drain leakage current I.sub.GIDL2 is further adjusted. For example, in case that the second control voltage V.sub.FL2 is 2V, the voltage Vz at the node z is about 4V (i.e., 5V−1V=4V), and the voltage difference between the second drain/source terminal of the following transistor M.sub.FL2 and the gate terminal of the following transistor M.sub.FL2 is about 2V (i.e., 4V−2V=2V). Under this circumstance, the gate induced drain leakage current I.sub.GIDL2 is very low (e.g., about 3 nA).

[0100] FIG. 7 is a schematic circuit diagram illustrating a cell array structure with plural antifuse-type OTP memory cells of the third embodiment and associated bias voltages. The cell array structure comprises m×n antifuse-type OTP memory cells, wherein m and n are positive integers. For illustration, the cell array structure 550 of this embodiment comprises 2×2 antifuse-type OTP memory cells c11-c22. Each of the antifuse-type OTP memory cells c11-c22 has the structure as shown in FIG. 6A. For example, the antifuse-type OTP memory cell c11 comprises a select device 551, a following device 552 and an antifuse transistor M.sub.AF.

[0101] Please refer to the cell array structure 550 of FIG. 7. Both of the two antifuse-type OTP memory cells c11-c12 in the first row are connected with a first word line WL1, a first following control line FL1, a second following control line FL2 and a first antifuse control line AF1. Moreover, the two antifuse-type OTP memory cells c11-c12 in the first row are connected with a first bit line BL1 and a second bit line BL2, respectively. Both of the two antifuse-type OTP memory cells c21-c22 in the second row are connected with a second word line WL2, a third following control line FL3, a fourth following control line FL4 and a second antifuse control line AF2. Moreover, the two antifuse-type OTP memory cells c21-c22 in the second row are connected with a first bit line BL1 and a second bit line BL2, respectively.

[0102] Please refer to FIG. 7 again. The antifuse control lines AF1 and AF2 receive a program voltage V.sub.PP, the following control lines FL1 and FL3 receive a first control voltage V.sub.FL1, the following control lines FL2 and FL4 receive a second control voltage V.sub.FL2, the first bit line BL1 receives a ground voltage (0V), the second bit line BL2 receives an inhibition voltage V.sub.INH, the first word line WL1 receives an on voltage V.sub.ON, and the second word line WL2 receives an off voltage V.sub.OFF. For example, the program voltage V.sub.PP is 5V, the first control voltage V.sub.FL1 is 1.5V, the second control voltage V.sub.FL2 is 2V, the on voltage V.sub.ON is 1V, the off voltage V.sub.OFF is 0V, and the inhibition voltage V.sub.INH is 1.2V.

[0103] Consequently, the first row connected to the first word line WL1 is a selected row, and the second row connected to the second word line WL2 is an unselected row. In addition, the two antifuse-type OTP memory cells c21-c22 in the second row are unselected cells. Moreover, the first bit line BL1 receives the ground voltage (0V), and the second bit line BL2 receives the inhibition voltage V.sub.INH. Consequently, the antifuse-type OTP memory cell c11 is a selected cell, and the antifuse-type OTP memory cell c12 is an unselected cell. Moreover, the selected cell c11 in the cell array structure 550 undergoes a program action, and the unselected cell c12 undergoes an inhibition action.

[0104] Similarly, plural antifuse-type OTP memory cells of the first embodiment can be combined as a cell array structure. By providing proper bias voltages to the cell array structure, a program action and a program inhibition action can be selectively performed on the memory cells of the cell array structure. It is noted the bias voltages for performing the program action or the program inhibition action on the antifuse-type OTP memory cell of the present invention are not restricted. That is, the bias voltages for performing the program action or the program inhibition action on the antifuse-type OTP memory cell may be varied according to the practical requirements.

[0105] While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.