Power semiconductor module with short circuit failure mode

Abstract

A power semiconductor device includes a base plate; a Si chip including a Si substrate, the Si chip attached to the base plate; a first metal preform pressed with a first press pin against the Si chip; a wide bandgap material chip comprising a wide bandgap substrate and a semiconductor switch provided in the wide bandgap substrate, the wide bandgap material chip attached to the base plate; and a second metal preform pressed with a second press pin against the wide bandgap material chip; the Si chip and the wide bandgap material chip are connected in parallel via the base plate and via the first press pin and the second press pin; the first metal preform is adapted for forming a conducting path through the Si chip, when heated by an overcurrent; and the second metal preform is adapted for forming an temporary conducting path through the wide bandgap material chip or an open circuit, when heated by an overcurrent.

Claims

1. A power semiconductor module, comprising: a base plate; a Si chip comprising a Si substrate, the Si chip attached to the base plate; a first metal preform pressed with a first press pin against a side of the Si chip; a wide bandgap material chip comprising a wide bandgap substrate and a semiconductor switch provided in the wide bandgap substrate, the wide bandgap material chip attached to the base plate; a second metal preform pressed with a second press pin against a side of the wide bandgap material chip; wherein the Si chip and the wide bandgap material chip are connected in parallel via the base plate and via the first press pin and the second press pin; wherein the first metal preform is adapted for forming a conducting path through the Si chip by forming an alloy with the Si substrate, when heated by an overcurrent; wherein the second metal preform, which is made of a material with a higher melting point as a material of the first metal preform, is adapted for forming an at least temporary conducting path through the wide bandgap material chip, when heated by an overcurrent.

2. The power semiconductor module of claim 1, wherein the second metal preform is adapted for forming an at least temporary conducting path through the wide bandgap material chip by at least partially being melted by the overcurrent.

3. The power semiconductor module of claim 1, wherein the first metal preform is made of Al, Cu, Ag, Mg or an alloy thereof.

4. The power semiconductor module of claim 1, wherein the second metal preform is made of Mo, W or an alloy thereof.

5. The power semiconductor module of claim 1, wherein the base plate is made of Mo.

6. The power semiconductor module of claim 1, wherein the wide bandgap material of the wide bandgap material chip is SiC.

7. The power semiconductor module of claim 1, wherein the Si chip comprises a semiconductor switch provided in the Si substrate.

8. The power semiconductor module of claim 7, wherein a gate of the semiconductor switch of the Si chip is electrically connected in the semiconductor module with a gate of the semiconductor switch of the wide bandgap material chip.

9. The power semiconductor module of claim 7, wherein a gate of the semiconductor switch of the Si chip is electrically connected to a first gate terminal of the semiconductor module and a gate of the semiconductor switch of the wide bandgap material chip is electrically connected to a second gate terminal of the semiconductor module, such that the semiconductor switch of the Si chip is switchable independently of the semiconductor switch of the wide bandgap material chip.

10. The power semiconductor module of claim 7, wherein a gate of the semiconductor switch of the Si chip is not connected to a gate terminal provided by the semiconductor module.

11. The power semiconductor module of claim 1, wherein the Si chip does not comprise an active switchable switch.

12. The power semiconductor module of claim 1, wherein the Si chip is a passive Si layer.

13. The power semiconductor module of claim 1, wherein the power semiconductor module comprises at least two wide bandgap material chips connected in parallel with the Si chip.

14. The power semiconductor module of claim 1, further comprising: an electrically conducting top plate connected to the first press pin and the second press pin.

15. The power semiconductor module of claim 1, wherein at least one of the first press pin and the second press pin comprises a spring element.

16. The power semiconductor module of claim 2, wherein the first metal preform is made of Al, Cu, Ag, Mg or an alloy thereof.

17. The power semiconductor module of claim 1, wherein the second metal preform is made of Mo, W or an alloy thereof; and wherein the base plate is made of Mo.

18. The power semiconductor module of claim 2, wherein the wide bandgap material of the wide bandgap material chip is SiC.

19. The power semiconductor module of claim 2, wherein the Si chip comprises a semiconductor switch provided in the Si substrate.

20. The power semiconductor module of claim 17, wherein the wide bandgap material of the wide bandgap material chip is SiC.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The subject-matter of the invention will be explained in more detail in the following text with reference to exemplary embodiments which are illustrated in the attached drawings.

(2) FIG. 1 schematically shows a cross-section through a power semiconductor module according to an embodiment of the invention.

(3) FIG. 2 schematically shows a cross-section through a power semiconductor module according to a further embodiment of the invention.

(4) FIG. 3 schematically shows a cross-section through a power semiconductor module according to a further embodiment of the invention.

(5) FIG. 4 schematically shows a top view of a power semiconductor module according to a further embodiment of the invention.

(6) The reference symbols used in the drawings, and their meanings, are listed in summary form in the list of reference symbols. In principle, identical parts are provided with the same reference symbols in the figures.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

(7) FIG. 1 schematically shows a cross-section through a power semiconductor module 10, which comprises a base plate 12, a top plate 14 and two semiconductor chips 16a, 16b sandwiched between them.

(8) The base plate 12 may be an electrically conducting plate, for example made of Mo. Also, the top plate may be an electrically conducting plate, for example made of Cu or Al.

(9) The first semiconductor chip 16a is a Si chip based on a Si substrate as semiconductor. The second semiconductor chip 16b is a wide bandgap material chip based on a wide bandgap semiconductor substrate, such as SiC.

(10) The first and the second semiconductor chip 16a, 16b may comprise a first and second bottom electrode 18a, 18b and a first and second top electrode 20a, 20b. The terms top and bottom are not absolute geometrical positions, but are only used to distinguish between two opposite lying electrodes. Every electrode may be provided by a metal layer, which is much thinner than the thickness of the corresponding chip 16a, 16b. Both semiconductor chips 16a, 16b may be attached to the base plate 12, for example by sintering, soldering or welding.

(11) Directly on top of the Si chip 16a is a first metal preform 22a and directly on top of the chip 16b is a second metal preform 22b. The metal preforms 22a, 22b may be made of the same material or of different materials, as indicated above. One or both metal preforms 22a, 22b may be attached to the respective chip 16a, 16b (by sintering, soldering or welding) and/or may be pressed against the respective chip 16a, 16b, for example against the respective electrode 20a, 20b.

(12) A pressing force may be applied by an electrically conducting press pin 24a, 24b, which is pressed against the respective metal preform 22a, 22b. For example, the first and/or second press pin 24a, 24b may comprise a spring element 26a, 26b, which, for example, may comprise a disc spring. The metal preforms 22a, 22b, the press pins 24a, 24b and/or the spring elements 26a, 26b may be accommodated between the base plate 12 and the top plate 14.

(13) The metal preforms 22a, 22b may be in electrical contact with the top plate, for example via the press pins 24a, 24b and/or via the spring elements 26a, 26b. In such a way, the two chips 16a, 16b are connected in parallel to each other, wherein there is a metal preform 22a, 22b in every current path.

(14) The metal preform 22a is adapted for forming a conducting path through the Si chip 16a, when heated by an overcurrent. In such a way, a short circuit failure mode is provided, which forms a permanent conducting path to the Si chip 16a.

(15) The metal preform 22b is adapted for forming an at least temporary conducting path through the wide bandgap material chip 16b, when heated by an overcurrent. In such a way, a short circuit failure mode is provided, which forms a temporary conducting path to the wide bandgap material chip 16b.

(16) In combination, when a failure in the power semiconductor module 10 occurs, a current through the wide bandgap material chip 16b may form a temporary conducting path or even an open circuit. Simultaneously or after that, a conducting path may be formed through the Si chip 16a, which may provide a permanent short circuit failure mode for the semiconductor module 10. In such a way, a not so reliable short circuit failure mode for the wide bandgap material chip 16b may be supported by a more reliable short circuit failure mode provided by the Si chip 16a.

(17) Since the melting point of Si may be lower than the melting point of the wide bandgap material (which is the case for SiC and most other wide bandgap materials), the first metal preform 22a may be made of a metal material with a lower melting point than the metal material of the second metal preform 22b. For example, the metal preform 22a may be made of Al and the metal preform 22b may be made of Mo.

(18) In the case of Al, a very reliable short circuit failure mode may be provided, since Al may form an eutectic alloy with the Si material of the Si chip 16a.

(19) The wide bandgap material chip 16b comprises a semiconductor switch 28b, which is controllable with a gate 30b. The wide bandgap material chip 16b may comprise a gate electrode 32b on the same side as the electrode 20b, which may be electrically connected, for example via a wire bond, with a gate terminal 34b of the semiconductor module 10. For example, the semiconductor switch 28b may be a SiC MOSFET. During a normal operation mode, the semiconductor switch 28b may be switched on and off with gate signals from a gate unit connected via the terminal 34b.

(20) The Si chip 16a may be a functional or a dummy chip. As shown in FIG. 1, the Si chip 16a either may contain no semiconductor element at all or may contain a semiconductor element without a gate, such as a diode. It also may be that the Si chip 16a comprises a switch without a gate connection.

(21) As shown in FIGS. 2 and 3, the Si chip 16a may comprise a semiconductor switch 28a, which is controllable with a gate 30a. The Si chip 16a may comprise a gate electrode 32a on the same side as the electrode 20a, which may be electrically connected, for example via a wire bond, with a first and/or second gate terminal 34a, 34b of the semiconductor module 10. For example, the switch 28a may be an IGBT or IGCT.

(22) As shown in FIG. 2, the gate 30a of the Si chip 16a may be connected to the same gate terminal as the gate 30b of the wide bandgap chip 16b. In such a way, both switches 28a, 28b may be controlled with the same gate signal, which may be provided by the same gate unit. During a normal operation mode, both semiconductor switches 28b may be switched on and off with a gate signal from the same gate unit. During a failure operation mode, this gate unit also may provide a gate signal that forces the Si chip 16a to heat and to form a conducting path with the first metal preform 22a.

(23) As shown in FIG. 3, the gate 30a of the Si chip 16a may be connected to a different gate terminal as the gate 30b of the wide bandgap chip 16b, such that the switches 28a, 28b may be controlled independently from each other. Two independent gate signals may be provided to the switches 28a, 28b, for example from the same or from two different gate units.

(24) During normal operation mode, the switch 28b and optionally the switch 28a may be switched to control a current through the semiconductor module 10.

(25) In a failure operation mode, the switch 28a may be controlled such that the Si chip 16a heats and forms a conducting path with the first metal preform 22a. For example, the gate signal may be such that the Si chip 16a has a resistance, which results in enough power to be converted to heat for melting the first metal preform 22a.

(26) In general, the semiconductor module 10 shown in FIGS. 1 to 3 may be stacked with equally designed semiconductor modules 10 to form a high voltage switch, for example for AC-to-DC conversion in high voltage applications.

(27) The following scenarios may happen when there is a failure in one of the chips 16a, 16b being part of a semiconductor module 10 connected in series with other semiconductor modules 10.

(28) If the failure happens in the Si chip 16a first, the Si substrate will form a conducting path with the first metal preform 22a immediately after the failure as a high enough voltage across the chip 16a may be present, when the other semiconductor modules are conducting.

(29) If the failure happens firstly in the wide bandgap chip 16b, an at least temporary SCFM (short circuit failure mode) formation may take place. A conducting path is formed by melting and reacting wide bandgap material and the second metal preform 22b.

(30) A high resistance or open circuit after the wide bandgap chip 16b has failed, for example, because the conducting path in the wide bandgap chip 16b has not formed or has a too high resistance, may result in a passively forced Si SCFM formation. A following voltage spike will form a safe conducting path through the Si chip 16a as described above.

(31) Furthermore, a transition from a SCFM conducting path provided though the wide bandgap chip 16b to a Si SCFM conducting path through the Si chip 16a may be possible. The conducting path formed through the wide bandgap material may withstand the full current load only for a short period, the resistance may increase or may lead to an open circuit. Then a transition to a conducting path through the Si chip 16a may be formed as described above. This may extend the lifetime of the SCFM mode of the semiconductor module 10.

(32) Additionally, for the embodiment shown in FIG. 3, a separate gate unit may turn on the switch 28a to conduct the full load current immediately after the failure and/or to actively force a SCFM formation.

(33) FIG. 4 shows that one Si chip 16a is combined with more than one wide bandgap material chip 16b in one semiconductor module 10. In such a way, a short circuit failure mode may be provided for more than one wide bandgap material chip 16b by only one Si chip 16a. All the chips 16a, 16b in FIG. 4 may be provided with metal preforms 22a, 22b and press pins 24a, 24 as shown in FIGS. 1 to 3. Furthermore, the gates 30a, 30b may be connected as shown in FIG. 1 to FIG. 3, wherein the gates 30b of the switches 28b provided by the wide bandgap material chip 16b may be connected in parallel to the same second terminal 34b.

(34) While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art and practising the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word comprising does not exclude other elements or steps, and the indefinite article a or an does not exclude a plurality. A single processor or controller or other unit may fulfil the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.

LIST OF REFERENCE SYMBOLS

(35) 10 power semiconductor module 12 base plate 14 top plate 16a first, Si chip 16b second, wide bandgap material chip 18a first bottom electrode 18b second bottom electrode 20a first top electrode 20b second top electrode 22a first metal preform 22b second metal preform 24a first press pin 24b second press pin 26a first spring element 26b second spring element 28a first semiconductor switch 28b second semiconductor switch 30a first gate 30b second gate 32a first gate electrode 32b second gate electrode 34a first gate terminal 34b second gate terminal