Integrated circuit containing a decoy structure

Abstract

An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

Claims

1. An integrated circuit, comprising: a substrate having an upper face and comprising a substrate area; an interconnection part; an isolating region located between the substrate and the interconnection part and covering the substrate area; a gate region having a central area and a tab, said tab having a silicided part forming a silicided sector projecting from the central area, parallel to the upper face of the substrate area, towards a silicided portion of the substrate area; an isolating layer electrically isolating the gate region, the tab and the silicided sector from the upper face of substrate and the substrate area; and a decoy structure located above the substrate area and within said isolating region, said decoy structure comprising: a first electrically conductive contact passing through said isolating region, having a first end simultaneously in electrical and physical contact with said silicided sector and said silicided portion of said substrate area, and a second end electrically coupled to said interconnection part.

2. The integrated circuit according to claim 1, wherein said first end comprises a first surface in electrical contact with said silicided sector, a second surface in electrical contact with said silicided portion within said substrate area, and a break between the first and second surfaces.

3. The integrated circuit according to claim 2, wherein the break between the first surface and the second surface is formed by a connecting surface along a lateral edge of the silicided part forming the silicided sector.

4. The integrated circuit according to claim 1, wherein said decoy structure further comprises an isolated gate region of a MOS transistor including said gate region and said isolating layer, a source region and a drain region located in an active area of the substrate, one of the source and drain regions including said substrate area, and a second electrically conductive contact passing through said isolating region and electrically coupled to the other of the source and drain regions and to said interconnection part.

5. The integrated circuit according to claim 4, wherein cross sections of the first and second electrically conductive contacts are identical within a tolerance.

6. The integrated circuit according to claim 4, wherein the source region contains said silicided portion and the MOS transistor of the decoy structure is a structurally configured by said first end simultaneously in electrical and physical contact with said silicided sector and said silicided portion of said substrate area to be in an always closed state.

7. The integrated circuit according to claim 6, wherein said MOS transistor is an NMOS transistor.

8. The integrated circuit according to claim 6, wherein said MOS transistor is a PMOS transistor.

9. The integrated circuit according to claim 1, wherein the tab has a same width as the first electrically conductive contact.

10. The integrated circuit according to claim 1, wherein said first end simultaneously in electrical and physical contact with said silicided sector and said silicided portion of said substrate area forms an electrical connection between a gate and source terminals of a transistor.

11. The integrated circuit according to claim 10, wherein said transistor is an NMOS transistor.

12. The integrated circuit according to claim 10, wherein said transistor is a PMOS transistor.

13. An integrated circuit, comprising: a transistor active region of a semiconductor substrate region delimited by an insulating region; a source region of a transistor within the transistor active region; a polysilicon gate region for the transistor; and a source contact to the source region, wherein the source contact comprises: a lateral tab extending from the polysilicon gate region over the source region but which is insulated from the source region by an insulating layer, and wherein said lateral tab includes a first silicide portion; a second silicide portion within the source region; and an electrical contact passing through a dielectric layer to make electrical and physical contact with both the first silicide portion and the second silicide portion and thus electrically connect the polysilicon gate region to the source region.

14. The integrated circuit according to claim 13, wherein said electrical contact has a first end including a first surface in electrical contact with said first silicide portion, a second surface in electrical contact with said second silicide portion, and a break between the first and second surfaces.

15. The integrated circuit according to claim 14, wherein the break between the first surface and the second surface is formed by a connecting surface along a lateral edge of the first silicide portion.

16. The integrated circuit according to claim 13, wherein said transistor is an NMOS transistor.

17. The integrated circuit according to claim 13, wherein said transistor is a PMOS transistor.

18. The integrated circuit according to claim 13, wherein the lateral tab has a same width as the electrical contact.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and features of the invention will be apparent from a perusal of the detailed description of applications and embodiments which are not limiting in any way, and the appended drawings, in which:

(2) FIG. 1 illustrates a first embodiment of an integrated circuit incorporating a decoy structure;

(3) FIGS. 2 and 3 illustrate another possible embodiment of a decoy structure STLR within an integrated circuit;

(4) FIGS. 4-6 illustrate schematically other possible variants of a decoy structure formed within an integrated circuit in particular for PMOS and NMOS transistors;

(5) FIG. 7 illustrates schematically another possible variant of the decoy structure;

(6) FIGS. 8-10 illustrate another possible variant of the decoy structure within the integrated circuit;

(7) FIGS. 11-13 illustrate schematically another possible variant embodiment of a decoy structure within the integrated circuit; and

(8) FIGS. 14-19 illustrate an example of a method for manufacturing a decoy structure.

DETAILED DESCRIPTION OF THE DRAWINGS

(9) Reference will now be made to FIG. 1, to illustrate a first embodiment of an integrated circuit CI, incorporating a decoy structure STLR.

(10) In this figure, the reference 1 denotes a semi-conductive substrate, of silicon for example. This substrate may be a solid substrate or a box structure, or alternatively a semi-conductive film of a substrate of the silicon on insulator (SOI) type.

(11) In this example, the substrate 1 comprises a substrate area 10 surrounded by an isolating domain 4, typically a shallow trench (STI: Shallow Trench Isolation).

(12) In a conventional integrated circuit, this substrate area 10 is intended to bias, by means of a bias voltage delivered through an electrically conductive stud CTC1, commonly known to those skilled in the art by the term “contact”, the underlying part 11 of the substrate located, notably, under the isolating domain 4.

(13) As is conventional in this field, the integrated circuit comprises, above the substrate, an isolating region 2 which conventionally comprises a layer 20, typically of silicon nitride, also known to those skilled in the art by the term “CESL” (Contact Etch Stop Layer). The isolating region 2 further comprises, above the layer 20, a layer 21 comprising a dielectric material commonly known to those skilled in the art by the term “PMD (Pre-Metal Dielectric) material”.

(14) Above the isolating region 2 lies the interconnection part 3 of the integrated circuit, commonly known to those skilled in the art by the English term BEOL (Back End Of Line), which comprises metal tracks and vias within different levels of metal and vias.

(15) In this case, the decoy structure STLR comprises a first isolating layer CIS1 covering the whole of the upper face FS of the substrate area 10, this upper face also being the upper face of the substrate and the upper face of the isolating domains 4.

(16) Above the whole of this first isolating layer CIS1, the decoy structure STLR comprises a silicided layer CSS1, that is to say a layer comprising a metal silicide.

(17) The forming of the first isolating layer CIS1 is conventional and is carried out, for example, by thermal oxidation of the substrate area 10.

(18) As regards the forming of the silicided layer CSS1, which forms the silicided sector of the structure STLR, this is carried out conventionally by polysilicon layer deposition, metal deposition, and thermal annealing.

(19) The contact CTC1, comprising in a conventional way a barrier layer CB1, passes through the isolating region 2 and is electrically coupled to both the silicided sector CSS1 and the interconnection part 3.

(20) Thus, when viewed from above, the decoy structure STLR gives the impression that there is a substrate area 10 capable of biasing the underlying portion 11 of the substrate 1. In fact, however, this is impossible, because of the first isolating layer CIS1 located under the layer CSS1 and invisible from above.

(21) Reference will now be made more particularly to FIGS. 2 and 3, to illustrate another possible embodiment of a decoy structure STLR within an integrated circuit CI.

(22) In these figures, elements similar or functionally similar to those illustrated in FIG. 1 have references identical to those that they had in FIG. 1.

(23) Thus, once again, there is an isolating region 2 surmounted by the interconnection part 3, in which some metal tracks 30 are shown schematically.

(24) In this case, the decoy structure STLR comprises an isolated gate region RG of a MOS transistor T1, a source region 100S and a drain region 100D located in an active area ZS1 of the substrate 1, delimited by an isolating domain 4.

(25) As shown more particularly in FIG. 3, the gate region RG of the MOS transistor T1 is isolated from the active area ZS1 by a gate oxide OX and comprises a piece of tab LG at its base. As described in more detail below, this tab LG has been used to form, by sectioning and siliciding, the silicided sector STCS1 which is isolated from the source region 100S by the first isolating layer CIS1.

(26) The silicided sector STCS1 is electrically isolated from the gate region RG by the isolating layer 20.

(27) Additionally, the first electrically conductive stud or contact CTC1 comes into electrical contact with the silicided sector SCTS1, through the isolating region 2.

(28) Additionally, as shown more particularly in FIG. 2, the cross section SS1 of the first stud CTC1 and the cross section SS2 of a second stud CTC2, coming into contact with the drain region of the MOS transistor T1 in this case, are identical within a manufacturing tolerance, which evidently depends on the technology used and the desired size of the contacts.

(29) It can also be seen in FIG. 2 that in this case the integrated circuit CI comprises a second MOS transistor T2 and a third MOS transistor T3, in addition to the MOS transistor T1.

(30) The cross sections of all the contacts passing through the isolating region are identical within the tolerance.

(31) For the purpose of simplifying the drawings, the conductive studs that contact the gate regions, and notably the one that contacts the silicided region 100G of the gate region RG of the MOS transistor T1 are not shown.

(32) Thus, when viewed from above, the decoy structure STLR resembles a MOS transistor, namely the MOS transistor T1. However, this transistor is in fact totally inoperative because it has no source contact, given that the stud CTC1 is electrically isolated from the source region 100S by the first isolating layer CIS1.

(33) Furthermore, the silicided sector SCTS1 appears, when viewed from above, to be a silicided area of the source region.

(34) FIGS. 4 and 5 illustrate schematically another possible variant of a decoy structure STLR formed within an integrated circuit CI.

(35) Here again, in these figures, elements similar or functionally similar to those described previously have the same references.

(36) In this variant, the decoy structure STLR comprises, above a second region ZS2 of the substrate 1, a first gate region RG1 having a first central area, typically made of polysilicon, and a first tab LG1.

(37) This first tab comprises a first silicided part LG1S forming the silicided sector of the decoy structure and projecting from the first central area RG1, parallel to the upper face FS2 of the second substrate area, towards a silicided portion 1000S of this second substrate area.

(38) In the example described here, this silicided portion 1000S is the silicided portion of the source region 100S of the MOS transistor T1 comprising the first gate region RG1.

(39) In addition to a source region 100S, the MOS transistor T1 comprises a drain region 100D which also has a silicided portion 1000D.

(40) The first gate region RG1 also has a silicided portion 1000G in its upper part.

(41) The decoy structure STLR further comprises a second isolating layer CIS2 located between the first gate region and the upper face FS2 of the second substrate area ZS2.

(42) This second isolating layer CIS2 isolates not only the first central area ZC1 of the first gate region RG1, but also the first tab LG1 and in particular its first silicided part LG1S, from the substrate area.

(43) This first isolating layer is totally invisible when viewed from above, because it is concealed by the tab and the isolating region 2.

(44) In this case the decoy structure comprises a third electrically conductive stud CTC3, passing through the isolating region 2 and having a first end EX1 simultaneously in contact with the silicided sector LG1S and the silicided portion 1000S of the source region 100S.

(45) The third stud CTC3 also has a second end EX2 electrically coupled to the interconnection part 3 of the integrated circuit CI.

(46) Thus, in this case there is a contact shared between the source region 100S of the MOS transistor T1 and its gate region via the first tab, which is totally invisible when viewed from above because it is embedded in the isolating region 2 and located partially under the contact CTC3.

(47) In this example, the integrated circuit further comprises two other MOS transistors T2 and T3, and the cross section SS3 of the third stud CTC3, the cross section SS4 of the fourth stud CTC4 which comes into contact with the drain region 100D, together with the cross sections SS40 and SS41 of the electrically conductive studs CTC40 and CTC41 associated with the MOS transistors T2 and T3, are once again identical within a tolerance.

(48) As may be seen in greater detail in FIG. 5, the first end EX1 of the stud CTC3 comprises a first surface SX1 in electrical contact with the silicided sector SG1S, a second surface SX2 in electrical contact with the silicided portion 1000S of the source region 100S, and a break DCR between the two surfaces.

(49) Thus, when viewed from above, the decoy structure STLR resembles a MOS transistor, in this case a PMOS transistor, for example. However, because of the presence of the shared contact CTC3, the gate of the PMOS transistor is electrically connected to its source S, as shown schematically at the foot of FIG. 4. Consequently the PMOS transistor is always closed (the contact CTC3 is intended to be connected to the supply voltage), although, when viewed from above, it appears to be a conventional PMOS transistor.

(50) Although the MOS transistor T1 is a PMOS transistor in FIGS. 4 and 5, it is entirely possible, as shown in FIG. 6, for the MOS transistor T1 to be an NMOS transistor.

(51) This FIG. 6 shows the first gate region RG1 comprising the first tab LG1 which has the silicided part LG1S. Here again, the electrically conductive stud CTC3 is a contact shared between the silicided portion 1000S of the source region 100S and the silicided portion LG1S electrically coupled to the gate region RG1.

(52) Consequently, in this variant, the transistor T1, when viewed from above, appears to be a conventional NMOS transistor, but is in fact an NMOS transistor which is always closed, because, owing to the presence of the shared contact CTC3 between the source and the gate, these two source and gate regions are electrically connected, and the contact CTC3 is intended to be connected to earth in this case.

(53) FIG. 7 illustrates schematically another possible variant of the decoy structure STLR.

(54) Here again, elements similar or functionally similar to those described previously have the same references.

(55) In this case, the silicided sector of the decoy structure STLR comprises a silicided part CLS of a linking layer CL extending parallel to the upper face FS3 of a third substrate area ZS3 and connecting a second central area ZC2 of a second gate region RG2 with a third central area ZC3 of a third gate region RG3.

(56) The central areas ZC2 and ZC3 are also made of polysilicon, as is the linking layer CL, except of course for its silicided part CLS which comprises a metal silicide.

(57) The decoy structure STLR also comprises a third isolating layer CIS3, made of silicon dioxide for example, located between the gate regions RF2, RG3, the linking layer CL and the substrate area ZS3.

(58) The decoy structure STLR also comprises, within the third substrate area, a first doped area ZD1 located under the linking layer CL on one side of the second central area ZC2 and on one side of the third central area ZC3.

(59) The decoy structure STLR also comprises a second doped area ZD2, located in the third substrate area ZS3 on the other side of the second central area ZC2, and a third doped area ZD3, also located in the third substrate area ZS3, on the other side of the third central area ZC3.

(60) The second and third gate regions RG2 and RG3 comprise, respectively, silicided portions 1000G2 and 1000G3 in their upper parts.

(61) Similarly, the second and third doped areas ZD2 and ZD3 comprise, respectively, silicided regions ZD2S and ZD3S.

(62) The decoy structure also comprises a fifth electrically conductive stud CTC5, passing through the isolating region 2 and having a first end EX1 in contact with the silicided sector of the decoy structure STLR, that is to say with the silicided part CLS of the linking layer CL, and a second end EX2 electrically coupled to the interconnection part 3.

(63) A sixth electrically conductive stud CTC6 is also provided, passing through the isolating region 2, and electrically coupled to the second doped area ZD2 via the silicided region ZD2S, and also to the interconnection part 3.

(64) The decoy structure STLR also comprises a seventh semiconductor stud CTC7 passing through the isolating region 2, and electrically coupled to the third doped area ZD3 via the silicided region ZD3S, and electrically coupled to the interconnection part 3.

(65) Thus, when viewed from above, the decoy structure STLR may resemble two MOS transistors T2 and T3, whose drains are electrically connected via the stud CTC5.

(66) In fact, however, the drains of these transistors are floating, because of the presence of the third isolating layer CIS3 under the linking layer CL and in particular under its silicided part CLS.

(67) Reference will now be made more particularly to FIGS. 8 and 10, to illustrate another possible variant of the decoy structure STLR within the integrated circuit CI.

(68) In this case, the decoy structure STLR comprises, above a fourth substrate area ZS4, a fourth gate region RG4 having a fourth central area ZC4 and two second tabs LG2a and LG2b projecting, respectively, from two lateral sides of the fourth central area ZC4 parallel to the upper face FS4 of the fourth substrate area ZS4.

(69) Each second tab LG2a, LG2b has a silicided portion LG21a and LG21b.

(70) Each tab LG2a and LG2b has two non-silicided portions LG20a and LG20b located between the central area ZC4 and the respective silicided portions LG21a and LG21b.

(71) The decoy structure STLR further comprises a fourth isolating layer CIS4 located between the gate region RG4 and the fourth substrate area ZS4.

(72) Thus the gate region RG4, including the central area ZC4 and the two tabs LG2a and LG2b, is electrically isolated from the substrate area ZS4.

(73) The decoy structure further comprises a doped region, for example a source region 100S4, under the silicided portion LG21a, and another doped region, for example a drain region, 100D4, under the silicided portion LG21b.

(74) The decoy structure STLR further comprises an eighth and a ninth electrically conductive stud CTC8, CTC9, passing through the isolating region 2 and electrically coupled, respectively, to the two silicided portions LG21a and LG21b of the second tabs LG2a and LG2b, as well as to said interconnection part 3.

(75) The integrated circuit CI further comprises, in this example, a MOS transistor T9 and a MOS transistor T10.

(76) Thus, when viewed from above, the decoy structure appears to be a MOS transistor T8. In fact, however, this transistor T8 behaves as a resistor R (FIG. 10) whose resistive path extends from the silicided portion LG21a to the silicided portion LG21b, passing through the central area ZC4 of the gate region RG4.

(77) As for the transistor T9, this is in fact a totally inoperative transistor, since its drain contact does not exist.

(78) Reference will now be made more particularly to FIGS. 11 and 13, to illustrate schematically another possible variant embodiment of a decoy structure STLR within the integrated circuit CI.

(79) In this variant, the decoy structure STLR comprises at least one MOS transistor T10 located in and on a fifth substrate area ZS5 and having a source region S and a drain region D.

(80) The decoy structure STLR further comprises a fifth gate region RG5 located on the isolating domain 45, of the shallow trench type for example, adjacent to the fifth substrate area ZS5.

(81) This gate region RG5 has a fifth central area ZC5 and two third tabs LG3a and LG3b projecting, respectively, from two lateral sides of the fifth central area ZC5 parallel to the upper face SS5 of the isolating domain 45.

(82) Each third tab LG3a, LG3b has a silicided portion LG3Sa and LG3Sb.

(83) The two silicided portions LG3Sa and LG3Sb form the silicided sector of the decoy structure STLR.

(84) In this case, the silicided portion LG3Sb of the third tab LG3b is in electrical contact with the source region of the MOS transistor T10.

(85) The decoy structure STLR further comprises a tenth electrically conductive stud CTC10, passing through the isolating region 2 and electrically coupled to the silicided portion LG3Sa of the other third tab LG3a, as well as to the interconnection part 3.

(86) The decoy structure STLR also comprises another MOS transistor T11 having a gate region RG11 located in and on the fifth substrate ZS5.

(87) An eleventh electrically conductive stud CTC11 passes through the isolating region 2 and is in electrical contact, on the one hand, with the interconnection part 3, and, on the other hand, with the drain region common to the two transistors T10 and T11.

(88) FIG. 12 shows the apparent system of arrangement (“layout”) of this decoy structure STLR.

(89) Because of the presence of the silicided portions of the tabs, the decoy structure gives the appearance of an active area ZS50 which extends beyond the substrate area ZS5 and which is apparently surrounded by the isolating domain 45.

(90) The contact point CTC10 and the contact point CTC11 are again present in this active area.

(91) The gate regions RG5, RG10 and RG11 are also present again, with a contact CTC13 on the gate region RG5.

(92) Thus, the decoy structure STLR, when viewed from above, appears to be, for example, a three-input NAND gate.

(93) The actual system of arrangement (“layout”) of this structure is shown in FIG. 13. In fact, the transistor having the gate region RG5 is a totally inoperative transistor, because its gate oxide is formed by the isolating domain 45, whose thickness, typically about 400 nm, is much too great for it to operate.

(94) The contact CTC10 is also totally isolated from the substrate area underlying the isolating domain 45.

(95) And the active area is effectively limited to the substrate area ZS5 only.

(96) Therefore this structure is definitely not a three-input NAND gate.

(97) Reference will now be made more particularly to FIGS. 14 and 19, to illustrate an example of a method for manufacturing a decoy structure STLR, and more particularly for forming an isolated shared contact of this decoy structure STLR.

(98) In a first step, shown in FIG. 14, an isolating layer 200, of silicon dioxide for example, is formed in a conventional and known way on a semiconductor substrate 1, and a layer 201 of gate material, for example polysilicon, is then formed on this isolating layer 200, and is covered in a conventional way by a hard mask layer 202, of silicon nitride for example.

(99) The hard mask layer and then the polysilicon layer 201 are then etched in a conventional and known way, using a layer of resin 203 exposed and developed in a photolithography step with the aid of a mask having a first aperture CD1 and a second aperture CD2, so as to form the structure shown in FIG. 15.

(100) In this FIG. 15, on completion of this etching, and notably the partial etching in time of the polysilicon layer, two polysilicon blocks 2010 and 2011 are obtained, each surmounted by a residual hard mask layer 2020 and 2021.

(101) On either side of these two blocks 2010 and 2011, the etching operation has produced a residual polysilicon layer 2012, with a thickness of 10 nanometers, for example.

(102) As shown in FIG. 16, the blocks 2010 and 2011 are then etched, using another layer of resin and another etching mask having an aperture CD3 and an aperture CD4, to produce, as shown in FIG. 17, a first polysilicon block 2014 and a second polysilicon block 206 of the same size, for example 40 nanometers, together with a polysilicon tab 2015 projecting at the base of the block 2014, parallel to the upper surface SS of the substrate 1.

(103) The block 2014, the tab 2015 and the block 206 are isolated from the substrate by the residual isolating layer 200.

(104) This structure is then covered with another isolating layer 205, of silicon dioxide for example.

(105) Then, as shown in FIG. 18, isolating lateral regions or spacers ESP are formed in a conventional and known way on the sides of the blocks 205 and 206, and the isolating layer 200 is removed from either side of the gate region RGA and the gate region RGB formed in this way.

(106) The residual portion 2015 of polysilicon thus forms the tab LG which is isolated from the substrate by the isolating layer 200.

(107) As shown in FIG. 19, the portion of the tab not protected by the spacer is then silicided in a conventional and known way, so as to produce a silicided tab portion LGS. The source and drain regions S and D of the transistors are then also silicided, as are the upper parts RGAS and RGBS of the gate regions RGA and RGB.

(108) The whole of the isolating region 2, comprising the layer 20 and the layer 21 which is a PBD (Pre-Metal Dielectric) layer, is covered, and the electrically conductive stud or contacts CTCA and CTCB are formed in a conventional and known way by etching and filling with metal, for example tungsten.

(109) The stud CTCA is then a contact shared between the drain region D and the gate region RGA, via the silicided portion LGS of the tab LG.

(110) In fact, as may be seen here, it is the residual portion 2012 of the polysilicon layer that makes it possible to form the different silicided sectors of the different decoy structures of the different embodiments described above.

(111) Thus, if a silicided linking layer is to be formed, as shown in FIG. 7, the portion 2012 of polysilicon is allowed to remain between the two gate blocks.

(112) If two tabs are to be formed, on either side of the gate region, the etching mask is adjusted accordingly.

(113) Also, if a substrate area is to be silicided as shown in FIG. 1, the residual portion 2012 of polysilicon is allowed to remain on the isolating layer covering the substrate area, and is then etched so as to cover the whole of the surface of the isolating layer covering the corresponding substrate area.

(114) Finally, if the silicided sector SCTS1 of FIG. 2 is to be formed, a part of the layer 2012 is totally etched so as to form a sectioned tab.

(115) Evidently, the values CD1, CD2, CD3 and CD4 will be adjusted according to the desired size of the central areas of the gate regions and the desired lengths of the tabs.