Antenna array

Abstract

The invention provides an antenna array comprising: a plurality of antenna modules, each of the antenna modules comprising an antenna, a signal conductor and one or more microelectromechanical (MEMS) switches, the antenna being conductively connected to the signal conductor, the MEMS switches and at least a portion of the signal conductor being supported by a MEMS substrate; and one or more integrated circuits comprising MEMS control circuitry configured to control the said one or more MEMS switches and/or signal processing circuitry configured to process signals received and/or to be transmitted by the antennas of the antenna modules, wherein the antenna modules and integrated circuits are supported by a common carrier substrate comprising the antennas of the antenna modules, the MEMS switches; or the said one or more integrated circuits. A hierarchy of MEMS controllers includes a master MEMS controller and local MEMS controllers which send control signals to a plurality of MEMS switches.

Claims

1. An antenna array comprising: a plurality of antenna modules, each of the antenna modules comprising an antenna, a signal conductor and one or more radio frequency (RF) microelectromechanical (MEMS) switches, the antenna being conductively connected to the signal conductor, the MEMS switches and at least a portion of the signal conductor being supported by a MEMS substrate; and one or more integrated circuits (ICs) comprising one or more MEMS controllers configured to control the said one or more MEMS switches of the antenna modules and/or signal processing circuitry configured to process signals received and/or to be transmitted by the antennas of the antenna modules, wherein the antenna modules and integrated circuit(s) are supported by a common carrier substrate comprising any one or more of the group comprising: the antennas of the antenna modules; the MEMS switches of the antenna modules; and the said one or more integrated circuit(s), wherein the MEMS controllers comprise a plurality of MEMS controllers each of which is configured to control the MEMS switches of a plurality of antenna modules of the array and/or signal processing circuitry configured to process signals received and/or to be transmitted by the antennas of a plurality of antenna modules of the array, and one or more ICs comprises a master MEMS controller and a plurality of local MEMS controllers and wherein the master MEMS controller is configured to control the MEMS switches of the said plurality of antenna modules by providing control signals to the said local MEMS controllers responsive to input target steering directions/phase shifts/signal amplitudes/gains/polarisations to be implemented by the said plurality of antenna modules, wherein the master MEMS controller is configured to receive the said inputs from circuitry external to the array, and one or more MEMS controllers are configured to preload a plurality of registers with control signal data indicative of the next control signal for a respective MEMS switch and to transmit the control signals indicated by the preloaded registers to the MEMS switches responsive to a trigger signal.

2. The antenna array according to claim 1, wherein each local MEMS controller controls a plurality of individual MEMS switches to thereby control the RF signals to be transmitted by the antennas of a plurality of antenna modules of the array.

3. The antenna array according to claim 1, wherein the said ICs comprise a plurality of hierarchial controllers, the hierarchial controllers comprising said master MEMS controller and a plurality of said local MEMS controllers, and the said hierarchial controllers comprise one or more intermediate MEMS controllers which receive instructions from the master MEMS controller and transmit instructions to a plurality of the said plurality of local MEMS controllers, optionally via one or more further intermediate controllers.

4. The antenna array according to claim 1 wherein the common carrier substrate and/or the MEMS substrate(s) comprise or consist of material having a dielectric constant greater than 3, and the MEMS substrate and antenna of each of the said antenna modules are arranged together in a stack comprising the said common carrier substrate.

5. The antenna array according to claim 1 wherein the said one or more ICs comprise signal processing circuitry having any one or more of the group comprising: one or more power amplifiers each of which is configured to amplify RF signals to be transmitted by the antennas of one or more or each of the antenna modules; one or more low noise amplifiers each of which is configured to amplify RF signals received by the antennas of one or more or each of the antenna modules; one or more analogue to digital converters each of which is configured to convert analogue signals received by the antennas of one or more said antenna modules into digital signals; one or more digital to analogue converters each of which is configured to convert digital signals into analogue signals for transmission by the antennas of one or more said antenna modules; and a digital interface configured to interface with external digital circuitry.

6. The antenna array according to claim 1 wherein the said antenna modules each further comprise a capping portion, wherein an enclosed volume is formed around the MEMS switches of that antenna module between the capping portion and at least a portion of the MEMS substrate of that antenna module, and either: (i) the carrier substrate comprises the capping portions of the said antenna modules, or (ii) the capping portions are provided by one or more capping substrates discrete from the carrier substrate, and either: (a) the capping substrate(s) comprise the antennas of the respective antenna modules, or (b) the capping substrate(s) comprise at least part of one or more of the said ICs.

7. The antenna array according to claim 1 further comprising one or more electromagnetic signal dividers and/or combiners each being configured to divide an electromagnetic signal from an RF port between the antennas of a respective two or more of the antenna modules of the array and/or to combine electromagnetic signals received from the antennas of a respective two or more antenna modules of the array to an RF port, and one or more or each of the electromagnetic signal dividers and/or combiners are provided on the common carrier substrate.

8. The antenna array according to claim 7 wherein one or more or each of the electromagnetic signal dividers and/or combiners are provided on the common MEMS substrate.

9. The antenna array according to claim 1 wherein the MEMS substrates of the antenna modules are each part of a shared MEMS substrate common to the antenna modules of the array, and which are discrete from the common carrier, and/or are discrete from each other.

10. The antenna array according to claim 1 wherein the MEMS substrate of each of one or more or each of the antenna modules comprises the said antenna of that antenna module, and the antenna, at least a portion of the signal conductor, and the one or more MEMS switches of one or more antenna modules are formed on the same side of the same MEMS substrate.

11. The antenna array according to claim 1 wherein the antennas of the antenna modules are either provided on a shared antenna substrate common to the antenna modules of the array, or are each provided on respective antenna substrates discrete from each other.

12. The antenna array according to claim 11 wherein the semiconductor IC substrates comprise the antennas of the antenna modules.

13. The antenna array according to claim 1 wherein one or more or each of the said ICs are provided on one or more semiconductor IC substrates discrete from the common carrier substrate, and, when the said one or more semiconductor IC substrates comprise a plurality of respective semiconductor IC substrates, each respective semiconductor IC substrate are discrete from each other, and wherein each of the said semiconductor IC substrates each comprise one or more said ICs.

14. The antenna array according to claim 1 wherein the antennas, the MEMS switches and the ICs are provided on respective antenna, MEMS and semiconductor IC substrates which are discrete from each other.

15. The antenna array according to claim 14 wherein the MEMS substrates have opposing first and second surfaces and the antenna substrates have opposing first and second surfaces, wherein the MEMS switches of each of the antenna modules are provided on the first surfaces of the MEMS substrates and the antennas are formed on the first surfaces of the antenna substrates, and wherein the second surfaces of the MEMS substrates are connected to the second surfaces of the antenna substrates.

16. The antenna array according to claim 14 wherein respective enclosed volumes are formed around the MEMS switches of the antenna modules between the capping portions and at least portions of the respective MEMS substrates.

17. The antenna array according to claim 14 wherein the MEMS substrates are each part of a shared MEMS substrate common to the antenna modules of the array, wherein the antenna substrates are each part of a shared antenna substrate common to the antenna modules of the array and wherein the semiconductor IC substrates are each part of a shared semiconductor IC substrate.

18. The antenna array according to claim 14 wherein the MEMS substrates, antenna substrates and semiconductor IC substrates of each of the said antenna modules are arranged together in a stack.

19. The antenna array according to claim 1 wherein the common carrier substrate either: (i) comprises the antennas of the antenna modules and the said ICs, or (ii) comprises the said ICs and the MEMS substrates of the said antenna modules.

20. The antenna array according to claim 1 wherein the said one or more ICs comprise one or more MEMS controllers, each of which is configured to control the MEMS switches of each of one or more said antenna modules, and the said one or more ICs comprises a plurality of MEMS controllers, each of which is configured to control the MEMS switches of one or more said antenna modules, and a discrete MEMS controller is provided for each said antenna module, the said discrete MEMS controller being configured to control the MEMS switches of the said antenna module.

21. The antenna array according to claim 20 wherein the discrete MEMS controller of each said antenna module is provided on a capping substrate comprising a capping portion wherein an enclosed volume is formed around the MEMS switches of that antenna module between the capping portion and at least a portion of the MEMS substrate of that antenna module, and the said one or more ICs comprises a plurality of discrete MEMS controllers, each of which is configured to control the MEMS switches of a respective plurality of the said antenna modules, and each said MEMS controller is provided on a semiconductor IC substrate comprising a plurality of capping portions wherein respective enclosed volumes are formed around the MEMS switches of the antenna modules the MEMS switches of which the said MEMS controller is configured to control between the respective capping portions and at least portions of the MEMS substrates of those antenna modules.

22. The antenna array according to claim 1 wherein the array of antenna modules comprises a plurality of independent sub-arrays each comprising a respective plurality of the said antenna modules, each of the said independent sub-arrays being configured to communicate with one or more electromagnetic signal sources/receivers independently of the other sub-arrays.

23. The antenna array according to claim 22 wherein each of the said MEMS controllers is configured to control the MEMS switches of the antenna modules of a respective said sub-array.

24. The antenna array according to claim 22 comprising a plurality of electromagnetic signal dividers and/or combiners each being configured to divide an electromagnetic signal from a respective RF port between the antennas of a respective sub-array and/or to combine electromagnetic signals received from the antennas of a respective sub-array to a respective RF port.

25. The antenna array according to claim 1 wherein the MEMS switches of each of the antenna modules comprise one or more capacitive MEMS switches of a reconfigurable MEMS phase shifter configured to adjust a phase of an electromagnetic signal propagating on the signal conductor to or from the antenna of that antenna module and/or one or more MEMS switches of a variable gain attenuator configured to adjust an amplitude of an electromagnetic signal propagating on the signal conductor to or from the antenna of the antenna module and/or one or more MEMS switches of a power amplifier configured to amplify electromagnetic signals to be transmitted by the antenna and/or one or more MEMS switches of a low noise amplifier configured to amplify electromagnetic signals received by the antenna.

26. The antenna array according to claim 25 wherein each of the said MEMS controllers is configured to either: (i) receive as inputs control signals which specify a configuration of the MEMS switches of the said antenna module(s) for implementing a target phase shift and/or steering direction and/or gain and/or signal amplitude, or (ii) receive as inputs target phase shifts and/or a target steering directions and/or a target gains and/or signal amplitudes; and to determine from the said inputs a configuration of the one or more MEMS switches of the antenna module(s) for implementing the required phase shift and/or steering direction and/or gain and/or signal amplitude.

27. A method of manufacturing an antenna array, the method comprising: forming a plurality of antenna modules, each of the said plurality of antenna modules being formed by supporting at least a portion of a signal conductor on a MEMS substrate, supporting one or more RF microelectromechanical (MEMS) switches on the said MEMS substrate, providing an antenna and conductively connecting the antenna to the signal conductor; providing one or more integrated circuits (ICs) comprising one or more MEMS controllers configured to control the said one or more MEMS switches of the antenna modules and/or signal processing circuitry configured to process signals received and/or to be transmitted by the antennas of the antenna modules; and supporting the antenna modules and integrated circuits on a common carrier substrate comprising any one or more of the group comprising: the antennas of the antenna modules; the MEMS switches of the antenna modules; and the said one or more integrated circuits, wherein the MEMS controllers comprise a plurality of MEMS controllers each of which is configured to control the MEMS switches of a plurality of antenna modules of the array and/or signal processing circuitry configured to process signals received and/or to be transmitted by the antennas of a plurality of antenna modules of the array, and one or more ICs comprises a master MEMS controller and a plurality of local MEMS controllers and wherein the master MEMS controller is configured to control the MEMS switches of the said plurality of antenna modules by providing control signals to the said local MEMS controllers responsive to input target steering directions/phase shifts/signal amplitudes/gains/polarisations to be implemented by the said plurality of antenna modules, wherein the master MEMS controller is configured to receive the said inputs from circuitry external to the array, and one or more MEMS controllers are configured to preload a plurality of registers with control signal data indicative of the next control signal for a respective MEMS switch and to transmit the control signals indicated by the preloaded registers to the MEMS switches responsive to a trigger signal.

28. An antenna array comprising: a plurality of antenna modules, each of the antenna modules comprising an antenna, a signal conductor and one or more radio frequency (RF) microelectromechanical (MEMS) switches, the antenna being conductively connected to the signal conductor, the MEMS switches and at least a portion of the signal conductor being supported by a MEMS substrate; and one or more integrated circuits (ICs) comprising one or more MEMS controllers configured to control the said one or more MEMS switches of the antenna modules and/or signal processing circuitry configured to process signals received and/or to be transmitted by the antennas of the antenna modules, wherein the antenna modules and integrated circuit(s) are supported by a common carrier substrate comprising any one or more of the group comprising: the antennas of the antenna modules; the MEMS switches of the antenna modules; and the said one or more integrated circuit(s), wherein the said one or more ICs comprises a plurality of MEMS controllers, wherein a discrete MEMS controller of the plurality of MEMS controllers is provided for each said antenna module, the said discrete MEMS controller being configured to control the MEMS switches of the said antenna module, wherein the discrete MEMS controller of each said antenna module is provided on a capping substrate comprising a capping portion wherein an enclosed volume is formed around the MEMS switches of that antenna module between the capping portion and at least a portion of the MEMS substrate of that antenna module, and each said MEMS controller is provided on a semiconductor IC substrate comprising a plurality of capping portions wherein respective enclosed volumes are formed around the MEMS switches of the antenna modules, the MEMS switches of which the said MEMS controller is configured to control between the respective capping portions and at least portions of the MEMS substrates of those antenna modules.

29. A method of manufacturing an antenna array, the method comprising: forming a plurality of antenna modules, each of the said plurality of antenna modules being formed by supporting at least a portion of a signal conductor on a MEMS substrate, supporting one or more RF microelectromechanical (MEMS) switches on the said MEMS substrate, providing an antenna and conductively connecting the antenna to the signal conductor; providing one or more integrated circuits (ICs) comprising one or more MEMS controllers configured to control the said one or more MEMS switches of the antenna modules and/or signal processing circuitry configured to process signals received and/or to be transmitted by the antennas of the antenna modules; and supporting the antenna modules and integrated circuits on a common carrier substrate comprising any one or more of the group comprising: the antennas of the antenna modules; the MEMS switches of the antenna modules; and the said one or more integrated circuits, wherein the said one or more ICs comprises a plurality of MEMS controllers, wherein a discrete MEMS controller of the plurality of MEMS controllers is provided for each said antenna module, the said discrete MEMS controller being configured to control the MEMS switches of the said antenna module, wherein the discrete MEMS controller of each said antenna module is provided on a capping substrate comprising a capping portion wherein an enclosed volume is formed around the MEMS switches of that antenna module between the capping portion and at least a portion of the MEMS substrate of that antenna module, and each said MEMS controller is provided on a semiconductor IC substrate comprising a plurality of capping portions wherein respective enclosed volumes are formed around the MEMS switches of the antenna modules, the MEMS switches of which the said MEMS controller is configured to control between the respective capping portions and at least portions of the MEMS substrates of those antenna modules.

Description

DESCRIPTION OF THE DRAWINGS

(1) An example embodiment of the present invention will now be illustrated with reference to the following Figures in which:

(2) FIG. 1 is a schematic diagram of an antenna module comprising an antenna conductively connected to a MEMS phase shifter;

(3) FIG. 2 is a schematic sectional view of a capacitive MEMS switch of the MEMS phase shifter of FIG. 1 having a bridge in a first (up) state;

(4) FIG. 3 shows the switch of FIG. 2 with the bridge in a second (down) state;

(5) FIG. 3a is a schematic circuit diagram of a pulse width modulation (PWM) amplifier;

(6) FIG. 3b is a schematic circuit diagram of a PWM amplifier using a capacitive MEMS switch;

(7) FIG. 4 shows the antenna module of FIG. 1 stacked on a semiconductor IC substrate;

(8) FIG. 5 is a schematic view of a portion of a phased antenna array having a plurality of antenna modules as shown in FIGS. 1 to 4 and having a common semiconductor IC substrate which carries the antenna modules of the array;

(9) FIG. 5a is a schematic circuit diagram of a sub-array of the phased antenna array, wherein a single power amplifier and a single low noise amplifier are provided to amplify signals received and/or to be transmitted by antennas of a sub-array of the array;

(10) FIG. 5b is a schematic view of a portion of a similar array to FIG. 5 but with common MEMS and capping substrates;

(11) FIG. 6 shows the array of FIG. 5 together with integrated circuitry offset from the antenna modules;

(12) FIG. 7 is a schematic circuit diagram of a sub-array of the phased antenna array, wherein each of the antennas of the sub-array have individually controllable reconfigurable phase shifters, individually controllable variable gain attenuators, individually controllable power amplifiers and individually controllable low noise amplifiers;

(13) FIG. 8 is a schematic diagram of an alternative phased antenna array to that shown in FIG. 5 wherein the antenna modules have a common antenna substrate which carries the antenna modules of the array (rather than a common semiconductor IC substrate);

(14) FIG. 9 shows a similar phased array to that of FIG. 8 but with discrete interposer caps provided between the MEMS substrates and the carrier substrate;

(15) FIG. 10 shows an alternative antenna module to that of FIGS. 1 to 4 where the semiconductor IC substrate comprises the antenna;

(16) FIG. 11 is a sectional view through the module of FIG. 10;

(17) FIG. 12 is a schematic diagram showing a portion of a phased antenna array having a plurality of the antenna modules of FIG. 10, with the antenna modules of the array having a common semiconductor IC substrate comprising the antennas of the array;

(18) FIG. 13 is a schematic diagram of an alternative antenna module where the antenna is provided on the reverse side of the MEMS substrate from the MEMS switches;

(19) FIG. 14 is a schematic diagram of a portion of a phased antenna array having antenna modules as shown in FIG. 13, with the antenna modules of the array having a common semiconductor IC substrate;

(20) FIG. 14a is a schematic diagram of a portion of a similar array to FIG. 14 but with a common MEMS substrate;

(21) FIG. 14b is a schematic diagram of a similar array to FIG. 14a but with semiconductor IC substrates discrete from each other mounted on the common MEMS substrate;

(22) FIG. 15 is a schematic diagram of a portion of an alternative phased antenna array having antenna modules each of which is made up from a semiconductor IC substrate stacked on and capping a MEMS substrate which is itself stacked on an antenna substrate comprising the antenna, the antenna substrate being a carrier substrate common to all of the antenna modules of the array;

(23) FIG. 16 is similar to FIG. 15 but with discrete interposer caps between the semiconductor IC substrates and the MEMS substrates of the antenna modules;

(24) FIGS. 17 to 20a illustrate a method of manufacturing the antenna modules of FIGS. 1 to 4;

(25) FIG. 21 shows a capping semiconductor IC substrate having an antenna on a top surface thereof;

(26) FIG. 22 shows a MEMS substrate having MEMS switches on a first surface and an antenna on a second surface opposite the first surface;

(27) FIG. 23 shows a semiconductor IC substrate having a cavity;

(28) FIG. 24 is a plan view of a phased antenna array having four sub-arrays the MEMS switches of the antenna modules within each sub-array being controlled by a common integrated circuit;

(29) FIG. 25 is a plan view of a similar phased array to FIG. 24, but with the sub-arrays arranged in a grid;

(30) FIG. 26 is a cross-section through an example embodiment of the invention; and

(31) FIGS. 27 to 30 are schematic diagrams of circuits for operating an embodiment of the invention.

DETAILED DESCRIPTION OF AN EXAMPLE EMBODIMENT

(32) FIG. 1 shows an antenna module 1 of a phased antenna array, the antenna module having a (typically crystalline) semiconductor MEMS substrate (or wafer) 2 having a first surface 4 and a second surface 6 opposite the first surface 4, the first surface 4 supporting an electromagnetic (e.g. RF) signal conductor 14 together with a pair of ground conductors 15 which form a co-planar waveguide with the signal conductor 14 (although it is not necessary for a co-planar waveguide arrangement to provided; any suitable alternative arrangement may be provided, such as a microstrip arrangement in which a microstrip signal conductor 14 is provided on the first surface 4 of the substrate 2), and a plurality of reconfigurable MEMS switches, two of which 16, 18 are shown schematically in FIG. 1.

(33) A first one of the MEMS switches 16 is shown more clearly in section in FIGS. 2 and 3. More specifically, the MEMS switch 16 is a capacitive switch comprising a conductive bridge 24 provided above and extending across the signal conductor 14, the bridge 24 having first and second conductive flexures extending from respective conductive anchors 20, 22 on the first surface 4 of the substrate 2 on either side of the signal conductor 14 where they are fixed (although alternatively the bridge may be cantilevered). A dielectric layer 28 comprising solid dielectric material is provided between the bridge 24 and the signal conductor 14 (in this case the dielectric layer 28 is provided on the signal conductor 14) to prevent a short circuit occurring between them and to provide the switch with the required capacitances. The bridge 24 is moveable by elastic deformation of the flexures between a first (up) relaxed state shown in FIG. 2 in which it is spaced from the dielectric layer 28 provided on the conductor 14 and a second (down) deformed state shown in FIG. 3 in which the bridge 24 engages the dielectric layer 28. The capacitance of the switch is greater in the second (down) state than in the first (up) state.

(34) The MEMS switches 16, 18 comprise a plurality of capacitive MEMS switches of a reconfigurable MEMS phase shifter which helps to control a steering direction of the phased antenna array. By adjusting which of the MEMS switches 16, 18 are in their first states and which are in their second states, the phase of electromagnetic signals propagating on the electromagnetic signal conductor 14 can be adjusted. The capacitive MEMS switches can thus be controlled to individually and selectively adjust the phase of electromagnetic signals propagating on the electromagnetic signal conductor 14. Although only two MEMS switches 16, 18 are shown in FIG. 1, it will be understood that any suitable number of MEMS switches could be employed to achieve phase shifts of a required range and granularity. Indeed, typically, the MEMS substrate 2 supports 127 capacitive MEMS switches in order to provide up to a 360 phase shift with a granularity of around 2.8. In this case, the capacitive MEMS switches of the phase shifter are grouped together to form seven groups of MEMS switches to thereby provide a 7-bit MEMS phase shifter. Specifically, the anchors 22 of respective groups of 64, 32, 16, 8, 4 and 2 different ones of the switches are conductively connected to each other so that applying a DC voltage to the groups of switches provides phase shifts of 181.42, 90.7, 45.35, 22.68, 11.33 and 5.67 respectively. The remaining group comprises a single capacitive MEMS switch which provides a phase shift of 2.83. In this case, seven vias 32 are provided through the MEMS substrate 2 to connect the respective groups to MEMS control circuitry (see below).

(35) The MEMS switches 16, 18 further comprise one or more MEMS switches of a variable gain attenuator configured to attenuate RF signals propagating on the signal conductor 14 to thereby provide individual and selective control of the amplitude of signals transmitted or received by the antenna module 1. The attenuator switches are typically adjacent to the phase shifter switches. The attenuator switches are typically ohmic and may, for example, be similar to the switch 16 described above but omitting the solid dielectric material in the dielectric layer 28 provided between the conductive bridge and the signal line. When the bridge engages the signal line, the length and therefore the impedance of the signal path increases, such that the signal is attenuated. Alternatively, the attenuator switches may be capacitive, in which case they typically have a relatively low capacitance in their off (up) states and a much greater capacitance in their on (down) states such that, when they are in their on (down) states, the capacitance of the switch causes attenuation of the signal. It may be that the attenuator switches cause some phase shift, which can be compensated for by the phase shifter. For example, any phase shift provided by MEMS attenuator switches can be accounted for by actuating fewer or more phase shifter switches in order to achieve a target phase shift and amplitude (or specific gain) for signals received and/or to be transmitted by the antenna module 1.

(36) Each of the switches 16, 18 is actuated electrostatically from the first state to the second state by way of a DC voltage applied to one (or both) of the conductive anchors 20, 22 which causes a DC potential difference to be provided between the flexures of the bridge 24 and the ground conductors 15, thereby causing the flexures to deflect downwards. It will be assumed in the following description that the DC voltage is applied only to anchor 22. The DC voltage is applied to the anchor 22 by way of a conductive through substrate via 32 which extends (fully) through the MEMS substrate 2 from the second surface 6 to the first surface 4 to conductively connect the anchor 22 to MEMS control circuitry (see below with reference to FIG. 4). To move the bridge from the second (down) state to the first (up) state, the DC voltage signal is removed from the anchors 22, and the restoring elastic force of the flexures causes the bridge to move back to the first (up) state.

(37) In some cases, the MEMS switches 16, 18 may additionally or alternatively comprise one or more MEMS switches of a MEMS power amplifier or a MEMS low noise amplifier configured to amplify electromagnetic signals to be transmitted and/or electromagnetic signals received by the antenna module 1. For example, a MEMS power amplifier or a MEMS low noise amplifier may comprise a MEMS amplifier based on the ones described in The MEMSamp: using (RF-)MEMS switches for the microelectromechanical amplification of electronic signals, W Merlijn van Spengen, Sander B Roobol, Wouter P Klaassen and Tjerk H Oosterkamp, J. Micromech. Microeng. 20 (2010) 125011 (van Spengen) which is incorporated herein in full by reference. In this case, the MEMS amplifier is based on the circuit shown in FIG. 3b (which is a generic pulse width modulation based amplifier circuit). The input signal 37a to be amplified is input to a comparator 37b together with a pulse width modulation signal (typically a triangle wave) 37c. The triangle wave 37c causes a switch 37d to be turned on and off at the frequency of frequency of the triangle wave. The switch 37d is connected to a DC power supply 37e through impedance 37f. When the switch 37d turns on and off, a pulse train 37g is generated from the DC power source which has a higher power than the signals provided to the comparator inputs. The (non-zero) input signal 37a causes the moment of switching (and thus the pulse train 37g) to change. The pulse train (with changed moment) is passed through a low pass filter 37h to provide an output 37i, the output 37i having the same frequency and phase but greater amplitude than the input signal 37a.

(38) FIG. 3b shows a similar circuit to that of FIG. 3a. Identical features will be allocated the same reference numerals. In this case, the input signal to be amplified is the signal 37a. A capacitive MEMS switch 37j comprising a conductive bridge which extends over the signal line 14 is provided. The MEMS bridge 24 is moveable between first (up) and second (down) states as described above. Electrodes 37k, 37l, 37o are provided under the bridge 24 of the MEMS switch 37j such that the capacitance between the bridge 24 and the electrodes 37k, 37l, 37o is greater when the bridge 24 is in the second state than when it is in the first state. The bridge 24 is grounded. A dielectric layer comprising solid dielectric material may be provided between the bridge 24 and one or each of the electrodes 37k, 37l, 37o to prevent a short circuit from occurring between the bridge and the electrode(s) (and/or to provide the required capacitance); alternatively, the bridge 24 may be controlled such that an air gap remains between the bridge 24 and the electrodes 37k, 37l, 37o when the bridge is in the second state. Signal 37a is applied to electrode 37l, while the triangle wave 37c described above is combined with a DC bias signal and applied to electrode 37o. A high frequency AC power supply 37m (rather than the DC power supply of FIG. 3a) is connected to the electrode 37k through impedance 37f. When the bridge 24 is in its first (up) state, the voltage at the opposing side of the impedance 37f from the AC power supply 37m is almost equal to that of the AC power supply 37m. When the switch 37j is in its second (down) state, a large fraction of the AC signal will be transmitted through electrode 37k. Thus, movement of the bridge 24 between the first and second states causes amplitude modulation of the AC signal from the power supply 37m. The triangle wave 37c (together with DC bias) applied to electrode 37o causes the bridge to be electrostatically switched up and down at the frequency of the triangle wave, resulting in a train of high frequency AC pulses at the frequency of the triangle wave. The duty cycle of the pulses is determined by the input voltage of the amplifier (i.e. the voltage of the signal 37a). The power in the pulses is determined by the AC voltage 37m, the impedance 37f and the properties of the switch 37j, rather than by the input signal. By rectifying the pulses (by way of diode 37n) and passing them through the low pass filter 37h, an amplified version of the original input signal 37a is provided. Alternative approaches are possible (and indeed described in van Spengen) with metal-to-metal contact MEMS switches.

(39) The MEMS switches 16, 18 are thus configured to individually and selectively adjust the phase (and thus the steering direction) and/or gain and/or signal amplitude of electromagnetic signals propagating on the signal conductor 14.

(40) By providing the signal conductor 14 on a crystalline MEMS substrate, electromagnetic (typically RF) signals propagating on the signal conductor 14 will experience low losses due to the substantially uniform (relatively defect free) structure of the crystalline substrate; this is particularly important at high signal frequencies (e.g. signal frequencies greater than 0.6 GHz, greater than 2 GHz, greater than 5 GHz, greater than 8 GHz, greater than 20 GHz, greater than 50 GHz or greater than 70 GHz). Although it may be that the crystalline MEMS substrate is polycrystalline, it is preferable that the MEMS substrate is monocrystalline or at least that the signal conductor is provided on a monocrystalline surface of the MEMS substrate (or at least the signal conductor is provided in electromagnetic communication with a monocrystalline MEMS substrate or a monocrystalline portion of the MEMS substrate). This is because monocrystalline structures are more uniform, which leads to more uniform propagation of electromagnetic signals over the substrate, thereby keeping signal losses low. In one example, the MEMS substrate 2 is a silicon-on-sapphire substrate comprising a layer of (typically monocrystalline) silicon grown on a (typically monocrystalline) layer of sapphire. In this case, the silicon layer is etched and the signal conductor 14 is formed or deposited on the etched portion, either directly on the sapphire layer (the silicon layer having been etched away) or on a thin (e.g. less than 5 m, less than 3 m, typically 1-2 m thick) layer of silicon provided over the sapphire such that the signal conductor 14 is in electromagnetic communication with the sapphire portion of the substrate. In this way, the signal conductor 14 obtains the benefit of the sapphire portion of the substrate (which is less lossy than silicon at higher signal frequencies), even if a thin layer of silicon remains between the signal conductor 14 and the sapphire portion.

(41) A MEMS controller is provided by an Integrated (typically complementary metal oxide semiconductor (CMOS)) Circuit (IC) 49 and is configured to control the states of the MEMS switches 16, 18. In the embodiment shown in FIG. 4 (which otherwise has the same structure as the arrangement of FIG. 1; common features are allocated the same reference numerals), the integrated circuit 49 is provided on a semiconductor (and semiconducting) integrated circuit (IC) substrate (or wafer) 50 stacked on and bonded to the second surface 6 of the MEMS substrate 2. The semiconductor IC substrate 50 has a first surface 52 bonded to the second surface 6 of the MEMS substrate 2 and a second surface 54 opposite the first surface 52 and the integrated circuit 49 is formed on the second surface 54. By stacking the semiconductor IC substrate 50 on the MEMS substrate 2, a compact arrangement is provided which saves cost, space and keeps the lengths of the conductive connections between the integrated circuit and the MEMS switches 16, 18 short. This allows control signals to be routed from the MEMS controller to the respective MEMS switches 16, 18 (in order to implement a target phase shift and/or steering direction and/or gain and/or signal amplitude) by way of conductive through substrate vias 58, 32 which together extend through the semiconductor IC substrate 50 and the MEMS substrate 2 between the MEMS controller and the DC anchors 22 of the respective groups of MEMS switches.

(42) It may be that the MEMS controller receives as an input control signals 59 from circuitry 62 which specify which of the MEMS switches 16, 18 (or groups of MEMS switches) should be in their first (up) states and which of the MEMS switches 16, 18 (or groups of MEMS switches) should be in their second (down) states in order to achieve a target phase shift and/or steering direction and/or gain and/or signal amplitude. It may be that the circuitry 62 is external to the array. The MEMS controller is required to interface with circuitry 62 (e.g. by way of an industry standard interface such as an industry standard RF Front End (RFFE) interface or Serial Peripheral Interface (SPI) etc.) to receive control signals for controlling the MEMS switches 16, 18, boost the system voltage (e.g. 3.3V) to a higher DC voltage (e.g. 30V or 40V) required for actuation of the MEMS switches (which is typically done using one or more charge pumps of the controller or the combination of one or more charge pumps of the controller and one or more energy storage elements (e.g. capacitors) which may or may not be provided in the same integrated circuit as the controller and may or may not be on the same substrate as the controller) and route the boosted, relevant control signals to the correct MEMS switches 16, 18 or groups of MEMS switches to implement the determined configuration (typically comprising setting one or more bits of the 7-bit phase shifter to digital 0 (no DC bias) and one or more bits of the phase shifter to digital 1 (DC bias applied)). In this case, the determination of which switches 16, 18 should be in which states is performed in circuitry 62 responsive to a target phase shift and/or steering direction and/or gain and/or signal amplitude.

(43) In other embodiments, it may be that the circuitry 62 is part of the MEMS controller which in this case is also configured to receive as inputs target phase shifts and/or steering directions and/or gains and/or signal amplitudes to be applied by the MEMS switches 16, 18 of the antenna module 1 (e.g. from circuitry external to the array) and to determine from the inputs configurations of the MEMS switches needed to implement the required phase shift and/or steering direction and/or gain and/or signal amplitude.

(44) In either case, one MEMS controller may be provided per antenna module. Alternatively, one MEMS controller may be provided per sub-array of antenna modules. In one embodiment, one MEMS controller may be provided per four antenna modules (e.g. 22 sub-array). In another embodiment, one MEMS controller may be provided for all of the antenna modules of the array. In one embodiment, one MEMS controller may be provided for sixteen antenna modules (e.g. 44 array). In embodiments where one MEMS controller is provided for a plurality of antenna modules, it may be that the controller requires one or more additional charge pump(s) and/or one or more larger storage element(s) may need to be provided to enable the controller to boost the system voltage for each of the plurality of antenna modules, but typically one or more of the same charge pump(s) and/or storage elements may be re-used for the MEMS switches of a plurality of the antenna modules.

(45) In another alternative it may be that the MEMS controller provided by integrated circuit 49 is a local MEMS controller and the circuitry 62 comprises a master MEMS controller of the array, the master MEMS controller being configured to control the local MEMS controller. In this case, the master MEMS controller is typically configured to receive as inputs target phase shifts and/or steering directions and/or gains and/or signal amplitudes to be applied by the MEMS switches 16, 18 of the antenna module 1 (e.g. from circuitry external to the array), to determine from the inputs configurations of the MEMS switches needed to implement the required phase shift and/or steering direction and/or gain and/or signal amplitude, and to apply signals to the local controller 49. In this case, the local controller is required to interface with circuitry 62 (e.g. by way of an industry standard interface such as an industry standard RF Front End (RFFE) interface or Serial Peripheral Interface (SPI) etc.) to receive control signals for controlling the MEMS switches 16, 18, boost the system voltage (e.g. 3.3V) to a higher DC voltage (e.g. 30V or 40V) required for actuation of the MEMS switches (which is typically done using one or more charge pumps of the local controller or the combination of one or more charge pumps of the local controller and one or more energy storage elements (e.g. capacitors) which may or may not be provided in the same integrated circuit as the local controller and may or may not be on the same substrate as the local controller) and route the boosted, relevant control signals to the correct MEMS switches 16, 18 or groups of MEMS switches to implement the determined configuration (typically comprising setting one or more bits of the 7-bit phase shifter to digital 0 (no DC bias) and one or more bits of the phase shifter to digital 1 (DC bias applied)).

(46) A plurality of local controllers may be provided, each being configured to control the states of the MEMS switches of a respective one or more of the antenna modules of the array (e.g. each local controller may be configured to control the states of the MEMS switches of any of: a respective one of the antenna modules of the array; a plurality of antenna modules of the array; the antenna modules of a sub-array; all of the antenna modules of the array; four antenna modules of the array; and sixteen antenna modules of the array). In this case, only the master MEMS controller is (and not the local controllers are) required to communicate with circuitry external to the array, and each of the local controllers can be relatively simple. In addition, the master MEMS controller can receive as inputs target phase shifts and/or steering directions and/or gains and/or signal amplitudes to be applied by the MEMS switches 16, 18 of each of a plurality of antenna modules 1 of the array (e.g. all of the antenna modules of the array) and to determine from the inputs configurations of the MEMS switches of the plurality of antenna modules to implement the required phase shifts and/or steering directions and/or gains and/or signal amplitudes, and to apply signals to the local controllers 49 to implement the determined configurations (typically comprising setting one or more bits of the 7-bit phase shifter to digital 0 (no DC bias) and one or more bits of the phase shifter to digital 1 (DC bias applied)). This helps reduce complexity and cost.

(47) In embodiments having a master MEMS controller and local MEMS controllers, instead of (or in addition to) the local MEMS controllers comprising the said charge pump(s) and/or the combination of the said charge pump(s) and energy storage element(s), it may be that the master MEMS controller comprises the said charge pump(s), or charge pump(s) and energy storage element(s). In this case, one or more of the charge pump(s) and, where provided, one or more of the energy storage element(s) can be re-used between a plurality of antenna modules. It will be understood that larger energy storage elements and/or additional charge pumps may required than, for example, embodiments in which the system voltage boosting is performed by local controllers provided for individual antenna modules to enable the master controller to boost the system voltage for each of the antenna modules. Alternatively, it may be that the master controller does not comprise charge pumps.

(48) It may be that the MEMS controller 49 comprises a memory 49a and a (e.g. analogue or digital) processor or control logic 49b. In this case, it may be that the memory 49a includes a look-up table specifying a plurality of MEMS switch configuration data portions each of which is associated with a respective phase shift and/or steering direction and/or gain and/or signal amplitude. The MEMS switch configuration data portions provide control data for selectively causing the respective MEMS switches 16, 18 (or groups thereof) to be in their first or second states in order to implement the phase shift and/or steering direction and/or gain and/or signal amplitude with which the respective configuration data portion is associated. Accordingly, the processor or control logic 49b (which is in communication with the memory 49a) receives the target phase/steering direction/gain and/or signal amplitude inputs and selects one or more configuration data portion(s) associated with the inputs (e.g. a first configuration data portion to implement the phase shift a second configuration data portion to implement the signal gain, or a single configuration data portion to implement the phase shift and the signal gain). The processor (or control logic) 49b then outputs signals to the MEMS switches 16, 18 derived from or specified by the configuration data portion(s) by way of the vias 58, 32 in order to implement the target phase shift.

(49) In another example, the memory 49a includes computer program instructions for implementing one or more algorithms for determining a MEMS switch configuration for achieving a target phase shift and/or a target steering direction and/or a target gain and/or signal amplitude based on inputs 59 specifying the target phase shift and/or steering direction and/or target gain and/or signal amplitude and for generating control signal data portions for routing to the MEMS switches 16, 18 to implement the MEMS switch configuration. In this case, the processor or control logic 49b is configured to receive the target phase shift and/or steering direction and/or target gain and/or signal amplitude inputs 59, retrieve the computer program instructions from the memory 49a, and run the computer program instructions together with the inputs 59 to determine and implement (by outputting to the respective DC anchors 22) the switch configuration. The algorithm may for example comprise the steps of receiving a target phase shift and/or steering direction and/or target gain and/or signal amplitude, retrieving data (e.g. from the memory) indicative of the phase shifts and/or signal gains provided by each of the MEMS switches 16, 18 (or by the respective groups of MEMS switches), and determining configurations of the MEMS switches to achieve the target phase shift and/or steering direction and/or target gain and/or signal amplitude taking into account the retrieved data. The algorithms typically further comprise generating control data for implementing the configuration; and outputting signals to the respective MEMS switches 16, 18 (or groups of MEMS switches) in accordance with the control data to implement the target phase shift and/or steering direction and/or target gain and/or signal amplitude.

(50) The memory 49a may additionally or alternatively include computer program instructions for implementing one or more algorithms for determining a MEMS switch configuration for improving signal quality or for tracking and/or locking on to a particular electromagnetic signal, e.g. from a cellular mobile wireless telecommunications base station or a small, micro or femto cell infrastructure, or wireless backhaul, transmitter, receiver or transceiver or a portable mobile wireless telecommunications device, based on feedback (e.g. link quality, quality of service, received signal strength) provided to the controller. For example the controller may be configured to perform a fine tuning scan (i.e. by fine tuning the direction of the beam, e.g. by changing one or more phase shifts of signals received and/or to be transmitted by the antennas and/or by adjusting the signal gains applied to signals received and/or to be transmitted by the antennas, e.g. by signal attenuators or signal boosting amplifiers)) to improve the connection if the connection has fallen below a first quality threshold (or to perform a wider tuning scan to improve the connection if the connection has fallen below a second quality threshold). In another example, the controller may be configured to increase one or more signal gains (e.g. by one or more power amplifiers or one or more low noise amplifiers) or reduce signal attenuation by one or more attenuators. This helps to increase the scanning range which can be beam formed (or steered) by adjusting the phases of the signals received and/or to be transmitted by the antennas of the array, which can reduce the magnitudes of one or more grating lobes and boost the gain of the signal (e.g. the main beam) received and/or to be transmitted by the antennas. Increasing signal gain can therefore maintain the wireless connection at a desired quality level (which may be variable depending on circumstances, such as the type of service being provided, the provider, atmospheric conditions and so on).

(51) It may be that the memory 49a also comprises actuation and hold DC voltage values for the MEMS switches, the actuation voltage being the DC voltage which needs to be applied to the switch to cause the bridge to move from a first state to a second state and the hold voltage being the DC voltage required to hold the bridge in the second state. The hold voltage is typically less than the actuation voltage. It may be that the processor or control logic 49b is configured to reduce the DC voltage applied to one or more MEMS switches from the actuation voltage to the hold voltage after the switch(es) has (have) been actuated from the first state to the second state. This reduces charging effects and increases the reliability of the MEMS bridges of the switches by reducing or eliminating the possibility for stiction due to charging.

(52) In alternative embodiments, the master MEMS controller comprises the memory storing the look-up table and/or algorithms. In this case, the master MEMS controller is configured to determine the configurations of the MEMS switches of the antenna modules using the look-up table and/or algorithms.

(53) The MEMS switches 16, 18 are enclosed in a volume between the first surface 4 of the MEMS substrate 2 and a first surface 33 of a capping portion of a capping substrate (or wafer) 34 (which is a monolithic semiconductor substrate in this example, but may alternatively be a laminate or ceramic substratee.g. a low temperature co-fired ceramic (LTCC) substrate or high temperature co-fired ceramic (HTCC) substrateorganic or multi-layer organic substrate (such as a multi-layer organic substrate from Rogers Corporation), a glass substrate, a ceramic substrate, a glass ceramic substrate or an insulating substrate such as an alumina substrate) which is stacked on and bonded to the MEMS substrate 2. The MEMS switches 16, 18 are thus provided between the capping portion of the capping substrate 34 and the MEMS substrate 2. The MEMS substrate 2 is sandwiched between the semiconductor IC substrate 50 and the capping portion of the capping substrate 34. The first surface 33 of the capping substrate 34 is provided with a cavity 36 which ensures that the bridges of the MEMS switches 16, 18 can (selectively) move between their first and second states unimpeded. It may be that the cavity comprises conductive tracks configured to route signals (e.g. to and/or from one or more integrated circuits, to and/or from the antenna (see below), to and/or from the signal conductor, or to and/or from the MEMS switches). The capping substrate 34 comprises end portions 34a, 34b at opposite ends of the cavity (and which align with ends 10, 12 of the MEMS substrate 2) which enclose the cavity 36. A hermetic seal is provided between the MEMS and capping substrates 2, 34. The enclosed volume between the MEMS substrate 2 and the capping substrate 34 is either evacuated to close to a vacuum or (in some cases preferably) it is filled with nitrogen (or an inert gas) at atmospheric pressure. By filling the volume with nitrogen at atmospheric pressure, the probability of a leak occurring in the seal is reduced because there is a lower pressure differential across it. The capping substrate 34 protects the MEMS switches 16, 18. Alternatively, it may be that the enclosed volume between the capping portion and the MEMS substrate is at a pressure intermediate vacuum and atmospheric pressure (e.g. between 10% and 90% of atmospheric pressure, e.g. between 25% and 75% of atmospheric pressure, e.g. substantially 50% of atmospheric pressure) in order to reduce seal leakage (as compared to vacuum pressure) and to increase switching speed (as compared to atmospheric pressure) of the MEMS switches 16, 18.

(54) The capping portion of the capping substrate 34 has a second surface 38 opposite the first surface 33. The second surface 38 of the capping portion of the capping substrate 34 carries an antenna 40 (which is formed thereon and) which is conductively connected to the signal conductor 14 by way of a conductive through substrate via 42 which extends (fully) through the capping portion of the capping substrate and a conductive pillar 43 (aligned with via 42) provided on a first (fronti.e. adjacent to the antenna) end of the signal conductor 14. Via 42 and pillar 43 carry radio frequency signals between the antenna 40 and the signal conductor 14. A further conductive through substrate via 44 is conductively connected to a second (backi.e. further from the antenna than the said front end) end of the signal conductor 14 in order to carry RF signals to or from the signal conductor 14, the via 44 extending (fully) through the MEMS substrate to a further through substrate via 45 extending through the semiconductor substrate 50 and being conductively connected to the via 44 for receiving or outputting RF signals. The first surface 33 of the capping substrate 34 comprises a ground plane for the (typically patch-type) antenna 40, although typically an insulating portion is provided around the vias extending through the capping substrate to avoid them shorting to the ground plane.

(55) By providing the antenna 40 on the capping substrate 34, the antenna, signal conductor and MEMS switches 16, 18 are provided close together in a compact arrangement, thereby keeping the lengths of signal propagation paths short, thus keeping parasitic and signal losses low. There is also no need for a separate cap for the MEMS switches 16, 18; this reduces material costs and helps to reduce the quantity of processing required during manufacture, thereby helping to reduce the overall cost of the antenna module 1.

(56) It will be understood that, instead of the MEMS switches and the MEMS controller being provided on different substrates stacked on top of each other, they may alternatively be manufactured on (e.g. different layers of) the same substrate.

(57) As indicated above, the antenna module 1 is typically provided as part of a (typically MIMO) phased antenna array, such as the phased antenna array 100, a portion of which is shown in FIG. 5. Although the array 100 shown in FIG. 5 is typically a 44 array comprising sixteen antennas, only a 22 portion of the array is shown, each antenna being provided as part of an antenna module 1 as shown in FIG. 4. The phased antenna array 100 may in turn be provided in a wireless electromagnetic signal communications device, such as a cellular mobile wireless telecommunications base station or a small, micro or femto cell infrastructure, or wireless backhaul, transmitter, receiver or transceiver or a portable mobile wireless telecommunications device. The relative phases of electromagnetic signals received or to be transmitted by respective antennas of the array are individually and selectively controlled by the phase shifters of the antenna modules 100 to effectively steer the antennas in one or more desired directions. Similarly, the amplitudes of electromagnetic signals received and/or to be transmitted by the antennas of the array are individually and selectively controlled by the MEMS attenuator switches and/or the MEMS switches of the power/low noise amplifiers of the antenna modules (where provided). By providing selective individual control of the phase and amplitude of signals received and/or to be transmitted by each antenna of the array, accurate and fine control over the directionality of combinations of the antennas by beamforming is provided. As the power control (either attenuation or amplification) is provided by MEMS switches, low noise, broadband performance is achieved.

(58) As shown in FIG. 5 (where the ground conductors 15 are omitted for clarity), the semiconductor IC substrate 50 is a common carrier substrate comprising the integrated circuits 49 (which in this embodiment comprises individual integrated circuits 49 for each antenna module) and supporting (carrying) the MEMS substrates 2 and the capping substrates 34 of each of the antenna modules 1 of the array, the MEMS and capping substrates 2, 34 of each module 1 being discrete from the other antenna modules. In embodiments comprising a master MEMS controller controlling local MEMS controllers (as discussed above), the master MEMS controller is typically formed on the common carrier substrate 50 and is provided in electrical communication with the local MEMS controllers by way of signal tracks supported by (and typically formed on) the common carrier substrate 50. The discrete MEMS substrates 2 are stacked on the carrier substrate 50 and the discrete capping substrates 34 are stacked on the MEMS substrates 2 of the respective modules.

(59) In order to make the MEMS substrate 2, MEMS switches 16, 18 and signal conductor 14 as small and as close together as possible, the MEMS substrate 2 may comprise or consist of material with a (relatively high) dielectric constant (Er) greater than 3, more preferably greater than 5, such as Gallium Nitride (Er=9.7), more preferably greater than 10, such as Silicon (Er=11.7), Sapphire (Er=9.5-12), Gallium Arsenide (Er=12.9) or Zircon (Er=10-12), and in some cases greater than 20, such as Tantalum Oxide (Er=27), Zirconium Oxide (Er=24.7), Hafnium Oxide (Er=40), PZT (Er=300 to 3850), barium titanate (Er=130 to 1000), lead titanate (Er=200 to 400), Tungsten oxide (Er=42), Lanthanum Oxide (Er=20.8) or borosilicate glass (such as Schott MEMpax (Er=4.8), Schott Borofloat or Schott D263 (Er=6.7)). By using material with a high dielectric constant, the electrical (and thus the physical) length of conductive structures formed thereon can be kept low, while structures can also be provided closer together, thereby helping to keep parasitic and signal losses low. It may be that the MEMS switches 16, 18 are formed directly on the said material with the high dielectric constant; alternatively, it may be that the MEMS switches 16, 18 are formed on a relatively thin layer of another (typically crystalline) material provided on the said high dielectric material (e.g. silicon on sapphire). The capping substrate 34 may also comprise or consist of material having a high dielectric constant, even though it may reduce the antenna efficiency. This can be beneficial because a substrate with a higher dielectric constant allows more complex structures to be formed thereon. In some embodiments, the MEMS substrate comprises a semiconductor substrate, a glass substrate, a ceramic substrate or a glass ceramic substrate.

(60) The antennas 40 of the array 100 are connected together to form a plurality of independent sub-arrays of antenna modules 1 configured to wirelessly communicate with different external electromagnetic signal sources/receivers independently from each other (e.g. along different paths), or with (e.g. respective different sub-arrays of) the same external signal sources/receivers along different paths. As shown in FIG. 5 an electromagnetic signal divider and/or combiner 70 is formed on and supported by the first surface 52 of the carrier substrate 50, the electromagnetic signal divider and/or combiner 70 being configured to divide an (typically RF) electromagnetic signal from an RF port 74 between a plurality of antenna modules 1 of the array 100 and/or to combine electromagnetic signals received from a plurality of antenna modules of the array to the RF port 74. The said plurality of antenna modules of the array are typically the antenna modules of a respective sub-array, with respective electromagnetic signal dividers and/or combiners and RF ports 74 being provided for each sub-array. In each case, the electromagnetic signal divider and/or combiner 70 comprises a plurality of conductive branches 72 each of which connects to the signal conductor 14 of a respective antenna module 1 by way of respective through vias 44, 45. The conductive branches 72 link to the RF port 74 which carries electromagnetic signals to and from the carrier substrate 50 by way of a surface mount connection (e.g. land grid array). The electromagnetic signal divider and/or combiner 70 is provided on the first surface 52 of the semiconductor IC substrate (i.e. on the same surface that the MEMS substrates of the antenna modules 1 are stacked), thereby avoiding the need to route electromagnetic signals through the carrier substrate which could lead to undesirable signal losses. A ground plane for the electromagnetic signal divider and/or combiner 70 is typically provided on the second surface 54 of the carrier substrate 52.

(61) The semiconductor IC substrate 50 typically further comprises (typically analogue, typically RF) integrated (typically semiconductor) signal processing circuitry (e.g. comprised in or adjacent to the integrated circuits 49, or in other integrated circuitry formed elsewhere on the semiconductor IC substrate 50e.g. laterally offset from the antennas 40 and/or the MEMS switches 16, 18) configured to process signals received and/or to be transmitted by the antennas 40. Typically the signal processing circuitry comprises transmitter, receiver or transceiver circuitry. For example, the signal processing circuitry may comprise any one or more of: one or more semiconductor (e.g. CMOS) phase shifters (e.g. as an alternative to implementing the phase shifters in MEMS as described above) configured to individually and selectively adjust the phase of electromagnetic signals received and/or to be transmitted by each of the antennas of the array; one or more semiconductor (e.g. CMOS) attenuators (e.g. as an alternative to implementing the attenuators in MEMS as described above) configured to individually adjust the amplitudes of electromagnetic signals received and/or to be transmitted by each of the antennas of the array; one or more semiconductor power amplifiers configured to (e.g. individually) adjust the power amplification of electromagnetic signals to be transmitted by the antennas of the array; one or more semiconductor low noise amplifiers configured to (e.g. individually) adjust the power amplification of electromagnetic signals received by the antennas of the array; mixed signal circuitry such as an analogue to digital converter (ADC) configured to convert analogue signals received by the antennas to digital signals or a digital to analogue converter (DAC) configured to convert digital signals into analogue signals to be transmitted by the antennas; a digital interface configured to interface with (e.g. receive commands from) external digital circuitry (e.g. such as an overall system processor or controller); and one or more RF filters configured to filter signals received and/or to be transmitted by each of the antennas 40. The signal processing circuitry is electrically connected to the back end of the signal conductor 14 by vias 44, 45.

(62) FIG. 5a is a schematic circuit diagram of an example sub-array configured in an hybrid beam forming architecture in which a single semiconductor power amplifier 105a and a single semiconductor low noise amplifier 105b are provided for the sub-array. Individual and selective control of the amplitudes of RF signals received and/or to be transmitted by the antennas 40 is achieved by the respective variable gain MEMS attenuators 104 (implemented by MEMS switches 16, 18 of each respective antenna module as discussed above). The MEMS phase shifters 102 (comprising reconfigurable MEMS capacitive switches as described above) provide individual and selective control of the phases of electromagnetic signals received and/or to be transmitted by each of the antennas 40. In addition, a digital to analogue converter (DAC) is provided between the low noise amplifier 105b and digital interface circuitry 112 configured to interface with external digital circuitry (e.g. digital circuitry not supported by the common substrate, such as baseband circuitry). An analogue to digital converter 108 is provided between the said digital interface circuitry 112 and the power amplifier 105a. A transmission/reception selection switch 103 is provided between the phase shifters 102/attenuators 104 and the amplifiers 105a, 105b, the switch 103 selecting one of a transmission mode and a reception mode. In the transmission mode, the combination of the ADC and power amplifier is selected so as to convert digital signals from the digital interface 112 into an amplified analogue signal for transmission by the antennas. In the reception mode, the combination of the DAC and the low noise amplifier is selected to amplify analogue signals received by the antennas and to convert them to digital signals for further processing. A similar arrangement may be provided for each sub-array of the array. Alternatively, a single power amplifier and low noise amplifier 105a, 105b (and/or ADC and/or DAC and/or interface) may be provided to serve all of the antennas of the array 100 in an analogue beam forming architecture. The signal processing circuitry may further comprise other RF components (e.g. RF front end components) not shown in FIG. 5a such as RF filters (which are typically common to the antennas 40 of each sub-array, but may alternatively be common to all of the antennas 40 of the array or individual to specific antennas of the array).

(63) FIG. 7 is a schematic circuit diagram of an example sub-array configured in an alternative digital beam forming architecture in which one variable gain power amplifier 105a is provided per antenna module 1 of the (e.g. 44) sub-array and one variable gain low noise amplifier 105b is provided per antenna module 1 of the sub-array. In this case, the individual power and low noise amplifiers are typically MEMS based amplifiers as discussed above; alternatively, they may be semiconductor amplifiers formed on the semiconductor IC substrate 50. By providing individual power amplifiers 105a/low noise amplifiers 105b, more specific control is provided over the power of electromagnetic signals received and/or to be transmitted by the individual antennas 40 (as compared to having a single power amplifier/low noise amplifier for the sub-array or for the entire array), although it will be appreciated that having a variable gain attenuator 104 for each antenna module 1 also provides some specific control (independently from the power amplifier/low noise amplifier) over the amplitudes of signals received and/or to be transmitted by the individual antennas 40. Individual control of the signal amplitudes transmitted and/or received by the antennas 40 of the array provides finer and more accurate control over the directionality of combinations of antennas by beamforming. By implementing this control by way of MEMS amplifiers, lower noise and broader band performance can be achieved. Although FIG. 7 shows both individual attenuators and individual power amplifiers/low noise amplifiers per antenna module, the individual attenuators may in this case be omitted, given that individual (and selective) power control is provided by the individual power amplifiers/low noise amplifiers. As shown in FIG. 7, separate transmission/reception switches 103 are provided per antenna module 1 of the sub-array to select whether the combination of the ADC 108 and power amplifier 105a is selected (transmission mode) or whether the combination of the DAC 110 and the low noise amplifier 105b are selected. The said multiple transmission/reception switches may be replaced by a single transmission/reception switch configured to control which said combination is selected for each antenna module of the sub-array.

(64) Individual analogue to digital converters and digital to analogue converters 108, 110 may be provided per antenna module (FIG. 7), or per sub-array (FIG. 5a), or single analogue to digital converters and digital to analogue converters 108, 110 may serve the entire array (analogue architecture). Similarly, RF filters may be provided for each antenna module (digital architecture), or per sub-array (hybrid architecture), or one may be provided for the entire (e.g. 44 or 1616) array (analogue architecture).

(65) To transmit signals, digital signals are provided to the digital interface circuitry 112 from which they are passed to the digital to analogue converter 110 (the transmission/receive switch(es) 103 being configured in transmit mode). After the signals are modulated (which may be done digitally or in analogue) the modulated signal is passed to the power amplifier(s) 105a which amplifies the modulated signal and passes it to the respective signal conductors 14 on the MEMS substrates 2, typically by way of through substrate vias 44, 45. In embodiments comprising a single power amplifier 105a per sub-array (FIG. 5a), the electromagnetic signal is divided between the antenna modules 1 of the sub-array after it has been amplified by the power amplifier 105a; in embodiments in which individual power amplifiers 105a are provided for each antenna module 1 (FIG. 7), the electromagnetic signal is divided between the antenna modules 1 prior to amplification by the respective power amplifiers 105a. Next the amplified signals propagate down the respective signal conductors 14 where they are phase shifted and/or attenuated and/or amplified and passed towards through substrate vias 42 which feed the signals to the antennas 40 for transmission. To receive signals, RF signals are detected by the antennas 40 which transfer the RF signal to the signal conductors 14 on the MEMS substrates 2 by way of through substrate vias 42 and pillars 43 (with the transmission/reception switch(es) 103 in receive mode). The RF signals propagate along the signal conductors 14 where they are phase shifted and/or attenuated and/or amplified by the MEMS switches 16, 18 and passed to the low noise amplifier(s) 105b. In embodiments comprising a single low noise amplifier 105b per sub-array, the electromagnetic signals received by the antennas 40 of the sub-array are combined prior to amplification by the low noise amplifier 105b; in embodiments in which individual low noise amplifiers 105b are provided for each antenna module 1, the electromagnetic signals received by each of the antennas of the sub-array are amplified by the respective low noise amplifiers prior to being combined. The combined amplified signal is then demodulated and converted to a digital signal in an analogue to digital converter 108 and passed to the digital interface circuitry 112 for further processing.

(66) FIG. 5b shows a similar phased antenna array to FIG. 5, but in this case the MEMS switches 16, 18 and signal and ground conductors 14, 15 of each antenna module of the array are supported by and formed on a shared common MEMS substrate 2. Similarly, the capping portions of each of the antenna modules of the array are provided by a shared common capping substrate 34. Ground conductors 15 and MEMS switches 16, 18 (although present) are not shown in FIG. 5b for clarity. The common MEMS substrate 2 is stacked on the carrier semiconductor IC substrate 50, while the common capping substrate 34 is stacked on the common MEMS substrate 2. The electromagnetic signal divider and/or combiner 70 is in this case provided on the first surface 4 of the MEMS substrate 2, the electromagnetic signal divider and/or combiner being connected to an RF input and/or output pad by way of conductive through substrate vias 99a, 99b which together extend through the MEMS substrate 2 and the semiconductor IC substrate 50. A ground plane for the electromagnetic signal divider and/or combiner is provided on the second surface 6 of the common MEMS substrate 2 (opposite the first surface 4 on which the MEMS switches are provided). Typically the electromagnetic signal divider and/or combiner 70 is electrically isolated from the antenna ground plane provided on the second surface 33 of the capping substrate 34. This may be done by providing an insulating layer between the antenna ground plane and the electromagnetic signal divider and/or combiner.

(67) The electromagnetic signal divider and/or combiner 70 may alternatively be provided on the second surface 6 of the MEMS substrate 2, in which case it may be conductively connected to the signal conductors 14 by way of through substrate vias extending through the MEMS substrate 2. In this case, it may be that the antennas 40 and the electromagnetic signal divider and/or combiner 70 share a common ground plane provided on the first surface 33 of the capping substrate 34. As another alternative, the electromagnetic signal divider and/or combiner 70 may be provided on the second surface 38 of the capping substrate 34 (i.e. on the same surface as the antennas 40). In this case, the electromagnetic signal divider and/or combiner 70 is typically conductively connected to the signal conductors 14 by way of through substrate vias extending through the capping substrate and again the antennas and divider/combiner share a common ground plane (e.g. provided on the first surface 33 of the capping substrate 34).

(68) As another alternative to the embodiment of FIG. 5b, the MEMS substrate 2 is flipped so that the semiconductor IC substrate 50 provides the caps over the MEMS switches 16, 18 and the second surface 6 of the MEMS substrate 2 engages the ground plane on the bottom surface of the antenna substrate 34 (which would typically not comprise cavities in this case). In this case, within each of the antenna modules, the via 42 extends fully through the antenna substrate 34 and an insulating gap is provided in the ground plane so that the antenna 40 is not shorted to the ground plane. A further through via extends through the MEMS substrate to the signal conductor 14, the said further through via being conductively connected to thevia 42 to thereby connect the antenna 40 to the signal conductor 14. The semiconductor IC substrate 50 in this case comprises cavities to form enclosed volumes around the MEMS switches. The electromagnetic signal divider and/or combiner 70 may still be provided on the first surface 4 of the MEMS substrate 2. The antennas 40 and divider/combiner may share a common ground plane provided on the second surface 6 of the MEMS substrate 2 or on the first surface 33 of the antenna substrate 34. In this arrangement, discrete semiconductor IC substrates 50 (comprising respective MEMS controllers) may instead be provided for each antenna module (instead of a common IC substrate) or discrete semiconductor IC substrates 50 may be provided for each sub-array (each comprising a MEMS controller configured to control the MEMS switches of the antenna modules of the sub-array). Alternatively, the discrete (i.e. discrete to the sub-arrays or to the individual antenna modules) semiconductor IC substrates 50 may be mounted or formed on the common MEMS substrate 2 (typically spaced laterally from the MEMS switches and connected thereto by patterned signal tracks). In this case, either a common interposer cap or discrete interposer caps may be provided to form respective enclosed volumes around the MEMS switches.

(69) As shown in FIG. 6, signal processing circuitry which is common to the antenna modules of a sub-array (e.g. power amplifier(s), low noise amplifier(s), analogue to digital converter, digital to analogue converter, interface, filters) may be provided in integrated circuitry 101 formed on the common carrier semiconductor substrate 50 between connection 74 and the electromagnetic signal divider and/or combiner 70. In the example of FIG. 6 the integrated circuitry 101 is laterally offset from the antenna modules 1 of the array 100. Respective said integrated circuitry 101 is typically provided for each sub-array of the array 100. As indicated above, in other embodiments, the same integrated circuitry 101 may serve all of the sub-arrays of the array. The integrated circuitry 101 may comprise a master MEMS controller configured to control a plurality of local MEMS controllers specific to the respective antenna modules as discussed above.

(70) FIG. 8 shows an alternative array 118 to that shown in FIGS. 5, 6 in which the capping substrate 34 is the carrier substrate rather than the semiconductor IC substrate 50. In this case, the capping substrate 34 has respective capping portions which form the hermetically sealed enclosed volumes together with the MEMS substrates 2 which enclose the MEMS switches 16, 18 in the antenna modules 1. In the example illustrated in FIG. 8, the antennas 40 are provided on the second surfaces 38 of the capping portions of the capping substrate 34. However, the antennas 40 could alternatively be (laterally) offset from the capping portions on the capping substrate 34. For example, it may be that the antennas are patch type antennas, which require ground conductors to be provided directly underneath them; in this case, the capping portion and the MEMS switches 16, 18 (and typically cavity 36) may be (laterally) offset from the antennas 40. This enables the ground conductors to be provided directly underneath the antennas 40 (on the second surface 38 of the capping substrate 34) and also provides an increased distance between the via 42/conductive pillar 43 and the MEMS switches 16, 18 (which are typically provided in the cavity 36), thereby reducing interference between the antennas 40 and the MEMS switches. Further conductive connections are required to connect the vias 42 (which still provide part of the conductive path between the signal conductor 14 and the antenna 40) to the antenna 40, such as deposited and/or patterned signal tracks. Typically a common ground plane is provided for the antennas 40 and the electromagnetic signal divider and/or combiner 70 between the second surface 38 and the first surface 33 of the capping substrate 34. Typically the common ground plane is parallel to planes of the (planar) first and second surfaces 33 38 of the substrate 34, and provided between the said first and second surfaces 33 38 (in which case the antenna substrate 34 comprises a plurality of layers). Insulating portions are typically provided in the common ground plane in the region of through vias so as to avoid short circuiting the vias to the ground plane.

(71) Integrated circuits 49 providing the MEMS controllers are not shown in FIG. 8 for clarity, but typically they are formed on the respective individual discrete semiconductor IC substrates 50 provided for each of the antenna modules 1. It may be that some of the semiconductor signal processing circuitry common to a plurality of antenna modules is provided on the capping substrate 34 (which may be formed from a semiconducting material in this case) offset from the antenna modules 1.

(72) Instead of the MEMS switches and the integrated circuits 49 being provided on different substrates stacked on top of each other in the embodiment of FIG. 8, they may alternatively be manufactured on (e.g. different layers of) the same (typically semiconductor) substrate.

(73) FIG. 9 shows a variation of the arrangement 118 of FIG. 8. In this case, instead of capping portions of the capping substrate 34 forming the enclosed volume (together with the MEMS substrates 2) in which the MEMS switches are provided, the antenna modules 1 are provided with respective discrete interposer caps 120 which perform this function. The respective discrete interposer caps 120 comprise cavities which are vertically aligned with the MEMS switches of the MEMS substrates 2 (the semiconductor IC substrates 50 and antenna substrate 34 do not have cavities in this embodiment) to allow the MEMS switches to (selectively) move between their first and second states unimpeded and are stacked between the first surfaces 4 of the discrete MEMS substrates 2 and the common capping substrate 34 comprising the antennas 40. The interposer caps 120 help to match different coefficients of thermal expansion between the MEMS substrates 2 and the substrate 34 comprising the antennas 40 (e.g. by being formed of material having a coefficient of thermal expansion intermediate those of the MEMS substrate 2 and the substrate 34). The interposer caps 120 also provide conductive interface circuitry (i.e. the interposer caps 120 provide signal routing layers) for conductively connecting the signal conductors 14 of the respective MEMS substrates 2 to the antennas 40. In this case, the interface circuitry comprises respective through vias 121 extending through the interposer caps 120 between the MEMS substrates 2 and the vias 42 which extend through substrate 34 to connect to respective antennas 40. The interposer caps 120 may further comprises one or more integrated components or (e.g. passive) devices, such as one or more lumped elements (e.g. one or more capacitors, one or more inductors or one or more resistors) provided as part of the conductive interface.

(74) Particularly in the embodiments of FIGS. 8 and 9, preferably the substrate 34 has a high dielectric constant (e.g. greater than 3, more preferably greater than 5, greater than 10, greater than 20 or greater than 50) to allow antennas 40 to be provided closer together on the substrate 34, particularly those in different sub-arrays (although antennas common to the same sub-array would not couple with each other through a substrate having a high dielectric constant, if positioned close to each other they could still couple through the air). Again integrated circuits 49, 101 are not shown in FIG. 9 for clarity.

(75) As an alternative to the embodiments of FIGS. 8 and 9, it may be that the antennas 40 are instead provided (e.g. formed) on the first surface 33 of the capping substrate 34 (together with the electromagnetic signal divider and/or combiner 70 and the MEMS substrates 2). In this case, the antennas 40 and the electromagnetic signal divider and/or combiner 70 may be provided with a common ground plane on the second surface 38 of the common substrate 34. This effectively makes the MEMS phase shifters an integral part of the electromagnetic signal divider and/or combiner 70, allowing the MEMS phase shifters and antennas to be provided closer to each other with shorter conductive connections between them. Indeed, the requirement for through substrate vias is significantly reduced (although typically a short via and/or small conductive pillar is typically required to connect the signal conductors 14 of the MEMS phase shifters to the antennas and electromagnetic signal divider and/or combiner). This helps to keep parasitic and signal losses low, particularly at high signal frequencies.

(76) FIG. 10 is a schematic view of an alternative antenna module 150 comprising a MEMS substrate 2, which is identical to the MEMS substrate 2 of the antenna module 1 described above (the same reference numerals will be used for common features) capped by a semiconductor IC substrate 152 similar to the semiconductor IC substrate 50 described above. The MEMS switches 16, 18 are provided between the semiconductor IC substrate 152 and the MEMS substrate 2. The semiconductor IC substrate 152 comprises a first surface 152a which engages the MEMS substrate 2 and a second surface 152b opposite the first surface which comprises the antenna 40. The semiconductor IC substrate 152 and the MEMS substrate 2 together form an enclosed volume around the MEMS switches 16, 18 and the signal conductor 14 and a hermetic seal is provided between them. The enclosed volume is either at vacuum or at atmospheric pressure (in which case it is filled with nitrogen or an inert gas) or at a pressure intermediate vacuum and atmospheric pressure. The semiconductor IC substrate 152 also comprises a (typically CMOS) MEMS controller 153 configured to control the states of the MEMS switches 16, 18 as described above (and/or in some embodiments some or all of the said signal processing circuitry). As shown in FIG. 11, the MEMS controller 153 is provided on the second surface 152b of the semiconductor IC substrate 152 (typically offset from the antenna 40 vertically (in which case it may be that the semiconductor IC substrate 152 comprises a plurality of layers, and it may be that one or more of the layers, such as a layer comprising the antenna 40, is insulating) and/or laterally), but alternatively the MEMS controller 153 (or a portion thereof, or at least a portion of the signal processing circuitry) may be provided on an upper surface of the cavity 154 (i.e. first surface 152a of the semiconductor IC substrate 152) or on the first surface 152a of the semiconductor IC substrate 152 laterally offset from the MEMS switches. The MEMS controller 153 is connected to the MEMS switches by way of a redistribution layer of the semiconductor IC substrate 152 which connects the MEMS controller 153 to respective conductive pads 155 which conductively connect to the anchors 22 of the MEMS substrate 2. In the embodiment of FIG. 11, the conductive pads 155 are provided in the enclosed volume between the MEMS substrate 2 and the cap 152, but it will be understood that, alternatively, the conductive pads 155 may be provided outside of the enclosed volume but conductively connected to the respective anchors 22. The MEMS controller 153 may be a standalone controller or a local controller configured to receive control signals from a master MEMS controller as described above. The antenna 40 is conductively connected to the signal conductor 14 by way of conductive through substrate via 161 extending (fully) through the semiconductor IC substrate 152 and a conductive pillar 162 built up on the front end of the signal conductor 14.

(77) FIG. 12 shows a portion of a phased array 200 of antenna modules 150 wherein a semiconductor IC substrate 152 is a carrier substrate common to all of the antenna modules 150 of the array comprising the MEMS controllers (or local and/or master MEMS controllers where provided) of the antenna modules 150. Also shown in FIG. 12 is electromagnetic signal divider and/or combiner 210 formed on and supported by the first surface 152a of the carrier substrate 152, the electromagnetic signal divider and/or combiner 210 being configured to divide an RF signal from an RF port 214 between a plurality of antenna modules (typically of a sub-array) of the array and/or to combine RF signals from a plurality of antenna modules (typically of a sub-array) of the array to the RF port 214. The electromagnetic signal divider and/or combiner 210 comprises a plurality of conductive branches 212 each of which (directly) connects to the signal conductor 14 of a respective antenna module 150. The conductive branches 212 link to the RF port 214 which carries RF signals to and from the carrier substrate 152 by way of a surface mount connection (e.g. land grid array). The electromagnetic signal divider and/or combiner 210 is provided on the first surface 152a of the semiconductor IC substrate (i.e. on the same surface that the MEMS substrates of the antenna modules 150 are stacked). As above, a common ground plane is typically provided for the antennas 40 and the electromagnetic signal divider and/or combiner 210 between the first and second surfaces 152a, 152b of the capping substrate 152. Typically the common ground plane is parallel to planes of the (planar) first and second surfaces 152a, 152b of the substrate 152, and provided between the said first and second surfaces 152a, 152b (in which case the semiconductor IC substrate 152 comprises a plurality of layers). Insulating portions are typically provided in the common ground plane in the region of through vias so as to avoid short circuiting the vias to the ground plane. Also as above, respective electromagnetic signal dividers and/or combiners are provided for each sub-array of the array.

(78) The common carrier substrate 152 may further comprise integrated circuitry 101 comprising (typically semiconductor, typically CMOS) signal processing circuitry (e.g. power amplifier(s), low noise amplifier(s), analogue to digital converter, digital to analogue converter, interface, filters) configured to process signals received and/or to be transmitted by the antennas 40. In this case, the integrated circuitry 101 is provided between the port 214 and the connection 214.

(79) FIG. 13 is a schematic view of an alternative antenna module 250 which is identical to that shown in FIG. 10 and described above with reference thereto (common features will be referred to using the same reference numerals) except for the fact that the antenna 40 is provided on the second surface of the MEMS substrate 2 rather than on the second surface of the semiconductor IC substrate 152, the antenna 40 is connected to the signal conductor 14 by way of a via 252 extending through the MEMS substrate 2 and the IC(s) provided by the semiconductor IC substrate 152 are connected to the anchors 22 of the MEMS switches provided on the MEMS substrates by way of through vias 32 extending through the semiconductor IC substrate 152 (which still provides a protective cap for the MEMS switches). Via 44 in this case extends through the semiconductor IC substrate 152 to connect to a conductive pillar 253 built up on the back end of the signal conductor 14.

(80) FIG. 14 shows a portion of a phased array 300 of antenna modules 250 wherein the semiconductor IC substrate 152 comprising the MEMS controllers of the antenna modules (or the local and/or master MEMS controllers where provided) is again the common carrier substrate. Also shown in FIG. 14 is an electromagnetic signal divider and/or combiner 310 formed on and supported by the second surface 152b of the carrier substrate 152 (i.e. the opposite side of the carrier substrate 152 from the first side 152a of the substrate 152 on which the MEMS substrates 2 are mounted) and configured to divide an RF signal from an RF port 314 between a plurality of antenna modules of the array (e.g. of a sub-array) and/or to combine RF signals received from a plurality of said antenna modules of the array (e.g. a sub-array) to an RF port 314. The electromagnetic signal divider and/or combiner 310 comprises a plurality of conductive branches 312 each of which connects to the signal conductor 14 of a respective antenna module 250 by way of a respective via 44 and pillar 253 as shown in FIG. 13. The conductive branches 312 link to the RF port 314 which carries electromagnetic signals to and from the carrier substrate 152 by way of a surface mount connection (e.g. land grid array). In this case, a common ground plane for the antennas and the electromagnetic signal divider and/or combiner 310 is provided on the first surface 152a of the carrier substrate 152. Although the antennas 40 are shown directly above (i.e. vertically aligned) with the MEMS switches 16, 18 in FIG. 14, the antennas 40 may alternatively be laterally offset from the MEMS switches 16, 18 to reduce interference between the antennas 40 and the MEMS switches 16, 18.

(81) The common carrier substrate 152 of FIG. 14 may further comprise integrated circuitry 101 comprising signal processing circuitry configured to process signals received and/or to be transmitted by the antennas 40.

(82) As an alternative to the embodiments of FIG. 14, it may be that the antennas 40 and the electromagnetic signal divider and/or combiner 310 are instead provided (e.g. formed) on the first surface 152a of the semiconductor IC substrate 152 (together with the MEMS substrates 2). In this case, the antennas 40 and the electromagnetic signal divider and/or combiner 310 may be provided with a common ground plane on the second surface 152b of the common substrate 152. This effectively makes the MEMS phase shifters an integral part of the electromagnetic signal divider and/or combiner 310, allowing the MEMS phase shifters and antennas to be provided closer to each other with shorter conductive connections between them. Indeed, the requirement for through substrate vias is significantly reduced. This helps to keep parasitic and signal losses low, particularly at high signal frequencies.

(83) FIG. 14a shows a similar phased antenna array to FIG. 14, but in this case the MEMS switches 16, 18, signal and ground conductors 14, 15 and antennas 40 of each antenna module of the array are supported by and formed on a common MEMS substrate 2 (rather than individual discrete MEMS substrates 2 for each module). The common MEMS substrate 2 is stacked on (and typically bonded to) the carrier semiconductor IC substrate 152. The electromagnetic signal divider and/or combiner 310 is in this case provided on the second surface 6 of the MEMS substrate 2, the electromagnetic signal divider and/or combiner 310 being connected to the signal conductors 14 of the respective antenna modules by way of respective first through vias 198 which extend through the MEMS substrate 2. The first surface 4 of the common MEMS substrate 2 comprises a ground plane which provides a common ground plane for the electromagnetic signal divider and/or combiner 310 and the antennas 40. Although the antennas are shown vertically aligned with the MEMS switches 16, 18, it will be understood that alternatively, the antennas 40 may be laterally offset from the MEMS switches 16, 18.

(84) FIG. 14b shows a similar phased antenna array to FIG. 14a, but in this case, the carrier substrate is the common MEMS substrate 2. Individual semiconductor IC substrates 152 (one per antenna module) which are discrete from each other are mounted on the common MEMS substrate 2 to form respective enclosed volumes around the MEMS switches of the antenna modules of the array between the respective semiconductor IC substrates 152 and the MEMS substrate 2. The respective semiconductor IC substrates 152 typically comprise respective MEMS controllers (not shown in FIG. 14b) configured to control the respective MEMS switches provided in the respective enclosed volume formed between the respective semiconductor IC substrate 152 and the MEMS substrate 2. The semiconductor substrates 152 each have a cavity vertically aligned with the MEMS switches in the respective enclosed volumes such that the MEMS switches are allowed to move (selectively) between their first and second states.

(85) FIG. 15 shows a phased array 330 of alternative antenna modules 350 with the antennas 40 provided on a common carrier antenna substrate 360 bonded to the second surfaces of the MEMS substrates 2. The MEMS substrates 2 are sandwiched between the antenna substrate 360 and discrete semiconductor IC substrates 152 comprising the MEMS controllers. The MEMS switches 16, 18 are provided in an enclosed volume between a capping portion of the semiconductor IC substrate 152 and the MEMS substrate 2. The antennas 40 are conductively connected to the respective signal conductors 14 of the respective antenna modules 350 by way of conductive through substrate vias 362a, 362b together extending through the MEMS substrate 2 and the antenna substrate 360. The discrete semiconductor IC substrates 152, together with the MEMS substrates 2, form enclosed volumes around the MEMS switches 16, 18 of the respective modules. Hermetic seals are provided between the MEMS substrates 2 and the respective semiconductor IC substrates. MEMS control signals are provided from the or the respective MEMS controller of the semiconductor IC substrate 152 to the anchors 22 of the MEMS switches 16, 18 by way of respective through vias 32 extending through the respective semiconductor IC substrates 152. A common ground plane is typically provided for the antennas 40 and the electromagnetic signal divider and/or combiner 310 between the second and first surfaces 361, 363 of the carrier substrate 360. Typically the common ground plane is parallel to planes of the (planar) first and second surfaces 361, 363 of the substrate 360, and provided between the said first and second surfaces 361, 363 (in which case substrate 360 comprises a plurality of layers). Insulating portions are typically provided in the common ground plane in the region of through vias so as to avoid short circuiting the vias to the ground plane. Electromagnetic signal divider and/or combiner 310 is formed on and supported by the first surface 361 of the carrier substrate 360 on which the MEMS substrates 2 are stacked, the electromagnetic signal divider and/or combiner 310 being configured to divide an RF signal from an RF port between a plurality of antenna modules 350 (e.g. a sub-array) of the array 330 and/or to combine RF signals received from a plurality of antenna modules 350 (e.g. a sub-array) of the array to an RF port.

(86) It may be that the carrier substrate 360 is formed from semiconducting material and signal processing circuitry common to a plurality of antenna modules (e.g. master MEMS controller) is formed on the carrier substrate 360 (e.g. offset from the antenna modules 1). Alternatively, semiconductor signal processing circuitry common to a plurality of antenna modules may be provided on an external substrate separate from the carrier substrate 360. It is preferable for the antenna substrate 360 to have a high dielectric constant (e.g. made from one or more of the high dielectric materials set out above in respect of the MEMS substrate(s)) in order to reduce the electric (and thus physical) length of the antennas 40, thereby allowing them to be provided smaller (or more complicated) and closer together. In some cases, the antenna substrate is a laminate substrate, LTCC substrate, HTCC substrate, organic substrate, multi-layer organic substrate (such as a multi-layer organic substrate from Rogers Corporation), a glass substrate, a ceramic substrate, a glass ceramic substrate or an insulating substrate such as alumina.

(87) FIG. 16 shows yet another phased antenna array 500 which is identical to phased antenna array 330 shown in FIG. 15 but for the addition of respective discrete interposer caps 510 provided between the MEMS substrates 2 and the semiconductor IC substrates 152. The respective interposer caps 510 are stacked (and sandwiched) between the first surface of the MEMS substrate 2 and the respective semiconductor IC substrates 152. The interposer caps 510 help to match different co-efficients of thermal expansion between the MEMS substrate 2 and semiconductor IC substrates 152 (e.g. by being formed of material having a coefficient of thermal expansion intermediate those of the MEMS substrate 2 and the semiconductor IC substrates 152). The interposer caps 510 also provide an electrical interface (i.e. the interposer caps 510 provide signal routing layers) between the MEMS substrates 2 and the respective semiconductor IC substrate 152, in this case in the form of through vias extending through the interposer caps 510 between the MEMS substrates 2 and the semiconductor IC substrate 152. In this case, the MEMS controllers of the respective semiconductor IC substrates 152 are electrically connected to the anchors 22 of the MEMS switches by way of a first respective through substrate via 32 extending through the respective semiconductor IC substrate 152 and a second respective through substrate via 365 which extends through the respective interposer cap 510. The interposer caps 510 may further comprise one or more integrated components or (e.g. passive) devices, such as one or more lumped elements (e.g. one or more capacitors, one or more inductors or one or more resistors) provided as part of the conductive interface.

(88) A method of manufacturing the antenna apparatus 1 of FIGS. 1 to 3 is illustrated in FIGS. 17 to 21. With reference to FIG. 17, the capping portion of the capping substrate 34 can be manufactured by: providing a (typically monolithic) semiconductor substrate 34; forming (e.g. etching) a cavity 36 in a first surface 33 of the (e.g. high resistivity silicon) substrate 34; providing (typically forming, e.g. by etching a hole in the substrate 34 and filling it with metal) a conductive through substrate via (e.g. through silicon via) 42 extending from a second surface 38 of the substrate 34 to the first surface 33 of the substrate 34 so that the via 42 is in communication with the cavity 36; and forming (e.g. by depositing and/or patterning metal (e.g. by photolithography)) an antenna element 40 on the second surface 38 of the substrate 34 such that an end of the antenna element 40 is in conductive communication with the via 42 (i.e. the end of the via 42 closest to the second surface 38 of the semiconductor substrate 34). A conductive ground plane is typically formed on the second surface 33 of the capping substrate 34 by depositing a metal layer thereon with an insulating portion surrounding the via 42 on the second surface 33.

(89) With reference to FIG. 18, a crystalline semiconductor MEMS substrate 2 (which in this case will be assumed to be formed from high resistivity silicon) is provided. As shown in FIG. 19, a through substrate via 44 is formed (e.g. by etching a hole in the MEMS substrate and filling it with metal) between the first and second surfaces 4, 6 of the MEMS substrate 2. A signal conductor 14 and ground conductors 15 are formed (e.g. deposited and/or patterned, e.g. using photolithography) on the first surface 4 such that a back end of the signal conductor is conductively connected to the through substrate via 44. Solid dielectric material 28 is deposited on the signal conductor 14. In addition, conductive through substrate vias 32 are formed (e.g. by etching holes in the substrate 2 and filling them with metal) between the first surface 4 of the MEMS substrate 2 and the second surface 6 of the MEMS substrate 2. Anchors 20, 22 are formed (e.g. deposited) on either side of the signal co-planar waveguide formed by the signal conductor 14 and ground conductors 15 by depositing conductive material (e.g. metal, e.g. aluminium) to form pillars having heights (above the first surface 4 of the MEMS substrate 2 on which they are formed) which are greater than the heights of the combination of the signal conductor 14 and dielectric layer 28 and greater than the heights of the ground conductors 15. Anchor 22 is formed on top of via 32 to allow connection of the anchor 22 to the MEMS controller. A ground plane may also be formed on the second surface 6 of the MEMS substrate 2 by depositing metal thereon.

(90) As shown in FIG. 20, MEMS switches 16, 18 are formed on the first surface 4 of the MEMS substrate 2. This is done by serial semiconductor (e.g. CMOS) fabrication process steps, typically including: filling the region between the anchors 20, 22 with a sacrificial (typically polymer or silicon oxide) layer; polishing the sacrificial layer; forming (e.g. depositing) a conductive (typically metallice.g. aluminium) layer on top of the sacrificial layer extending between the anchors 20, 22; patterning (e.g. by masking and etching, e.g. using photolithography) the conductive layer into the desired shape of the MEMS bridge 24; and removing (the mask, where provided, and) the sacrificial layer (e.g. using a sacrificial layer solvent). In addition, the conductive pillar 43 is formed (e.g. built up by material deposition) at a front end of the signal conductor 14 for conductively connecting the via 42 to the signal conductor 14.

(91) It will be understood that, alternatively, a trench may be formed in the MEMS substrate 2 and the MEMS switches 16, 18 are formed in the trench by depositing the sacrificial layer in the trench and polishing it before forming the bridge 24 as described above. In some embodiments, the anchors 22 of discrete groups of capacitive MEMS switches are conductively connected together to form a (e.g. 7-bit) reconfigurable MEMS phase shifter (as described above).

(92) With reference to FIG. 20a, the capping substrate 34 is typically bonded to the MEMS substrate 2 by: providing a first metal sealing ring 598 around the MEMS switches 16, 18 on the MEMS substrate 2; providing a second metal sealing ring 599 around the cavity 36 on the capping substrate 34; placing the capping substrate 34 onto the MEMS substrate 2 such that the rings are provided between the capping substrate 34 and the MEMS substrate 2 which form an enclosed volume around the MEMS switches 16, 18; placing the capping substrate and the MEMS substrate 2 together into a vacuum chamber; evacuating the chamber (e.g. to substantially a vacuum); heating the chamber to melt the sealing rings; and cooling the chamber so that the sealing rings cool and thereby solidify to bond the MEMS substrate 2 to the capping substrate 34, and to form a hermetic seal between the MEMS substrate 2 and the capping substrate to maintain a vacuum in the enclosed volume. Grooves 600 are provided between the MEMS switches 16, 18 and the sealing rings 598, 599 so as to receive reflowed metal from the molten sealing rings, in order to inhibit (preferably prevent) the reflowed metal coming into contact with the MEMS switches 16, 18. Optionally, grooves 601 are also provided between the sealing rings 598, 599 and the outer edge of the capping substrate. Grooves may be provided in the MEMS substrate 2 such that the grooves in the MEMS substrate 2 can be aligned with grooves in the capping substrate to thereby align the MEMS substrate 2 and the capping substrate 34 during assembly (which typically helps to align via 42 with conductive pillar 43).

(93) Instead of using grooves 600 to prevent molten metal from the sealing rings from coming into contact with the MEMS switches 16, 18, multiple (thinner) sealing rings (for example three sealing rings) may be provided with gaps between them in place of sealing rings 598, 599.

(94) The step of evacuating the chamber may be substituted or followed by a step of filling the chamber with nitrogen at atmospheric pressure or at a pressure intermediate vacuum and atmospheric pressure (e.g. between 25% and 75% of atmospheric pressure). In this case, instead of the enclosed volume being a vacuum in the sealed structure, the sealed enclosed volume contains nitrogen at atmospheric pressure or at the said pressure intermediate vacuum and atmospheric pressure. This reduces the pressure differential between the enclosed volume and the surrounding environment (in typical use) which helps to prevent leaks bringing the enclosed volume into communication with the surrounding environment.

(95) It will be understood that, when the capping substrate 34 is placed on the MEMS substrate, the via 42 is brought into conductive engagement with the signal conductor 14 to thereby conductively connect the antenna 40 to the signal conductor 14.

(96) In order to form the structure of FIG. 4, the method may further comprise forming integrated circuitry 49 on the semiconductor IC substrate 50 by serial semiconductor (e.g. high voltage CMOS) fabrication process steps, typically including depositing material on the substrate; patterning the deposited material (e.g. by photolithography); etching; and doping. Next, the method comprises bonding the first surface 52 of the semiconductor IC substrate 50 to the second surface 6 of the MEMS substrate 2. Again, this may be by providing metal sealing rings around the periphery of the second surface 6 of the MEMS substrate 2 and around the periphery of the first surface 52 of the semiconductor IC substrate 50; heating the metal sealing rings to thereby melt the metal sealing rings; and cooling the metal sealing rings so that they solidify to thereby bond the substrates 2, 52 together. This results in the antenna module of FIG. 4.

(97) As shown in FIG. 5, it may be that the semiconductor IC substrate 50 is a carrier substrate which carries a plurality of antenna modules 1 to form a phased antenna array 100. In this case, the second surfaces 6 of the discrete MEMS substrates 2 of the respective antenna modules 1 are bonded to respective portions of the carrier substrate. The method may further include providing (typically forming, typically deposited and/or patterned, e.g. using photolithography) digital signal tracks on and/or through the semiconductor IC substrate 50 in order to carry control signals from the MEMS controller to the vias 32 (if for example the MEMS controller is not provided directly beneath the MEMS substrates 2 and is instead offset therefrom on the carrier substrate, or to carry control signals from the master MEMS controller (where provided) to the respective local MEMS controllers).

(98) The method typically further comprises forming electromagnetic signal dividers and/or combiners 70 on the first surface 52 of the semiconductor carrier substrate 50, typically by providing deposited and/or patterned tracks onto the first surface 52 of the semiconductor carrier substrate (e.g. by depositing, masking and etching a metallic layer, e.g. using photolithography). The electromagnetic signal dividers and/or combiners is typically connected to circuitry external to the carrier substrate 50 by respective connections 74 (e.g. to RF front end circuitry of a base station or a small, micro or femto cell infrastructure, or wireless backhaul, transmitter, receiver or transceiver or a or mobile wireless telecommunications device).

(99) The method typically further comprises forming integrated circuitry 101 on the semiconductor carrier substrate 50 by serial semiconductor (e.g. CMOS) fabrication process steps, typically including depositing material on the substrate; patterning the deposited material (e.g. by photolithography); etching; and doping. The integrated circuitry 101 is typically provided between an electromagnetic signal divider and/or combiner 70 and a connection 74.

(100) As discussed above, the integrated circuitry 49 typically comprises a MEMS controller (or local MEMS controller) configured to control the states of the MEMS switches 16, 18. The integrated circuitry 101 typically comprises semiconductor integrated signal processing circuitry, which may be RF signal processing circuitry and/or digital signal processing circuitry. The integrated circuitry 101 may further comprise a master MEMS controller configured to control local MEMS controllers provided in integrated circuitry 49 local to the antenna modules.

(101) As discussed above, instead of the semiconductor IC substrate 50 being the carrier substrate of the phased antenna array 100, it may be that the capping substrate 34 is the carrier substrate so as to form the phased antenna array 118 shown in FIG. 8. In this case, the sealing and evacuation (and/or inert gas/nitrogen filling) of the enclosed volumes between the capping substrate 34 and the MEMS substrates 2 of the antenna modules 1 typically takes place in parallel in the chamber. The bonding of the individual semiconductor IC substrates 52 to the second surfaces of the MEMS substrates 2 may be performed beforehand, afterwards or at the same time.

(102) As also discussed above, instead of the capping substrate 34 forming the enclosed volume around the MEMS switches 16, 18 with the MEMS substrate 2, it may be that respective discrete interposer caps 120 are provided between the MEMS substrates 2 and the carrier substrate 50 to form the phased array as shown in FIG. 9. In this case, the sealing and evacuation (and/or inert gas/nitrogen filling) of the enclosed volumes between the interposers 120 and the MEMS substrates 2 of the antenna modules 1 is performed (serially or in parallel) in the said chamber. The bonding of the interposers 120 to the carrier substrate 50 (which is typically performed by heating and cooling a metallic sealing ring between the interposers 120 and the carrier substrate 50) can be performed serially or in parallel with the sealing of the enclosed volumes. The method may comprise forming a conductive interface in the interposers, optionally comprising one or more conductive through substrate vias and/or one or more integrated components or (e.g. passive) devices, such as one or more lumped elements (e.g. one or more capacitors, one or more inductors or one or more resistors) provided as part of the conductive interface. For example, the interposers may comprise one or more vertical capacitors.

(103) As discussed above with respect to FIG. 5b, instead of providing discrete MEMS substrates 2 and capping substrates 34, it may be that a MEMS substrate 2 common to all of the antenna modules of the array and a capping substrate 34 common to all of the antenna modules of the array are provided. In addition, it may be that the electromagnetic dividers and/or combiners are provided on the first surface 4 of the common MEMS substrate 2.

(104) In order to manufacture the antenna module 150 shown in FIGS. 10 to 11, or the phased array 200 shown in FIG. 12, the step of forming the IC substrate 152 is the same as the step of forming the IC substrate 50 described above, but for the addition of the antenna 40 being deposited and/or patterned on the second surface 152b of the semiconductor IC substrate 152 and a conductive through substrate via 161 conductively extending between the antenna 40 and the signal conductor 14 on the MEMS substrate 2. This is illustrated in FIG. 21. Typically via 161 is formed (e.g. by etching a hole through the substrate 152 and filling it with metal) before the antenna 40. In addition, a redistribution layer is formed and configured to route MEMS control signals from the integrated circuitry formed on the semiconductor IC substrate 152 to the conductive anchors 22 on the MEMS substrates 2. The semiconductor IC substrate 152 is sealedly bonded to the MEMS substrate 2 in a similar way to the way in which the capping substrate(s) 34 and the MEMS substrates 2 are bonded above.

(105) As shown in FIG. 12, the semiconductor IC substrate 152 may be the carrier substrate of the phased array 200. In this case, the sealing of the semiconductor IC substrate 152 to the respective MEMS substrates 2 of the array 200 is typically performed in the chamber (e.g. in parallel with each other).

(106) In order to manufacture the antenna module 250 shown in FIG. 13, instead of forming the antenna 40 on the second surface of the semiconductor IC substrate 152, the antenna 40 is formed on the second surface 6 of the MEMS substrate 2 (again typically by depositing material and patterning (e.g. using photolithography)) and a via 252 is formed which extends through the MEMS substrate 2 to conductively connect the antenna 40 to the signal conductor 14. This is illustrated in FIG. 22. In this case, the semiconductor IC substrate 152 comprises the integrated circuitry and a cavity 36 which aligns with the MEMS switches 16, 18 on the MEMS substrate 2. This is shown in FIG. 23. Again, grooves may be provided in the respective substrates to help with the alignment thereof.

(107) As shown in FIG. 14, the semiconductor IC substrate 152 may be the carrier substrate for a phased array 300 comprising a plurality of the antenna modules 250 of FIG. 13.

(108) As shown in FIG. 14a, instead of providing discrete MEMS substrates 2, a MEMS substrate 2 may be provided which is common to all of the antenna modules of the array. In this case, it may be that the electromagnetic signal dividers and/or combiners are provided on the second surface 6 of the common MEMS substrate 2.

(109) As shown in FIG. 14b, instead of providing a common semiconductor IC substrate 152, a plurality of semiconductor IC substrates 152 discrete from each other may be provided.

(110) In order to form the phased antenna array 330 shown in FIG. 15, instead of forming the antennas 40 on the second surfaces 6 of the MEMS substrates 2, they may be formed on a second surface 363 of a semiconductor antenna substrate 360 opposite a first surface 361 of the semiconductor antenna substrate 360 on which the MEMS substrates of the antenna modules are mounted. In this case, the semiconductor antenna substrate 360 acts as the carrier substrate. The vias 362a,b together extend between the antennas 40 and the respective signal conductors 14 through the antenna substrate 360 and the MEMS substrate 2. In this embodiment, the sealing and evacuation (and/or inert gas/nitrogen filling) occurs between the semiconductor IC substrates 152 and the MEMS substrates 2, the semiconductor IC substrates 152 providing the protective cap function for the MEMS switches 16, 18. The MEMS substrates 2 are bonded to the antenna substrate 360, either in series with or in parallel to the evacuation (and/or inert gas/nitrogen filling) and sealing between the semiconductor IC substrates 152 and the MEMS substrates 2.

(111) As shown in FIG. 16, respective discrete interposers 510 may provide the cap over the MEMS switches 16, 18. In this case, the sealing and evacuation (and/or inert gas/nitrogen filling) between the interposers 510 and the MEMS substrates 2 occurs either in series with or in parallel with the bonding of the antenna substrate 360 to the MEMS substrates 2. Similarly the bonding between the interposers 510 and the semiconductor IC substrates 152 may occur in series with or parallel to the sealing and evacuation (and/or inert gas/nitrogen filling) between the interposers 510 and the MEMS substrates 2.

(112) It will be understood that in any of the above embodiments, any of the MEMS controller(s) or signal processing circuitry may be provided on semiconductor IC substrates individual to the antenna modules, on a semiconductor IC substrate common to a plurality of the antenna modules, or distributed between semiconductor IC substrates individual to the antenna modules and a semiconductor IC substrate common to a plurality of the antenna modules.

(113) In each case, the respective ground planes are formed by depositing metallic layers on the relevant substrate surfaces.

(114) It will be understood that, in the variations of the embodiments of FIGS. 8, 9 where the antennas are formed on the second surface 38 of the capping substrate 34, the antennas would be formed on the first surface 33 of the capping substrate 34 (typically by deposition of metal) rather than on the second surface 38. Similarly, in the variation of the embodiment of FIG. 14 where the antennas 40 are formed on the first surface 152a of the semiconductor IC substrate 152, the antennas would be formed on the first surface 152a of the semiconductor IC substrate 152 rather than on the second surfaces 6 of the MEMS substrates 2.

(115) It will also be understood that, in some embodiments the MEMS phase shifters and/or MEMS attenuators may be replaced by other types of phase shifter and/or attenuator (e.g. semiconductor based phase shifters and/or attenuators).

(116) In some embodiments, instead of forming the antennas of the antenna modules on a semiconducting substrate, it may be that they are formed on an insulating substrate such as alumina. Alumina is particularly attractive for the antenna substrate because it has a very low loss tangenti.e. it allows the antenna to radiate the field rather than it being lost in the substrate. Alumina can also be easily deposited as a dielectric.

(117) The electromagnetic signal divider and/or combiner in each phased array may be formed by the deposition of metal on the relevant surface.

(118) As discussed above, common ground planes may be provided for the electromagnetic signal divider and/or combiner and the antennas, and in some cases this is provided as an intermediate layer between first and second substrate surfaces of the capping substrate, the MEMS substrate or the carrier substrate. In this case, the respective capping substrate, MEMS substrate or carrier substrate may be provided as a multi-layered substrate comprising respective first and second substrate layers and a ground plane sandwiched between them.

(119) Further variations and modifications may be made within the scope of the invention herein described.

(120) For example, although some of the embodiments discussed above provide a respective MEMS controller or local MEMS controller on an integrated circuit 49 for each antenna module, it may be that a single MEMS controller or a single local MEMS controller is provided for controlling the MEMS switches of each of a plurality of antenna modules. FIG. 24 is a plan view of a 44 MIMO phased antenna array 700 comprising sixteen antenna modules (which in this example are the antenna modules as described in FIG. 13) which form four independent 22 sub-arrays (the antennas of the first sub-array being referred to by reference numeral 702, the antennas of the second sub-array being referred to by reference numeral 704, the antennas of the third sub-array being referred to by reference numeral 706 and the antennas of the fourth sub-array being referred to by reference numeral 708), each of which comprises four antennas and which is configured to wirelessly communicate with one or more (typically terrestrial) electromagnetic signal sources/receivers independently of the other sub-arrays. The antenna modules 702-708 of the respective sub-arrays are interspersed with antenna modules of one or more other said sub-arrays to reduce interference between antenna modules of the same sub-array. In an alternative embodiment (see FIG. 25), the antennas of each sub-array may be provided adjacent to each other (e.g. arranged in a 22 grid). Typical separation between antennas of the same sub-array is /2 or or 2 (where is the wavelength of electromagnetic radiation being transmitted or received by the antennas).

(121) The antenna modules 702-708 of all four sub-arrays are carried by a common semiconductor carrier substrate 709 which comprises respective integrated circuits 710, 712, 714 and 716 (formed on the reverse side thereof (i.e. to that on which the MEMS substrates of the antenna modules are mounted)) which each comprise a respective MEMS controller configured to control the MEMS switches of the antenna modules within the respective sub-arrays 702, 704, 706 and 708 respectively. That is, each MEMS controller controls the MEMS switches of a respective sub-array. Specifically, IC 710 controls the MEMS switches of sub-array 702, IC 712 controls the MEMS switches of sub-array 704, IC 714 controls the MEMS switches of sub-array 706 and IC 716 controls the MEMS switches of the sub-array 708. The integrated circuits 710-716 are conductively connected to the MEMS switches of the antenna modules which they are configured to control by deposited and/or patterned signal tracks (e.g. on one or both of the side of the carrier substrate 709 on which the MEMS substrates are mounted and the side on which the integrated circuits are formed) and/or conductive through substrate vias (not shown). Part of one of the integrated circuits 710, 712, 714 and 716 is typically (but not necessarily) provided beneath each antenna module 702, 704, 706 and 708. By providing a common integrated circuit which provides the MEMS controller for the MEMS switches of the antenna modules of each sub-array, a more compact structure can be provided which helps to reduce footprint and signal losses and to improve manufacturing efficiency.

(122) It may be that a master MEMS controller is provided (e.g. on the semiconductor carrier substrate 709) which controls each of the MEMS controllers 710-716, the MEMS controllers 710-716 being local MEMS controllers in this case. The MEMS controllers 710-716 may each be configured to receive (e.g. from the master MEMS controller) as inputs control signals 59 which specify which of the MEMS switches 16, 18 of the respective said sub-arrays should be in their first (up) states and which should be in their second (down) states in order to achieve target phase shifts and/or a steering direction and/or signal amplitudes and/or gains for the electromagnetic signals received and/or to be transmitted by the antennas 40 of that sub-array. In this case, as explained above, the MEMS controllers 710-716 are required to interface with circuitry 62 (e.g. by way of an industry standard interface such as an industry standard RF Front End (RFFE) interface or Serial Peripheral Interface (SPI) etc.) to receive control signals for controlling the MEMS switches 16, 18, in some cases boost the system voltage (e.g. 3.3V) to a higher DC voltage (e.g. 30V or 40V) required for actuation of the MEMS switches of the respective sub-array (which is again typically done by one or more charge pumps of the local controllers or the combination of one or more charge pumps of the local controllers and one or more energy storage elements (e.g. capacitors), although alternatively this may be done by one or more charge pumps of the master controller or the combination of one or more charge pumps of the master controller and one or more energy storage elements (e.g. capacitors)) and route the boosted, relevant control signals to the correct MEMS switches 16, 18 of the correct antenna modules. The determination of which switches 16, 18 should be in which states may performed in the master MEMS controller (where provided) or in circuitry external to the array responsive to a target phase shift and/or gain and/or amplitude and/or steering direction.

(123) Alternatively, the MEMS controllers 710-716 may be standalone controllers configured to receive inputs from circuitry external to the array. For example, the controllers 710-716 may be configured to receive as inputs target phase shifts and/or a steering direction and/or signal amplitudes and/or gains for the electromagnetic signals received and/or to be transmitted by the antennas 40 of the respective sub-array they control. The controllers 710-716 may be configured to determine from the inputs configurations for the MEMS switches of the respective sub-array specifying which of the one or more MEMS switches 16, 18 should be in their first (up) states and which of the MEMS switches 16, 18 should be in their second (down) states responsive to the inputs, and to provide control signals to the relevant MEMS switches 16, 18 of the relevant sub-arrays to implement the determined configurations. Alternatively, the inputs received by the controllers 710-716 may specify which of the MEMS switches of the antenna modules are to be in which state.

(124) The re-use of MEMS controllers for a plurality of antenna modules means, for example, that one or more charge pumps and, where provided, energy storage elements, (where required to boost the system voltage in order to actuate the MEMS switches) can be re-used between antenna modules within a particular sub-array. In addition, the number of digital interfaces required can be reduced.

(125) As an alternative to providing one standalone MEMS controller or one local MEMS controller per sub-array, one standalone MEMS controller or local MEMS controller can be provided per pair of antenna modules (i.e. to control the MEMS switches thereof) or even one standalone MEMS controller for the entire array.

(126) As before the common carrier substrate 709 may further comprise signal processing circuitry configured to process electromagnetic signals received and/or to be transmitted by the antennas (either individual to the antenna modules, or common to each of a plurality of the antenna modules, e.g. common to the antenna modules of a respective sub-array).

(127) Although the arrays shown in FIGS. 24 and 25 are described as being 44 arrays, with 22 sub-arrays, more typically a full array would be a 1616 array with each sub-array being 44 sub-arrays.

(128) It may be that the arrays of FIGS. 24, 25 are based on the architecture described above with reference to FIG. 14. In an alternative embodiment to that shown in FIGS. 24-25, the carrier substrate 709 is instead an antenna substrate common to each of the antennas of the array. In this case, it may be that the arrays are based on the architecture described above with reference to FIG. 14a.

(129) Although the examples shown in the Figures show the anchors 20, 22 as provided within an enclosed volume between the MEMS substrate and the capping substrate, it may be that the anchors 20, 22 (or conductive pads conductively connected to the anchors) are provided external to the enclosed volume. In this case, the method may comprise grinding the capping substrate in order to expose the anchors 20, 22 (or a single anchor thereof).

(130) Although the example described above describe the MEMS substrate as a semiconductor crystalline substrate, in some embodiments the MEMS substrate need not be a semiconductor substrate or a crystalline substrate. For example, in some embodiments, the MEMS substrate may be an amorphous (e.g. glass) substrate. In some embodiments the MEMS substrate may be a ceramic substrate.

(131) Although the examples described above involve the capacitive MEMS switches of the MEMS phase shifter each providing substantially the same quantity of phase shift to signals propagating on the signal conductor, it will be understood that in other embodiments, different capacitive MEMS switches of the phase shifter provide different quantities of phase shift to signals propagating on the signal conductor.

(132) Although the interposer caps 120 and 510 are described as comprising a conductive interface and optionally integrated components or devices provided as part of the conductive interfaces, it may be that the capping substrate of any of the embodiments described herein may comprise a conductive interface and optionally integrated components or devices provided as part of the conductive interfaces.

(133) FIGS. 26 and 27 illustrate an example embodiment of the invention labelled as above, in which MEMS switches 16 are formed on a MEMS substrate 2 which also support an antenna 40 to which it is connected via a signal conductor 14 (in practice although it is shown schematically with a dashed line it is typically formed on the MEMS substrate). A capping substrate 34 has a capping portion 600 which is sealed against the MEMS substrate, using in this example a sealant 602, thereby forming an enclosed volume 604 around the respective MEMS switch. The signal conductor is connected to RF signal processing circuitry (e.g. a power amplifier to drive the antenna) by way of a through-substrate via 606. Ground conductors 608 are also connected to external circuitry by way of through-substrate vias 610. MEMS switch control lines 612 further extend through a semiconductor carrier substrate 614 on which are formed one or more ICs predominantly configured as local MEMS controllers 615 which a group of MEMS switches to regulate a plurality of antenna modules, but also include a master MEMS controller 616 which control the local MEMS controllers thereby (indirectly) controlling the switches of the array. A ground plane 617 is provided on the opposite surface of the MEMS substrate to the antennas.

(134) The through-substrate vias are hermetic and the interior of the enclosed volume is a vacuum. Accordingly, the MEMS switches remain in a vacuum environment, avoiding damage. Typically the number of through-substrate vias is limited, for example, it may be that there are two hermetic through-substrate vias for an RF signal line (for communication between the antenna and RF circuitry) two or four hermetic through-substrate vias for a ground connection, and optionally two through-substrate vias for one or more MEMS switch control signals, and no other electrical connections into the enclosed volume.

(135) In another embodiment, RF signals are conducted into the enclosed volume by way of through-substrate vias, but non-RF signals, typically MEMS switch control signals, are conducted into the enclosed volume through substrate integrated waveguides, e.g. along the surface of the MEMS substrate, under the sealant. This provides efficient, reliable connections while maintaining the vacuum.

(136) The control architecture is further described in FIGS. 28 to 30. In this example a 16-element passive subarray comprises 16 antennas 40 with individual MEMS switch controlled phase shifters 618 and attenuators 619 to form a controllable phased array driven by baseband 620. RF signals to the antennas are generated by 10 GHz and 18 GHz sources 622, 624 (in this example), and digital data 626 fed into a DAC 628 (or in reverse ADC) and upconverters 630 within a transceiver 632 which generates modulated RF signals 634 which are in turn processed through a suitable RF front-end 636 and supplied through dividers and combiners to the individual antennas. A master MEMS controller provides array control signals 638 which are processed by local MEMS controllers containing charge pumps 646 to generate switch control signals to raise or lower MEMS switches, in changing their capacitance and thus the phase shift to a respective antenna. Although a single phase shifter is shown per antenna for clarity, in practice there may be many to give a highly controllable phase shift. As well as MEMS phase shifters and attenuators MEMS switches may select between antennas. To enable the MEMS switches to change rapidly and simultaneously despite the potentially large number of control signals, each switch is associated with a control register 640 which determines the instantaneous control signal to an individual MEMS switch and a shadow register 642 into which the next setting of the control register is preloaded. A trigger signal line 644 conducts trigger signals to the local MEMS controllers and the shadow registers are copied to the control registers at a trigger signal (e.g. rising or falling edge).