SINGLE-GATE MULTIPLE-TIME PROGRAMMING NON-VOLATILE MEMORY AND OPERATION METHOD THEREOF

Abstract

A single-gate non-volatile memory and an operation method thereof are disclosed, wherein the non-volatile memory has a single floating gate. The non-volatile memory disposes a transistor and a capacitor structure in a semiconductor substrate. The transistor has two ion-doped regions disposed at two sides of a conduction gate to function as a source and a drain and disposed in the semiconductor substrate. The widths of the source and the drain are differently, and the edge of the drain is utilized to serve as a capacitor to control the floating gate. The minimum control voltages and elements during writing are involved to greatly reduce the area, control lines and the cost thereof.

Claims

1. A single-gate multiple-time programming non-volatile memory comprising: a P-type semiconductor substrate; a transistor comprising a first dielectric layer, a first conduction gate and a plurality of ion-doped regions, said first dielectric layer is disposed on said P-type semiconductor substrate, and said first conduction gate is stacked on said first dielectric layer, and said ion-doped regions are respectively disposed at two sides of said first conduction gate to function as a source and a drain and disposed in said P-type semiconductor substrate, wherein the source and the drain have different widths; and a capacitor structure disposed on said P-type semiconductor substrate, and the edge of the drain is utilized to serve as a capacitor to control a floating gate and comprises a lightly-doped region between the drain and the floating gate, and said lightly-doped region and said ion-doped regions are doped with the same type of ions, and forming a single floating gate.

2. An operation method of a single-gate multiple-time programming non-volatile memory, and said non-volatile memory comprises a P-type semiconductor substrate, a transistor and a capacitor structure, and said transistor and said capacitor structure are disposed in said P-type semiconductor substrate, and said transistor comprises a first dielectric layer, a first conduction gate and a plurality of ion-doped regions, said first dielectric layer is disposed on said P-type semiconductor substrate, and said first conduction gate is stacked on said first dielectric layer, and said ion-doped regions are respectively disposed at two sides of said first conduction gate to function as a source and a drain and disposed in said P-type semiconductor substrate, wherein the source and the drain have different widths, and the edge of the drain is utilized to serve as a capacitor to control a floating gate and comprises a lightly-doped region between the drain and the floating gate, and said lightly-doped region and said ion-doped regions are doped with the same type of ions, and forming a single floating gate, and said operation method is characterized in: respectively applying a substrate voltage V.sub.sub, a source voltage V.sub.s and a drain voltage V.sub.d to said P-type semiconductor substrate, said source and said drain; in writing said non-volatile memory, a. V.sub.sub=ground (0); b. V.sub.d=V.sub.s=HV (High Voltage); V.sub.d=HV (High Voltage), and V.sub.s=MV (Medium Voltage) or LV (Low Voltage); or V.sub.d=MV (Medium Voltage), and V.sub.s=LV (Low Voltage) or ground (0); and in erasing said non-volatile memory, a. V.sub.sub=ground (0); b. V.sub.d=HV (High Voltage), and V.sub.s=ground (0); V.sub.d=HV (High Voltage), and V.sub.s=floating voltage; V.sub.s=HV (High Voltage), and V.sub.d=ground (0); or V.sub.s=HV (High Voltage), and V.sub.d=floating voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG. 1 is a sectional view schematically showing the structure of a single-gate multiple-time programming non-volatile memory according to an embodiment of the present invention;

[0022] FIG. 2 is a diagram schematically showing a first layout structure of the source and the drain with different widths according to the embodiment of the present invention;

[0023] FIG. 3 is a diagram schematically showing a second layout structure of the source and the drain with different widths according to the embodiment of the present invention; and

[0024] FIG. 4 is a diagram schematically showing the single-gate multiple-time programming non-volatile memory having three terminals according to the embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0025] Refer to FIG. 1. FIG. 1 is a sectional view schematically showing the structure of a single-gate multiple-time programming non-volatile memory according to an embodiment of the present invention.

[0026] The single-gate multiple-time programming non-volatile memory 100 comprises a P-type semiconductor substrate 130 or a semiconductor substrate with a P-type well. In FIG. 1, the P-type semiconductor substrate 130 is used as an exemplification. An NMOS transistor (NMOSFET) 110 and an N-type capacitor structure 120 are disposed in the P-type semiconductor substrate 130. The NMOS transistor 110 comprises a first dielectric layer 111 disposed on the P-type semiconductor substrate 130; a first conduction gate 112 stacked on the first dielectric layer 111; and two ion-doped regions disposed in the P-type semiconductor substrate 130 to respectively function as a source 113 and a drain 114, wherein a channel 115 is formed between the source 113 and the drain 114. The source 113 and the drain 114 have different widths. The N-type capacitor structure 120 uses the edge of the drain 114 to serve as a capacitor and control a floating gate, jointly functioning as a single floating gate of the non-volatile memory 100. Specifically, the edge of the drain 114 is in the middle of the floating gate. Wherein, the N-type capacitor structure 120 has a lightly-doped region 116 between the drain 114 and the floating gate, and the ion-doped regions and the lightly-doped region 116 are N-type ion-doped regions.

[0027] In the invention, the widths of the source 113 and the drain 114 are the side lengths along a horizontal axis direction (i.e. the direction parallel to the direction from the source 113 to the drain 114), as shown in FIG. 1. It is shown that the width W.sub.d of the drain 114 is larger than the width W.sub.s of the source 113 in the embodiment. Moreover, the lengths of the source 113 and the drain 114 may also be different. As shown in FIG. 2, the length L.sub.d of the ion doping region of the drain 114 is larger than the length L.sub.s of the ion doping region of the source 113 in the embodiment. In addition, as shown in FIG. 3, the length L.sub.d of the ion doping region of the drain 114 is larger than the length L.sub.s of the ion doping region of the source 113 in another embodiment, and a tilt angle is presented between the opposite sides of the ion doping regions of the drain 114 and the source 113.

[0028] The single-gate multiple-time programming non-volatile memory 100 is a three-terminal structure. As shown in FIG. 4, the three terminals are respectively a source, a drain and a substrate. A substrate voltage V.sub.sub, a source voltage V.sub.s and a drain voltage V.sub.d are respectively applied to the P-type semiconductor substrate 130, the source 113 and the drain 114. The single-gate multiple-time programming non-volatile memory 100 operates as follows:

[0029] In writing, [0030] a. V.sub.sub=ground (0); [0031] b. V.sub.d=V.sub.s=HV (High Voltage); [0032] V.sub.d=HV (High Voltage), and V.sub.s=MV (Medium Voltage) or LV (Low Voltage); or [0033] V.sub.d=MV (Medium Voltage), and V.sub.s=LV (Low Voltage) or ground (0).

[0034] In erasing, [0035] a. V.sub.sub=ground (0); [0036] b. V.sub.d=HV (High Voltage), and V.sub.s=ground (0); [0037] V.sub.d=HV (High Voltage), and V.sub.s=floating voltage; [0038] V.sub.s=HV (High Voltage), and V.sub.d=ground (0); or [0039] V.sub.s=HV (High Voltage), and V.sub.d=floating voltage.

[0040] Furthermore, the ranges of High Voltage, Medium Voltage and Low Voltage proposed in the above bias conditions are specifically described. The High Voltage refers to subtract the threshold voltage V.sub.t of the transistor from the breakdown voltage of the drain to the source. The Medium Voltage refers to half of the breakdown voltage of the drain to the source. The Low Voltage refers to one quarter of the breakdown voltage of the drain to the source.

[0041] The structure of FIG. 1 is disposed in a P-type silicon wafer. The isolation structure is disposed with a standard isolation module process. After the basic isolation structure is completed, the channel of the NMOS transistor is disposed with an ion implant process. After the dielectric layers of the first conduction gate is grown, polysilicon is deposited. Next, a photolithographic process is used to pattern the polysilicon to form the single floating gate. Next, another ion implant process is undertaken to form the electrodes of the NMOS transistorthe drain and source. After metallization, the fabrication of a great number of the single-gate multiple-time programming non-volatile memory is completed.

[0042] In conclusion, compared with a conventional single-gate programming non-volatile memory having high cost due to complicated control, the single-gate multiple-time programming non-volatile memory and the operation method thereof of the present invention can greatly reduce the lengths of control lines, areas and production cost of the non-volatile memory on account of simple operation and the least elements and the least control voltages.

[0043] The embodiments described above are only to exemplify the present invention but not to limit the scope of the present invention. Therefore, any equivalent modification or variation according to the shapes, structures, features, or spirit disclosed by the present invention is to be also included within the scope of the present invention.