3D stack of electronic chips

Abstract

A 3D stack includes a first chip having first interconnection pads of rectangular section, the first interconnection pads having a first pitch in a first direction and a second pitch in a second direction perpendicular to the first direction; and a second chip having second interconnection pads, the second interconnection pads having a third pitch in the first direction and a fourth pitch in the second direction, at least one part of the second interconnection pads being in contact with the first interconnection pads to electrically couple the first and second chips. The first interconnection pads have a first dimension in the first direction equal to m times the third pitch and a second dimension in the second direction equal to n times the fourth pitch. The first interconnection pads are separated two by two in the first direction by a first distance equal to q times the third pitch.

Claims

1. A 3D stack of electronic chips comprising: a first chip having on a first face a plurality of first interconnection pads of rectangular section, arranged in lines and in columns, the columns of first interconnection pads having a first pitch in a first direction and the lines of first interconnection pads having a second pitch in a second direction perpendicular to the first direction; a second chip having, on a second face bonded to the first face of the first chip, a plurality of second interconnection pads arranged in lines and in columns, the columns of second interconnection pads having a third pitch in the first direction and the lines of second interconnection pads having a fourth pitch in the second direction, at least one part of the second interconnection pads being in contact with the first interconnection pads to electrically couple the first and second chips; wherein: the first interconnection pads have a first dimension in the first direction equal to m times the third pitch, where m is a non-zero natural integer, and a second dimension in the second direction equal to n times the fourth pitch, where n is a non-zero natural integer; the first interconnection pads belonging to a same line and to two consecutive columns are separated in the first direction by a first distance equal to q times the third pitch, where q is a non-zero natural integer; the first interconnection pads belonging to a same column and to two consecutive lines are separated in the second direction by a second distance equal to r times the fourth pitch, where r is a non-zero natural integer; the second interconnection pads are interconnected in a plurality of groups, each group comprising a number N of interconnected second interconnection pads such that:
N=(m+q)(n+r), each group being electrically connected to a first interconnection pad by at least one of the second interconnection pads of the group.

2. The 3D stack according to claim 1, wherein the first dimension of the first interconnection pads is further equal to the first pitch divided by 2 and wherein the second dimension of the first interconnection pads is further equal to the second pitch divided by 2.

3. The 3D stack according to claim 2, wherein the first pitch is equal to the second pitch.

4. The 3D stack according to claim 1 wherein the second interconnection pads have a rectangular, round or octagonal section.

5. The 3D stack according to claim 1, wherein the second interconnection pads have a first dimension in the first direction equal to the third pitch divided by 2 and a second dimension in the second direction equal to the fourth pitch divided by 2.

6. The 3D stack according to claim 5, wherein the third pitch is equal to the fourth pitch.

7. The 3D stack according to claim 1, wherein: the first dimension of the first interconnection pads is equal to the third pitch; the second dimension of the first interconnection pads is equal to the fourth pitch; the first distance is equal to the third pitch; and the second distance is equal to the fourth pitch.

8. The 3D stack according to claim 1, wherein: the first dimension of the first interconnection pads is equal to two times the third pitch; the second dimension of the first interconnection pads is equal to two times the fourth pitch; the first distance is equal to two times the third pitch; and the second distance is equal to two times the fourth pitch.

9. The 3D stack according to claim 1, wherein the second chip comprises a layer of active components and a plurality of metal interconnection levels connecting the active components, and wherein at least one of the metal interconnection levels serves to interconnect the N second interconnection pads of each group.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) Other characteristics and benefits of the invention will become clearer from the description that is given thereof below, for indicative purposes and in no way limiting, while referring to the appended figures, among which:

(2) FIG. 1 shows a 3D circuit integrating a first example of stack of electronic chips according to the prior art;

(3) FIG. 2 represents a 3D interconnection structure employed in a second example of stack of electronic chips according to the prior art;

(4) FIG. 3 represents a 3D interconnection structure employed in a third example of stack of electronic chips according to the prior art;

(5) FIG. 4 represents a 3D interconnection structure employed in a stack of electronic chips according to a first embodiment of the invention;

(6) FIGS. 5A and 5B illustrate the 3D interconnection structure of FIG. 4 in misalignment situations of different values;

(7) FIG. 6 represents a 3D interconnection structure employed in a stack of electronic chips according to a second embodiment of the invention;

(8) FIG. 7 represents a 3D interconnection structure employed in a stack of electronic chips according to a third embodiment of the invention; and

(9) FIG. 8 represents a 3D interconnection structure employed in a stack of electronic chips according to a fourth embodiment of the invention.

(10) For greater clarity, identical or similar elements are marked by identical reference signs in all of the figures.

DETAILED DESCRIPTION

(11) In the following description, 3D interconnection structure designates all of the interconnection pads that make it possible to electrically connect two electronic chips stacked (vertically) one on the other. These interconnection pads are present on one face of each electronic chip, which may be the front face or the back face. The front face of an electronic chip designates the face of a substrate, generally made of a semiconductor material such as silicon, on which are formed active components, for example transistors, then (if applicable) passive components and metal interconnection levels. The back face of the electronic chip is the face of the substrate opposite to the front face.

(12) The two electronic chips are bonded together, in an embodiment by a direct bonding technique (i.e. without introducing an intermediate compoundsuch as an adhesive, a wax or a low melting point alloyat the level of the bonding interface), for example of metal-metal type or of hybrid metal-dielectric type. The bonding may be carried out according to different approaches: front face against front face, back face against back face or front face against back face. The two faces that are bonded together are substantially flat, their topology generally not exceeding 15 nm. No space then exists between the chips after the bonding thereof, unlike other assembly technologies (typically by microbumps or micro-pillars), which have an important topology (of the order of several m) and require the introduction of a polymer between the chips.

(13) FIG. 4 is a partial sectional view of a stack of electronic chips according to a first embodiment of the invention. This view is taken at the level of a bonding interface between two electronic chips and schematically represents a first 3D interconnection structure 400 ensuring the electrical connection between the two electronic chips.

(14) The 3D interconnection structure 400 comprises a plurality of first identical interconnection pads 401a belonging to a first electronic chip and a plurality of second identical interconnection pads 401b belonging to a second electronic chip. The face of the first chip, on which the first interconnection pads 401a emerge, is bonded to the face of the second chip revealing the second interconnection pads 401b. The first interconnection pads 401a and the second interconnection pads 401b are in an embodiment made of metal, for example copper or aluminium, and contribute to the bonding of the first and second chips.

(15) The second interconnection pads 401b of the second chip, as well as the first interconnection pads 401a of the first chip, are spaced apart from each other by electrically insulating portions 402, for example made of silicon oxide. The bonding surface of each chip is thus composed of metal interconnection pads surrounded by a dielectric material.

(16) The first interconnection pads 401a of the first chip are distinct and arranged in lines and in columns, in the form of a matrix or mesh. The columns of first pads 401a have a first pitch P.sub.X1 in a first direction X of the sectional plane of FIG. 4. This first pitch P.sub.X1 is equal to the distance that separates the centres of two pads 401a belonging to a same line and to two consecutive columns. In the same way, the lines of first pads 401a have a second pitch P.sub.Y1 in a second direction Y of the plane, perpendicular to the first direction X. This second pitch P.sub.Y1 is equal to the distance that separates the centres of two pads 401a belonging to a same column and to two consecutive lines. In other words, the first interconnection pads 401a are reproduced in a periodic manner on the surface of the first chip, and this is so in the two directions X and Y.

(17) The second interconnection pads 401b of the second chip are also distinct and arranged in lines and in columns. The columns of second pads 401b are repeated in the first direction X according to a third pitch P.sub.X2, whereas the lines of second pads 401b are repeated in the second direction Y according to a fourth pitch P.sub.Y2. The third and fourth pitches P.sub.X2-P.sub.Y2 are defined in the same way as the first and second pitches P.sub.X1-P.sub.Y1, with respect to the centres of the second pads 401b.

(18) The number of lines and columns, and thus interconnection pads on the surface of each chip, depends on the desired interconnection density and the surface area of the bonding surface of the chips. In order not to clutter FIG. 4 unduly, only three columns and three lines of first pads 401a are represented and only six columns and six lines of second pads 401b are represented.

(19) As illustrated in FIG. 4, the first pitch P.sub.X1 (pitch along X of the first pads 401a) may be different from the second pitch P.sub.Y1 (pitch along Y of the first pads 401a) and the third pitch P.sub.X2 (pitch along X of the second pads 401b) may be different from the fourth pitch P.sub.Y2 (pitch along Y of the second pads 401b). The first pads 401a and the second pads 402b are then in the form of rectangular meshes.

(20) The first interconnection pads 401a have a section, in the plane of the bonding face, of rectangular shape. The dimensions of the first pads 401a in the first direction X and in the second direction Y are noted respectively A.sub.X1 and A.sub.Y1.

(21) The section of the second interconnection pads 401b (in the plane of the bonding face) may be of any shape, for example rectangular (cf. FIG. 4), round or octagonal. The dimensions of the second pads 401b in the first direction X and in the second direction Y are noted respectively A.sub.X2 and A.sub.Y2. The distance that separates in the direction X two consecutive second pads 401b belonging to a same line is noted D.sub.X2 and the distance that separates in the direction Y two consecutive second pads 401b belonging to a same column is noted D.sub.Y2.

(22) In this first embodiment, the dimension A.sub.X1 along X of the first pads 401a is equal to the third pitch P.sub.X2 and the dimension A.sub.Y1 along Y of the first pads 401a is equal to the fourth pitch P.sub.Y2. Moreover, the distance D.sub.X1 that separates in the direction X two first consecutive pads 401a of a same line, that is to say the width of the insulating portion 402 separating two consecutive columns of first pads 401a, is equal to the third pitch P.sub.X2. Similarly, the distance D.sub.Y1 that separates in the direction Y two consecutive first pads 401a of a same column, that is to say the width of the insulating portion 402 separating two consecutive lines of first pads 401a, is equal to the fourth pitch P.sub.Y2.

(23) Although separated physically, the second interconnection pads 401b are interconnected by group of N, in an embodiment by means of metal tracks 403 situated in a plane parallel to the bonding face of the second chip. Each group of second interconnection pads 401b is electrically connected to a single first interconnection pad 401a. To produce this electrical connection, at least one second pad 401b of each group is in direct contact with the first pad 401a associated with the group. The number N of second pads 401b in the groups varies as a function of the dimensions A.sub.X1-A.sub.Y1 of the first pads 401a and the spacings D.sub.X1-D.sub.Y1 between the first pads 401a. As an example, in the embodiment of FIG. 4, each first pad 401a is connected to four interconnected (N=4) second pads 401b.

(24) In an embodiment, the second chip comprises several metal interconnection levels (belonging to a functional block or set of technological levels called Back End Of Line or BEOL) connecting active components (belonging to a functional block called Front End Of Line or FEOL), for example transistors. At least one of the metal interconnection levels is beneficially used to interconnect the N second interconnection pads of each group. In other words, the metal tracks 403 connecting the second pads 401b are added to this metal interconnection level. Beneficially, the metal tracks 403 are added to the two final metal interconnection levels (i.e. the furthest from the active components), of which the interconnection density is lower. These two latter levels are normally used to produce the power delivery network of the chip and the creation of additional metal tracks 403 does not impact the performances of this delivery network.

(25) A particularity of the interconnection structure 400 is that the contact surface S between each first pad 401a and the N second pads 401b of the associated group is independent of the misalignment related to the bonding of the first and second chips, as long as this misalignment does not exceed (along X and along Y) the threshold values delimiting a tolerance interval (or window).

(26) The configuration shown in FIG. 4 is that of a perfect alignment between the two chips (zero misalignment along X and along Y). Each first pad 401a is centred on the group of second pads 401b to which it is connected. The contact surface S is distributed in a uniform manner over the four second pads 401b of the group. It is equal to the surface area of a second pad 401b.

(27) FIGS. 5A and 5B show two other configurations of the interconnection structure 400 (after bonding of the chips), in which the misalignment between the chips is not zero.

(28) In the configuration of FIG. 5A, that of a moderate misalignment along X and along Y, the contact surface S is still distributed over the four pads of the group, but no longer in a uniform manner. However, the contact surface S is nevertheless identical to the configuration of FIG. 4, because the sum of the contact surfaces from first pad 401a to second pad 401b (so-called individual contact surfaces) is equal to the surface area of a second pad 401b. In the configuration of FIG. 5B, that of an extreme misalignment along X and along Y (at the limit of the tolerance intervals), the contact between the first pad 401a and the group of second pads 401b is no longer limited only to a single second pad 401b, over its whole surface area. The contact surface S is thus always the same.

(29) This constant contact surface, whatever the value of the misalignment (within the tolerance interval) between the two chips, makes it possible to homogenise the electrical performances from one 3D stack to the next, notably their electrical resistance. This is valid whatever the transfer technique employed: die-to-die, die-to-wafer or wafer-to-wafer (the misalignment between the chips may vary from one spot to the other of the wafers, notably between the centre and the edge of the wafers).

(30) A constant contact surface also implies an identical bonding energy between the different stacks, which is particularly beneficial in the case of die-to-wafer and wafer-to-wafer transfer techniques because it is next necessary to cut the stacks. The reliability of the 3D circuits from a mechanical viewpoint is thus improved overall.

(31) Finally, it is observed that the distribution of metal on the surface of the second chip (second interconnection pads 401b) is much better in the interconnection structure 400 than that obtained (for the upper chip) in the interconnection structure of the prior art (cf. FIG. 2, interconnection pads 104a). This is due to the fact that each first pad 401a is associated in the interconnection structure 400 with a multitude (at least 4) of second pads 401b, instead of a single one in the prior art. Thanks to this better distribution of metal, the manufacture of the second chip (before bonding) is facilitated, in particular the step of planarization of its bonding face by chemical mechanical planarization.

(32) FIG. 6 schematically represents a second 3D interconnection structure 600 belonging to a stack of chips according to a second embodiment of the invention.

(33) The second interconnection structure 600 represents a particular case of the first interconnection structure 400, because the first and second interconnection pads 401a-401b have a section of square shape. Consequently, the dimension A.sub.X1 along X of the first pads 401a is equal to the dimension A.sub.Y1 along Y of the first pads 401a and the dimension A.sub.X2 along X of the second pads 401b is equal to the dimension A.sub.Y2 along Y of the second pads 401b.

(34) As in the structure 400 of FIG. 4, the dimension A.sub.X1 along X of the first pads 401a is beneficially equal to the first pitch P.sub.X1 divided by two and the dimension A.sub.Y1 along Y of the first pads 401a is beneficially equal to the second pitch P.sub.Y1 divided by two. The density of metal d.sub.1 of the first chip, which represents the surface of the first pads 401a over the total bonding surface, is then equal to 25%:

(35) $d_1=\frac{A_{X1}{A}_{Y1}}{P_{X1}{P}_{Y1}}=\frac{P_{X1}\text{/}2P_{Y1}\text{/}2}{P_{X1}{P}_{Y1}}=0.25$

(36) A metal density d.sub.1 of 25% represents an optimal solution for facilitating the preparation of the first chip, and more specifically the step of chemical mechanical planarization of its bonding face, because the portions of metal (pads 401a) along X and along Y are of same width as the dielectric portions (402).

(37) It results from these geometric considerations that the first pitch P.sub.X1 is equal to the second pitch P.sub.Y1 (the mesh of first pads 401a is thus itself square). The distribution of metal is then the same in the direction of the lines (X) and in the direction of the columns (Y).

(38) In the same beneficial manner, the dimension A.sub.X2 along X of the second pads 401b and the dimension A.sub.Y2 along Y of the second pads 401b are equal respectively to the third pitch P.sub.X2 divided by two and to the fourth pitch P.sub.Y2 divided by two. The density of metal d.sub.2 on the surface of the second chip is then itself also equal to 25%:

(39) $d_2=\frac{A_{X2}{A}_{Y2}}{P_{X2}{P}_{Y2}}=\frac{P_{X2}\text{/}2P_{Y2}\text{/}2}{P_{X2}{P}_{Y2}}=0.25$

(40) The benefits in terms of manufacturing described for the first chip are thus also valid for the second chip. As a comparison, the density of metal of one of the two chips (the upper chip) in the interconnection structure of the prior art (cf. FIG. 2) is only around 6%.

(41) In view of these geometric choices, the third pitch P.sub.X2 is equal to the fourth pitch P.sub.Y2 (the mesh of second interconnection pads 401b is thus itself also square).

(42) The maximum allowed misalignment along X, hereafter noted F.sub.X, in the interconnection structure 600 is equal to half the dimension A.sub.X2 of the second pads 401b plus the distance D.sub.X2 between two consecutive second pads 401b. Indeed, a first pad 401a should not enter into contact with the second pads 401b of the adjacent groups. The maximum allowed misalignment along X is thus here equal to of the third pitch P.sub.X2 (because A.sub.X2=D.sub.X2=P.sub.X2/2) or instead of the first pitch P.sub.X1 (because P.sub.X1=A.sub.X1+D.sub.X1=2*P.sub.X2):

(43) $F_X=\left(\frac{A_{X2}}{2}+D_{X2}\right)=\frac{3}{4}{P}_{X2}=\frac{3}{8}{P}_{X1}$

(44) The tolerance window, represented by the zone 601 in FIG. 6, thus has a length along X equal to 75% of the first pitch P.sub.X1.

(45) The maximum allowed misalignment along Y (noted F.sub.Y) is identical to that allowed along X (because the distances, dimensions and pitch along Y are the same as along X), i.e. a tolerance window of width along Y equal to 75% of the first pitch P.sub.X1.

(46) As a comparison, in the interconnection structure of the prior art (FIG. 2), the tolerance window is only 50% of the pitch (2*0.9 m/3.6 m=0.5), along X and along Y.

(47) For a same (first) pitch (that is to say a same functional 3D interconnection density) the interconnection structure 600 according to the invention thus tolerates a greater misalignment than the interconnection structure of the prior art.

(48) FIG. 7 schematically represents a third 3D interconnection structure 700 belonging to a stack of chips according to a third embodiment of the invention.

(49) The third interconnection structure 700 differs from the second interconnection structure 600 uniquely in the shape of the second interconnection pads 401b. The section of the second pads 401b is not in fact limited to a rectangular (FIG. 4) or square (FIG. 6) shape. A constant contact surface S (whatever the misalignment within the tolerance interval) is in fact obtained even if the section of the second pads 401b is not symmetrical along X and along Y. In the embodiment of FIG. 7, the contact surface S is still equal to the surface area of a second pad 401b.

(50) In a fourth interconnection structure 800 represented by FIG. 8, the first and second pads 401a-401b are of square section and organised according to meshes that are also square. The first pitch P.sub.X1 is thus equal to the second pitch P.sub.Y1 and the third pitch P.sub.X2 is equal to the fourth pitch P.sub.Y2. The dimensions A.sub.X1 (along X) and A.sub.Y1 (along Y) of the first pads 401a, as well as the distances D.sub.X1 (along X) and D.sub.Y1 (along Y) that separates the first pads 401a, are further equal to two times the third (or fourth) pitches P.sub.X2 (=P.sub.Y2). The dimensions A.sub.X2 (along X) and A.sub.Y2 (along Y) of the second pads 401b are equal to the third pitch P.sub.X2 divided by 2. The metal densities d.sub.1 and d.sub.2 are still consequently equal to 25%. The number N of interconnected second pads in each group is equal to 16 (they are distributed according to a 44 matrix). The contact surface S is constant and equal to the surface area of four second pads 401b, whatever the value of the misalignment within the tolerance interval.

(51) The maximum allowed misalignments along X (F.sub.X) and along Y (F.sub.Y) are equal to one times the third pitch P.sub.X2 plus half the distance D.sub.X2 between two consecutive second pads 401b, i.e. here 5/4 of the third pitch P.sub.X2 or instead 5/16 of the first pitch P.sub.X1 (because P.sub.X1=A.sub.X1+D.sub.X1=4*P.sub.X2):

(52) $F_X=F_Y=\left(\frac{D_{X2}}{2}+P_{X2}\right)=\frac{5}{4}{P}_{X2}==\frac{5}{16}{P}_{X1}$

(53) The tolerance window, represented by the zone 801 in FIG. 8, thus has a length along X and a width along Y equal to 62.5% of the first pitch P.sub.X1. The tolerance window of the fourth interconnection structure 800 is thus less extended than that of the second interconnection structure 600 (F.sub.X=F.sub.Y=75%) but still more extended than the tolerance window of the interconnection structure according to the prior art.

(54) More generally, a constant contact surface S may be obtained with an interconnection structure of the type of FIG. 4 from the moment that it meets the following criteria: the dimension A.sub.X1 along X of the first pads 401a is equal to m times the third pitch P.sub.X2, where m is a first non-zero natural integer; the dimension A.sub.Y1 along Y of the first pads 401a is equal to n times the fourth pitch P.sub.Y2, where n is a second non-zero natural integer; the distance D.sub.X1 that separates in the direction X two consecutive first pads 401a (of a same line) is equal to q times the third pitch P.sub.X2, where q is a third non-zero natural integer; the distance D.sub.Y1 that separates in the direction Y two consecutive first pads 401a is equal to r times the fourth pitch P.sub.Y2, where r is a fourth non-zero natural integer.

(55) The natural integers m, n, q and r may be equal or different to each other.

(56) The number N of interconnected second interconnection pads 401b in each group satisfies the following equation:
N=(m+q)(n+r)

(57) The contact surface S between each first pad 401a and the N second pads 401b of the associated group is given by the following formula:

(58) $S=4\left(\frac{S_{\mathrm{pad}}}{4}\right)+2\left(m-1\right)\left(\frac{S_{\mathrm{pad}}}{2}\right)+2\left(n-1\right)\left(\frac{S_{\mathrm{pad}}}{2}\right)+\left(m-1\right)\left(n-1\right)S_{\mathrm{pad}}=mn{S}_{\mathrm{pad}}$
with S.sub.pad the surface area of a second interconnection pad 401b.

(59) In the first embodiment (FIG. 4), the second embodiment (FIG. 6) and the third embodiment (FIG. 7), the natural integers m, n, q and r are all equal to 1 (A.sub.X1=P.sub.X2, A.sub.Y1=P.sub.Y2, D.sub.X1=P.sub.X2 and D.sub.Y1=P.sub.Y2). As indicated previously, the number N of second pads 401b in each group is equal to 4 (N=4) and the contact surface S is equal to the surface area S.sub.pad of a second interconnection pad 401b (S=S.sub.pad).

(60) In the fourth embodiment (FIG. 8), the natural integers m, n, q and r are all equal to 2 (A.sub.X1=2*P.sub.X2, A.sub.Y1=2*P.sub.Y2, D.sub.X1=2*P.sub.X2 and D.sub.Y1=2*P.sub.Y2). The number N of second pads 401b in each group is equal to 16 (N=16), the contact surface area S is equal to the surface area of four second pads 401b (S=4*S.sub.pad).

(61) The interconnection structures 400, 600, 700 and 800 described below tolerate, apart from a misalignment related to the bonding of the chips (and represented by FIGS. 5A-5B), an offset of the interconnection pads within a single chip. In other words, the contact surface S between a first pad 401a and a group of second pads 401b remains constant even if the distance between the pads 401a or 401b varies slightly within the matrix. This offset is variable as a function of the position on the wafer (low between two neighbouring pads, but may be important between two pads far apart on the wafer). It is for example due to an expansion of the materials or to misalignments during the manufacturing steps of the chips (photolithography steps notably). The electrical performances of the 3D interconnections, and notably their electrical resistance, are thus homogeneous within a same stack. For the same reason, the bonding energy is homogeneous within a same stack, which improves the mechanical strength and the reliability of the stack.

(62) These interconnection structures can be used whatever the value of the pitch of the first pads 401a, called functional pitch because it determines the density of the 3D interconnections in the stack. They prove however particularly beneficial for a functional pitch less than 2 m. Indeed, with such a pitch, the 3D interconnection pads and the metal lines of the upper interconnection levels have very similar dimensions. The interest of having a constant contact surface S, and thus a homogeneous electrical resistance, is thus very high. Conversely, when the functional pitch is of the order of 4-5 m or more, the 3D interconnection pads are larger and the resistance of the metal lines is great compared to that of the 3D interconnection pads. The variation in the contact surface S then influences to a lesser extent the overall electrical performances of the interconnections that connect the active components of the two chips (3D interconnections, metal lines of the interconnection levels and vias between the levels).

(63) Many variants and modifications of the stack of electronic chips according to the invention will become clear to the man skilled in the art. The characteristics of the interconnection structures 400, 600, 700 and 800, described through FIGS. 4, 6 to 8, may be easily combined together. It is notably possible to combine the characteristics relative to the shape of the second pads 401b, to the pitch along X and along Y of the pads 401a-401b and to the dimensions of the pads 401a-401b with respect to the pitch, to define new 3D interconnection structures benefiting from the same benefits.

(64) The stack of electronic chips according to the invention comprises at least the first and second electronic chips. The first chip provided with the first interconnection pads 401a may be arranged on the second chip provided with the second interconnection pads 401b, or vice versa. A stack of more than two electronic chips comprises more than one 3D interconnection structure and at least one of the electronic chips has the interconnection pads on its two faces (front face and back face).