Dielectric resonant antenna based NMOSFET terahertz detector and method

Abstract

The present disclosure discloses a dielectric resonant antenna based NMOSFET terahertz detector, comprising an on-chip dielectric resonant terahertz antenna, wherein the on-chip dielectric resonant terahertz antenna is connected to a matching network, the matching network is connected to a source of an NMOSFET, and a gate of the NMOSFET is sequentially connected to a first bias resistor and a first bias voltage, a third transmission line is connected between the first bias resistor and the gate, a drain of the NMOSFET is connected to a first DC blocking capacitor, the other end of the first DC blocking capacitor is connected to a low noise preamplifier, a second bias resistor and a second bias voltage are connected in parallel between the first DC blocking capacitor and the low noise preamplifier, and the low noise preamplifier is further provided with a voltage feedback loop. The present disclosure also discloses a design method for the same.

Claims

1. A dielectric resonant antenna based N-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET) terahertz detector comprising an on-chip dielectric resonant terahertz antenna, wherein the on-chip dielectric resonant terahertz antenna is connected to a matching network, the matching network is connected to a source of an NMOSFET, wherein the matching network comprises a first transmission line connected to the on-chip dielectric resonant terahertz antenna and the source respectively at both ends, a middle portion of the first transmission line is connected to one end of a second transmission line, and the other end of the second transmission line is grounded, wherein a gate of the NMOSFET is sequentially connected to a first bias resistor and a first bias voltage, a third transmission line is connected between the first bias resistor and the gate, a drain of the NMOSFET is connected to a first Direct Current (DC) blocking capacitor, the other end of the first DC blocking capacitor is connected to a low noise preamplifier, a second bias resistor and a second bias voltage are further connected in parallel between the first DC blocking capacitor and the low noise preamplifier, and the low noise preamplifier is further provided with a voltage feedback loop.

2. The dielectric resonant antenna based NMOSFET terahertz detector of claim 1, wherein the on-chip dielectric resonant terahertz antenna comprises an on-chip H-shaped slot structure and a rectangular dielectric resonator block connected to the on-chip H-shaped slot structure at the surface by an insulating adhesive layer.

3. The dielectric resonant antenna based NMOSFET terahertz detector of claim 2, wherein the on-chip H-shaped slot structures are formed on a surface of an integrated process top layer metal and is located within a metal cavity formed by stacking intermediate layer metals, other than the integrated process top layer metal and an integrated process bottom layer metal in an integrated process, and metal vias.

4. The dielectric resonant antenna based NMOSFET terahertz detector of claim 3, wherein the on-chip H-shaped slot structure comprises a left vertical slot and a right vertical slot arranged in parallel, opposite sides of the left vertical slot and the right vertical slot are connected to an inverted L-shaped left side slot and right side slot, respectively.

5. The dielectric resonant antenna based NMOSFET terahertz detector of claim 4, wherein a horizontal portion of the left side slot is connected in the middle of the left vertical slot, a horizontal portion of the right side slot is connected in the middle of the right vertical slot, and vertical portions of the left side slot and the right side slot are parallel to each other and constitute two lead-out slots for connecting the antenna to an outside structure.

6. The dielectric resonant antenna based NMOSFET terahertz detector of claim 1, wherein the voltage feedback loop comprises a first resistor connected to two ends of the low noise preamplifier, a left end of the first resistor connected to a negative terminal of the low noise preamplifier is sequentially connected to a second resistor, a second DC blocking capacitor and the ground, and a right end of the first resistor is also sequentially connected to a third DC blocking capacitor and the ground.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In order to more clearly illustrate the technical solutions in embodiments of the present disclosure or the prior art, the accompanying drawings needed to be used in the description of the embodiments or the prior art will be briefly described below. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and other accompanying drawings can be obtained by ordinary persons skilled in the art from the structures illustrated in these accompanying drawings without any inventive efforts.

(2) FIG. 1 is a schematic structural view of a dielectric resonant antenna based NMOSFET terahertz detector according to the present disclosure;

(3) FIG. 2 is a schematic structural view of an on-chip dielectric resonant terahertz antenna according to the present disclosure;

(4) FIG. 3 is a schematic structural view of a rectangular dielectric resonator block according to the present disclosure;

(5) FIG. 4 is a schematic structural view of an on-chip H-shaped slot structure according to the present disclosure;

(6) FIG. 5 is a graph showing the return loss S11 of an on-chip dielectric resonant terahertz antenna according to the present disclosure as a function of frequency;

(7) FIG. 6 is a graph showing the gain of an on-chip dielectric resonant terahertz antenna according to the present disclosure as a function of frequency;

(8) FIG. 7 is a radiation pattern of an on-chip dielectric resonant terahertz antenna according to the present disclosure.

DESCRIPTION OF THE REFERENCE NUMERALS

(9) TABLE-US-00001 No. Name No. Name 1 First bias voltage 43 Rectangular dielectric 2 First bias resistor resonator block 3 NMOSFET 44 Top layer metal 31 Source 5 Matching network 32 Drain 51 First transmission line 33 Gate 52 Second transmission 4 On-chip dielectric line resonant 6 First DC blocking terahertz capacitor antenna 7 Second bias voltage 41 On-chip H-shaped 8 Second bias resistor slot structure 9 Low noise preamplifier 411 Left vertical slot 10 First resistor 412 Right vertical slot 11 Second resistor 413 Left side slot 12 Second DC blocking 414 Right side slot capacitor 415 Metal cavity 13 Grounding 416 Bottom layer 14 Third DC blocking metal capacitor 42 Insulating adhesive 15 Third transmission layer line

(10) The implementation, functional features and advantages of the present disclosure will be further described in the light of embodiments with reference to the accompanying drawings.

DETAILED DESCRIPTION

(11) The technical solutions according to the embodiments of the present disclosure are clearly and completely described in the following with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, and not all the embodiments. All other embodiments obtained by ordinary persons skilled in the art based on the embodiments of the present disclosure without creative efforts are within the scope of the present disclosure.

(12) It should be noted that if there is a directional indication (such as up, down, left, right, front, back, . . . ) mentioned in the embodiments of the present disclosure, the directional indication is only used to explain the relative positional relationship between components, motion status, and the like in a specific posture (as shown in the drawing), and if the specific posture changes, the directional indication also changes accordingly.

(13) In addition, if there is a description of first, second, etc. in the embodiments of the present disclosure, the description of the first, second, etc. is used for the purpose of illustration only, and is not to be construed as an its relative importance or implicit indication of the number of technical features indicated. Thus, the features defined by first or second may include at least one of the features, either explicitly or implicitly. In addition, the technical solutions among the various embodiments may be combined with each other, but must be based on the enablement of those skilled in the art, and when the combination of the technical solutions is contradictory or impossible to implement, it should be considered that such combination of the technical solutions does not exist, and is not within the scope of protection claimed by the present disclosure.

(14) The present disclosure proposes a dielectric resonant antenna based NMOSFET terahertz detector and a design method for the on-chip dielectric resonant terahertz antenna.

(15) Referring to FIG. 1, in an embodiment of the present disclosure, the dielectric resonant antenna based NMOSFET terahertz detector comprises an on-chip dielectric resonant terahertz antenna 4. The on-chip dielectric resonant terahertz antenna 4 is connected to a matching network 5, and the matching network 5 is further connected to a source 31 of an NMOSFET 3. A gate 33 of the NMOSFET 3 is sequentially connected to a first bias resistor 2 and a first bias voltage 1. An open-end quarter-wavelength third transmission line 15 is connected between the gate 33 and the first bias resistor 2. A drain 32 of the NMOSFET 3 is connected to a first DC blocking capacitor 6, and the other end of the first DC blocking capacitor 6 is connected to a low noise preamplifier 9. A second bias resistor 8 is connected between the first DC blocking capacitor 6 and the low noise preamplifier 9, and the other end of the second bias resistor 8 is connected to the first bias voltage 7 so as to provide a DC power supply to the low noise preamplifier 9. In addition, the low noise preamplifier 9 is also connected to a voltage feedback loop.

(16) Referring to FIG. 2 to FIG. 4, specifically, the on-chip dielectric resonant terahertz antenna 4 of the present embodiment comprises an on-chip H-shaped slot structure 41 and a rectangular dielectric resonator block 43, and the rectangular dielectric resonator block 43 is disposed on a surface of the on-chip H-shaped slot structure 41 through the insulating adhesive layer 42. The on-chip H-shaped slot structure 41 of the present embodiment is formed on a surface of an integrated process top layer metal 44 and is located within a metal cavity 415 formed by stacking intermediate layer metals, other than the integrated process top layer metal 44 and an integrated process bottom layer metal 416 in an integrated process, and metal vias.

(17) Referring to FIG. 4, more specifically, the on-chip H-shaped slot structure 41 of the present embodiment comprises a left vertical slot 411 and a right vertical slot 412 arranged in parallel, opposite sides of the left vertical slot 411 and the right vertical slot 412 are connected to an inverted L-shaped left side slot 413 and right side slot 414, respectively, a horizontal portion of the left side slot 413 is connected in the middle of the left vertical slot 411, and a horizontal portion of the right side slot 414 is connected in the middle of the right vertical slot 412. Additionally, vertical portions of the left side slot 413 and the right side slot 414 are parallel to each other and constitute two lead-out slots for connecting the antenna to an outside structure.

(18) Preferably, the on-chip H-shaped slot structure 41 of the present embodiment is designed and processed using a silicon-based process so as to excite the rectangular dielectric resonator block 43 overlying it and optimize the impedance matching effect. In addition, the insulating adhesive layer 42 has good thermal stability for fixing the rectangular dielectric resonator block 43 to a surface of the on-chip excitation structure.

(19) More preferably, the rectangular dielectric resonator block 43 of the present embodiment has a larger relative dielectric constant, for example, a relative dielectric constant of >5, so that the insulating material is processed into a specific size to couple and radiate an electromagnetic field to the space. In addition, the rectangular dielectric resonance mode of the present embodiment is a TE.sub.1,3 mode. In this embodiment, the center frequency of the on-chip dielectric resonant terahertz antenna 4 is 300 GHz, and magnesium oxide having a relative dielectric constant of 9.65 is selected as the material of the rectangular dielectric resonator block. A parameter (Towerjazz SBC18H3) of the 0.18mGeSi BiCMOS process is selected to design the on-chip structure, and there are six layers of metal Metal1-Metal6 and five layers of metal vias Via1-Via5 in this process.

(20) The matching network 5 of the present embodiment is composed of two microstrip transmission lines, the first transmission line 51 and the second transmission line 52. The matching network 5 is mainly used to improve the power transmission efficiency between the antenna and the transistor, and a DC power supply is provided for the source (S) of the transistor. The left end of the microstrip first transmission line 51 is connected to the on-chip dielectric resonant terahertz antenna 4, and the right end of the microstrip first transmission line 51 is connected to the source 31 of the NMOSFET 3.

(21) The gate 33 of the NMOSFET 3 of the present embodiment is loaded with a fixed first bias voltage 1 and a first bias resistor 2, and an open-end quarter-wavelength third transmission line 53 is connected between the gate 33 of the NMOSFET and the first bias resistor 2. The open-end quarter-wavelength third transmission line 53 is mainly used to eliminate the influence of the gate DC bias on the impedance matching between the antenna and the transistor.

(22) In the present embodiment, a first DC blocking capacitor 6, a second bias voltage 7, and a second bias resistor 8 are connected between the drain 32 of the NMOSFET 3 and the forward input terminal of the low noise preamplifier 9, wherein the second bias voltage 7 and the second bias resistor 8 are used for supplying power to the low noise preamplifier 9.

(23) The voltage feedback loop of the low noise preamplifier 9 of the present embodiment is mainly composed of the first resistor 10, the second resistor 11, the second DC blocking capacitor 12 and the third DC blocking capacitor 14, wherein the gain of the low noise preamplifier 9 can be adjusted by changing the resistance values of the first resistor 10 and the second resistor 11.

(24) Referring to FIG. 1 to FIG. 7, the design of the on-chip dielectric resonant terahertz antenna specifically comprises the following design steps.

(25) 1. Design of rectangular dielectric resonator block 43. The resonant mode is in TE.sub.1,,n mode, and the dimensions of the rectangular dielectric resonator block 43 as shown in FIG. 3 can be calculated by solving the transcendental equation (1):

(26) $\begin{array}{cc}{k}_y\tan \left(\frac{k_y{W}_{\mathrm{DRA}}}{2}\right)=\sqrt{\left({\mathrm{.Math.}}_r-1\right)k_{\mathrm{mn}}^2-k_y^2}& \left(1\right)\\ k_{\mathrm{mn}}=\frac{2f_{\mathrm{mn}}}{c},k_x=m\frac{}{L_{\mathrm{DRA}}},k_z=n\frac{}{2H_{\mathrm{DRA}}},k_x^2+k_y^2+k_z^2={\mathrm{.Math.}}_r{k}_{\mathrm{mn}}^2& \left(2\right)\end{array}$
where Equations (2) is the explanation for parameters of the equation (1), wherein c is the speed of light, and f.sub.mn is the operating frequency of the rectangular dielectric resonator block in this mode. The TE.sub.1,,3 mode of high-order resonant modes is selected as the resonant mode of the rectangular dielectric resonator block 43 in the embodiment of the present disclosure, and has a higher gain than the base mode. The transcendental equation (1) is solved by programming with the mathematical software Matlab, obtaining the dimensions of the rectangular dielectric resonator block 43 at 300 GHz as: W.sub.DR=250 m, L.sub.DR=250 m, H.sub.DR=400 m.

(27) 2. Design of on-chip excitation structure. The on-chip H-shaped slot structure 41 is shown in FIG. 4. In the design process, the top layer metal Metal6 is selected to design the slot structure, while the bottom layer metal Metal1 is selected as the metal base plate to suppress the electromagnetic wave from propagating toward a high-loss silicon substrate, and the intermediate metal layer and metal vias are stacked to form a metal shield cavity around the H-shaped slot structure, to suppress electromagnetic leakage and reduce loss.

(28) The dimension parameters of the H-shaped slot structure are: l.sub.1=70 m, l.sub.2=220 m, w.sub.s=9.5 m, w.sub.1=15 m, w.sub.2=10 m, w.sub.3=10 m

(29) 3. Selection of the insulating adhesive layer 42. The insulating adhesive layer 42 is made of a thermally stable insulating adhesive having a relative dielectric constant of 2.4 and a thickness of 10 m, for bonding the rectangular dielectric resonator block 43 and the on-chip H-shaped slot structure 41.

(30) 4. Simulating the on-chip dielectric resonant terahertz antenna by using high frequency structure simulation analysis software (HFSS). FIG. 5 shows the return loss S11 of the on-chip dielectric resonant terahertz antenna 4 as a function of frequency, where the impedance matching bandwidth of the on-chip dielectric resonant terahertz antenna array at 10 dB is 15.2% (273-318 GHz). FIG. 6 shows the gain of the on-chip dielectric resonant terahertz antenna 4 as a function of frequency, where the peak gain of the on-chip dielectric resonant terahertz antenna 4 is 5.77 dBi and the gain bandwidth at 3 dB is 13.7% (270-310 GHz). The radiation pattern of the on-chip dielectric resonant terahertz antenna is shown in FIG. 7, where the radiation efficiency of the dielectric resonant antenna is 71%.

(31) The output voltage signal of the dielectric resonant antenna based NMOSFET terahertz detector of the technical solution according to the present disclosure is a DC voltage signal, and the magnitude of the DC voltage signal is proportional to the radiation intensity of the terahertz signal, so that the intensity information of the incident terahertz signal can be obtained according to the magnitude of the output voltage signal of the terahertz detector, thereby realizing terahertz detection.

(32) The above is only a preferred embodiment of the present disclosure, which is not intended to limit the scope of the disclosure. All equivalent structural alterations made by using the disclosure of the present specification and drawings, or directly or indirectly utilized in other related technical fields, in the concept of the present disclosure, are encompassed within the scope of patent protection of the present disclosure.