Vertical high-blocking III-V bipolar transistor

Abstract

A vertical high-blocking III-V bipolar transistor, which includes an emitter, a base and a collector. The emitter has a highly doped emitter semiconductor contact region of a first conductivity type and a first lattice constant. The base has a low-doped base semiconductor region of a second conductivity type and the first lattice constant. The collector has a layered low-doped collector semiconductor region of the first conductivity type with a layer thickness greater than 10 μm and the first lattice constant. The collector has a layered highly doped collector semiconductor contact region of the first conductivity type. A first metallic connecting contact layer is formed in regions being integrally connected to the emitter. A second metallic connecting contact layer is formed in regions being integrally connected to the base. A third metallic connecting contact region is formed at least in regions being arranged beneath the collector.

Claims

1. A vertical high-blocking III-V bipolar transistor comprising: an emitter comprising a highly doped emitter semiconductor contact region of a first conductivity type with a dopant concentration greater than 1.Math.10.sup.18 cm.sup.−3 and a first lattice constant; a base comprising a low-doped base semiconductor region of a second conductivity type and the first lattice constant, a dopant concentration of the low-doped base semiconductor region being less than 10.sup.17 cm.sup.−3; and a collector comprising a layered low-doped collector semiconductor region of the first conductivity type with a layer thickness greater than 10 μm and the first lattice constant, wherein the collector comprises a layered highly doped collector semiconductor contact region of the first conductivity type with a dopant concentration greater than 1.Math.10.sup.18 cm.sup.3, wherein the base and collector semiconductor regions and the emitter and collector semiconductor contact regions are arranged in the specified sequence, wherein a first connecting contact layer is integrally connected to the emitter, wherein a second connecting contact layer is integrally connected to the base, wherein a third connecting contact layer is arranged beneath the collector, and wherein the emitter semiconductor contact region, the base semiconductor region and the collector semiconductor region each comprise a III-V material.

2. The vertical III-V bipolar transistor according to claim 1, wherein the emitter includes a highly doped emitter intermediate layer of the first conductivity type, the emitter intermediate layer being arranged between the emitter semiconductor contact region and the base semiconductor region having a dopant concentration greater than 1.Math.10.sup.18 cm.sup.−3 and a first band gap energy, the base semiconductor region having a second band gap energy, and the first band gap energy being greater than the second band gap energy.

3. The vertical III-V bipolar transistor according to claim 1, wherein the collector includes a collector intermediate layer of the second conductivity type, the collector intermediate layer being arranged between the base semiconductor region and the collector semiconductor region having a dopant concentration less than 5.Math.10.sup.17 cm.sup.−3 and a third band gap energy, the base semiconductor region having a second band gap energy, and the third band gap energy being greater than the second band gap energy.

4. The vertical III-V bipolar transistor according to claim 3, wherein the base semiconductor region comprises GaAs, and the collector intermediate layer comprises InGaP or AlGaAs.

5. The vertical III-V bipolar transistor according to claim 1, wherein the collector semiconductor contact region is a substrate layer.

6. The vertical III-V bipolar transistor according to claim 1, wherein the bipolar transistor comprises a semiconductor substrate region, the semiconductor substrate region being arranged between the third connecting contact layer and the collector semiconductor contact region.

7. The vertical III-V bipolar transistor according to claim 1, wherein the bipolar transistor comprises a metamorphic buffer layer sequence of the first conductivity type, which comprises a layer thickness of more than 0.5 μm and less than 20 μm, the metamorphic buffer layer sequence having an upper side with the first lattice constant and an underside with a second lattice constant, and the metamorphic buffer layer sequence being arranged between the collector semiconductor region and the collector semiconductor contact region or beneath the collector semiconductor contact region or being designed as the collector semiconductor contact region, all semiconductor regions arranged beneath the metamorphic buffer layer sequence having the second lattice constant and the first conductivity type.

8. The vertical III-V bipolar transistor according to claim 1, wherein the first conductivity type is p and the second conductivity type is n.

9. The vertical III-V bipolar transistor according to claim 1, wherein at least the emitter is designed as a mesa structure having a first height on a surface of the base.

10. The vertical III-V bipolar transistor according to claim 9, wherein the bipolar transistor comprises a semiconductor edge region with a width B and a second height H2, the edge region extending along the edge of the surface of the base around the emitter, the first connecting contact layer and the second connecting contact layer, the second height of the semiconductor edge region being less than or equal to the first height of the emitter, and the semiconductor edge region along second height including a material corresponding to the emitter.

11. The vertical III-V bipolar transistor according to claim 1, wherein the emitter semiconductor contact region, the base semiconductor region and the collector semiconductor region each consists of a III-V material.

12. The vertical III-V bipolar transistor according to claim 1, wherein the first, second and third connecting contact layers are all metallic.

13. The vertical III-V bipolar transistor according to claim 1, wherein the first conductivity type is n and the second conductivity type is p.

14. The vertical III-V bipolar transistor according to claim 3, wherein the base semiconductor region consists of GaAs, and the collector intermediate layer consists of InGaP or AlGaAs.

15. The vertical III-V bipolar transistor according to claim 2, wherein the bipolar transistor comprises a semiconductor edge region with a width B and a height H2, the semiconductor edge region extending along the edge of the surface of the base around the emitter, the first connecting contact layer and the second connecting contact layer, the height H2 of the semiconductor edge region corresponding to a height of the emitter intermediate layer, and a material of the semiconductor edge region corresponding to a material of the emitter intermediate layer.

16. The vertical III-V bipolar transistor according to claim 1, further comprising: a base semiconductor contact region of the second conductivity type with a dopant concentration greater than 1.Math.10.sup.18 cm.sup.−3, the base semiconductor contact region extending from a first partial region of an upper side of the base semiconductor region and extending into the base semiconductor region.

17. The vertical III-V bipolar transistor according to claim 16, wherein the second connecting contact layer is connected to the base semiconductor contact region.

18. The vertical III-V bipolar transistor according to claim 2, wherein the base semiconductor region comprises GaAs, and the emitter intermediate layer comprises InGaP or AlGaAs.

19. The vertical III-V bipolar transistor according to claim 2, wherein the base semiconductor region consists of GaAs, and the emitter intermediate layer consists of InGaP or AlGaAs.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:

(2) FIG. 1 shows a cross-sectional view of a vertical high-blocking III-V bipolar transistor;

(3) FIG. 2 shows a cross-sectional view of a vertical high-blocking III-V bipolar transistor;

(4) FIG. 3 shows a cross-sectional view of a vertical high-blocking III-V bipolar transistor;

(5) FIG. 4 shows a cross-sectional view of a vertical high-blocking III-V bipolar transistor;

(6) FIG. 5 shows a cross-sectional view of a vertical high-blocking III-V bipolar transistor;

(7) FIG. 6 shows a cross-sectional view of a vertical high-blocking III-V bipolar transistor;

(8) FIG. 7 shows a top view of a vertical high-blocking III-V bipolar transistor;

(9) FIG. 8 shows a top view of a vertical high-blocking III-V bipolar transistor;

(10) FIG. 9 shows a top view of a vertical high-blocking III-V bipolar transistor;

(11) FIG. 10 shows a top view of a vertical high-blocking III-V bipolar transistor;

(12) FIG. 11 shows a top view of an individual vertical high-blocking III-V bipolar transistor; and

(13) FIG. 12 shows a cross-sectional view of an individual vertical high-blocking III-V bipolar transistor shown in FIG. 11, along Line A-A′.

DETAILED DESCRIPTION

(14) The illustration in FIG. 1 shows a first specific embodiment of a vertical high-blocking III-V bipolar transistor 10, including a collector K, an emitter E and a base B and three connecting contact layers K.sub.K, K.sub.E and K.sub.B.

(15) The collector comprises a low n-doped collector semiconductor region 12 and a highly n-doped collector semiconductor region 14, collector semiconductor region 12 being arranged with an underside on an upper side of collector semiconductor contact region 14, and third connecting contact layer K.sub.K covering the underside of collector semiconductor contact region 14. Connector semiconductor region 12 has a thickness D12 of at least 10 μm.

(16) Base B comprises a low p-doped base semiconductor region 16, base semiconductor region 16 being arranged with an underside on an upper side of collector semiconductor region 12. Second connecting contact layer K.sub.B is arranged on a first partial region of an upper side of base semiconductor region 16, according to one refinement, a highly p-doped base semiconductor contact region 18 (shown by the dashed line) extending at least from the first partial region of the upper side of base semiconductor region 16 into base semiconductor region 16 in a well-shaped manner.

(17) A highly n-doped emitter semiconductor contact region 20, which forms emitter E as a mesa structure having a first height H1, is arranged on a second partial region of the upper side of base semiconductor region 16. The first connecting contact layer K.sub.E is formed on an upper side of emitter semiconductor contact region 20.

(18) For this purpose, transistor 10 has an npn structure and is designed in a stacked manner having layered semiconductor regions and semiconductor contact regions, emitter E having a smaller diameter than the base and the collector and being designed as a mesa emitter. It is understood that a pnp structure may also be formed.

(19) A second specific embodiment is shown in the illustration in FIG. 2. Only the differences from the illustration in FIG. 1 are explained below.

(20) The vertical high-blocking III-V semiconductor transistor includes a further semiconductor layer structure 22, further semiconductor layer structure 22 being arranged between the underside of collector semiconductor contact region 14 and third connecting contact layer K.sub.K.

(21) Further semiconductor contact structure 22 comprises a substrate or a semiconductor substrate region and/or a metamorphic buffer or a metamorphic buffer layer sequence.

(22) A third specific embodiment is shown in the illustration in FIG. 3. Only the differences from the illustration in FIG. 1 are explained below.

(23) The base and the emitter are provided with a well-shaped design, so that base semiconductor region 16 extends from an upper side of transistor 10 into collector semiconductor region 12, and emitter semiconductor region 20 extends into base semiconductor region 16.

(24) A fourth specific embodiment is shown in the illustration in FIG. 4. Only the differences from the illustration in FIG. 1 are explained below.

(25) Vertical high-blocking III-V bipolar transistor 10 is designed as a heterojunction bipolar transistor, an emitter intermediate layer 24 of the emitter, which adjoins base semiconductor region 16, being made of a material having a first band gap energy, and the first band gap energy being greater than a second band gap energy of base semiconductor region 16. Emitter intermediate layer 24 is arranged between base semiconductor region 16 and emitter semiconductor contact region 20.

(26) In one refinement, vertical high-blocking III-V bipolar transistor 10 comprises a semiconductor edge region R having a width B and a height H2, semiconductor edge region R being arranged on the surface of base B, extending in a balcony-like manner along an edge of the surface around emitter E, first connecting contact layer K.sub.E and second connecting contact layer K.sub.B. Height H2 of edge region R is less than height H1 of emitter E and corresponds to a layer thickness of emitter intermediate layer 24, the material of semiconductor edge region R corresponding to the material of emitter intermediate layer 24.

(27) A fifth specific embodiment is shown in the illustration in FIG. 5. Only the differences from the illustration in FIG. 4 are explained below.

(28) In addition to the first heterojunction between emitter intermediate layer 24 and base semiconductor region 16, bipolar transistor 10 also includes a second heterojunction between base semiconductor region 16 and a collector intermediate layer 26 of collector K, collector intermediate layer 26 being made of a material having a third band gap energy, and the third band gab energy being greater than the second bad gap energy of base semiconductor region 16. Collector intermediate layer 26 is arranged between base semiconductor region 16 and collector semiconductor region 12 having layer thickness D12.

(29) A sixth specific embodiment is shown in the illustration in FIG. 6. Only the differences from the illustration in FIG. 1 are explained below.

(30) Bipolar transistor 10 is designed as an npn transistor. Collector semiconductor contact region 14 and emitter semiconductor contact region 20 are provided with a highly n-doped design, collector semiconductor region 12 with a low n-doped design and base semiconductor region 16 with a low p-doped design.

(31) A top view of a further specific embodiment of the vertical high-blocking III-V bipolar transistor is shown in the illustration in FIG. 7. First connecting contact layer K.sub.E includes multiple transverse ribs connected by a longitudinal rib. Second connecting contact layer K.sub.B also includes transverse ribs connected by a longitudinal rib, the transverse ribs of second connecting contact layer K.sub.B extending into gaps between the transverse ribs of first connecting contact layer K.sub.E.

(32) A top view of a further specific embodiment of the vertical high-blocking III-V bipolar transistor is shown in the illustration in FIG. 8. Only the differences from the illustration in FIG. 7 are explained below.

(33) First connecting contact layer K.sub.E comprises three ribs running in parallel. Second connecting contact layer E.sub.B comprises two ribs, the two ribs of second connecting contact layer E.sub.B being arranged to the left and right of the ribs of first connecting contact layer K.sub.E.

(34) A top view of a further specific embodiment of the vertical high-blocking III-V bipolar transistor is shown in the illustration in FIG. 9. Only the differences from the illustration in FIG. 7 are explained below.

(35) First connecting contact layer K.sub.E comprises multiple longitudinal ribs connected by a transverse rib. Second connecting contact layer K.sub.B comprises two ribs, the two ribs of second connecting contact layer K.sub.B being arranged to the left and right of the longitudinal ribs of first connecting contact layer K.sub.E.

(36) Semiconductor edge region R extends along the edge of the surface of base B.

(37) A top view of a further specific embodiment of the vertical high-blocking III-V bipolar transistor is shown in the illustration in FIG. 10. Only the differences from the illustration in FIG. 7 are explained below.

(38) Both first connecting contact layer K.sub.E and second connecting contact layer K.sub.B each comprise exactly one contact surface, the contact surfaces in the illustrated top view each being situated on one side of a step KA dividing the upper side of the III-V bipolar transistor and being created, for example, by an etching process.

(39) A top view of a specific embodiment of an individual vertical high-blocking III-V bipolar transistor is shown in the illustration in FIG. 11. Only the differences from the illustration in FIG. 9 are explained below.

(40) In the case of the emitter, first connecting contact layer K.sub.E is integrally connected to emitter semiconductor contact region 20. The emitter comprises only one longitudinal rib and is completely surrounded by base semiconductor region 16. Base semiconductor region 16 is electrically connected with the aid of second connecting contact layer K.sub.B. Base semiconductor region 16 optionally includes a further second connecting contact layer K.sub.B—drawn as the dashed line—to improve the dynamic behavior of the transistor structure. Base semiconductor region 16 is completely surrounded by a substrate layer SUB. A low-resistance layer is optionally formed on substrate layer SUB, the low-resistance layer making it possible, by means of a high transverse conductivity, to optionally connect collector semiconductor region 12 with the aid of third connecting contact layers K.sub.K—drawn as a dashed line. The dynamic properties of the transistor may be further improved hereby.

(41) A cross-sectional view of the specific embodiment of the vertical high-blocking III-V bipolar transistor is illustrated in the illustration in FIG. 12, shown along Line A-A′ in FIG. 11. Only the differences from the illustration in FIG. 11 are explained below.

(42) The transistor structure is designed as a mesa structure and includes a step, due to circumferential substrate layer SUB. The collector optionally includes a collector semiconductor contact region 14 on the underside. If electrical cross-layer layer QLS and no collector semiconductor contact region 14 are formed between the collector and the substrate layer, collector semiconductor contact region 14 rests directly on substrate layer SUB. The collector is connected by the substrate layer. For this purpose, the substrate layer includes a third connecting contact layer K.sub.K on the underside, which is preferably formed over the entire surface.

(43) The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.