Component Carrier With High Passive Intermodulation Performance

Abstract

A component carrier which includes a stack having at least one electrically conductive layer structure and at least one electrically insulating layer structure, and electrically conductive wiring structures being part of the at least one electrically conductive layer structure, wherein a value of the passive intermodulation for signals propagating along the electrically conductive wiring structures is less than 153 dBc.

Claims

1. A component carrier, comprising: a stack including at least one electrically conductive layer structure and at least one electrically insulating layer structure; electrically conductive wiring structures being part of the at least one electrically conductive layer structure; wherein a value of the passive intermodulation for signals propagating along the electrically conductive wiring structures is less than 153 dBc.

2. The component carrier according to claim 1, wherein the value of the passive intermodulation is less than 155 dBc, in particular less than 160 dBc, more particularly less than-165 dBc, and preferably less than 168 dBc.

3. The component carrier according to claim 1, wherein at least a part of a surface of the electrically conductive wiring structures has a roughness Rz of less than 300 nm, in particular less than 200 nm.

4. The component carrier according to claim 3, comprising at least one of the following features: wherein a horizontal surface of the electrically conductive wiring structures has a roughness Rz of less than 300 nm, in particular less than 200 nm; wherein an entire surface of a plated structure of the electrically conductive wiring structures has a roughness Rz of less than 300 nm, in particular less than 200 nm.

5. The component carrier according to claim 1, comprising at least one of the following features: wherein a surface of an electrically conductive base structure of the electrically conductive wiring structures below a plated structure of the electrically conductive wiring structures has a roughness Rz of less than 1.6 m, in particular less than 1 m; wherein a surface finish covering at least part of the electrically conductive wiring structures, wherein in particular the surface finish comprises or consists of tin, in particular chemical tin; wherein at least part of a surface of the electrically conductive wiring structures is covered with an adhesion promoter; wherein at least one electronic component, in particular at least one radio-frequency semiconductor chip configured for emitting and/or receiving radio-frequency signals via the electrically conductive wiring structures, mounted on and/or embedded in the stack and being electrically coupled with the electrically conductive wiring structures; wherein the stack includes a central electrically insulating layer structure covered on both opposing main surfaces thereof with a respective electrically conductive layer structure; wherein the stack includes at least one through hole extending vertically through the at least one electrically insulating layer structure and being at least partially filled with an electrically conductive filling medium for electrically connecting electrically conductive wiring structures on both opposing main surfaces of the at least one electrically insulating layer structure.

6. The component carrier according to claim 1, wherein the electrically conductive wiring structures include a base structure, in particular on the at least one electrically insulating layer structure, and a plated structure on the base structure.

7. The component carrier according to claim 6, comprising at least one of the following features: wherein the base structure is a patterned metal foil, in particular a patterned copper foil; wherein the base structure has a thickness in a range between 5 m and 30 m, in particular in a range between 10 m and 20 m; wherein the plated structure is a plated copper structure; wherein the plated structure comprises at least two stacked plating layers, in particular is configured as a double plating layer; wherein the plated structure has a thickness in a range between 20 m and 70 m, in particular in the range between 30 m and 50 m.

8. The component carrier according to claim 1, comprising at least one of the following features: wherein the electrically conductive wiring structures form an antenna structure; wherein at least one component being surface mounted on and/or embedded in the component carrier, wherein the at least one component is in particular selected from a group consisting of an electronic component, an electrically non-conductive and/or electrically conductive inlay, a heat transfer unit, a light guiding element, an energy harvesting unit, an active electronic component, a passive electronic component, an electronic chip, a storage device, a filter, an integrated circuit, a signal processing component, a power management component, an optoelectronic interface element, a voltage converter, a cryptographic component, a transmitter and/or receiver, an electromechanical transducer, an actuator, a microelectromechanical system, a microprocessor, a capacitor, a resistor, an inductance, an accumulator, a switch, a camera, an antenna, a magnetic element, a further component carrier, and a logic chip; wherein the at least one electrically conductive layer structure comprises at least one of a group consisting of copper, aluminum, nickel, silver, gold, palladium, and tungsten, any of the mentioned materials being optionally coated with supra-conductive material such as graphene; wherein the at least one electrically insulating layer structure comprises at least one of the group consisting of resin, in particular reinforced or non-reinforced resin, for instance epoxy resin or Bismaleimide-Triazine resin, FR-4, FR-5, cyanate ester, polyphenylene derivate, glass, prepreg material, polyimide, polyamide, liquid crystal polymer, epoxy-based build-up material, polytetrafluoroethylene, a ceramic, and a metal oxide; wherein the component carrier is shaped as a plate; wherein the component carrier is configured as one of a group consisting of a printed circuit board, and a substrate; wherein the component carrier is configured as a laminate-type component carrier.

9. A method of manufacturing a component carrier, comprising: forming a stack including at least one electrically conductive layer structure and at least one electrically insulating layer structure; forming electrically conductive wiring structures being part of the at least one electrically conductive layer structure; wherein the electrically conductive wiring structures are formed so that a value of the passive intermodulation for signals propagating along the electrically conductive wiring structures is less than 153 dBc.

10. The method according to claim 9, wherein forming the electrically conductive wiring structures includes forming the electrically conductive wiring structures with a base structure, in particular arranged on the at least one electrically insulating layer structure, and with a plated structure arranged on the base structure.

11. The method according to claim 10, comprising at least one of the following features: wherein the method includes attaching, in particular laminating, a metal foil as the base structure or as a preform of the base structure to the at least one electrically insulating layer structure; wherein the method includes plating, in particular galvanic plating, electrically conductive material as the plated structure or as a preform of the plated structure on the base structure or on a preform of the base structure.

12. The method according to claim 10, wherein the method includes forming the plated structure with a first plating layer on the base structure and with a second plating layer on the first plating layer, wherein the first plating layer and the second plating layer are formed in separate plating procedures.

13. The method according to claim 12, comprising at least one of the following features: wherein the method includes plating the first plating layer on the base structure before applying an etch resist, and plating the second plating layer on only a part of the first plating layer after applying the etch resist, wherein in particular the method includes commonly removing a part of the first plating layer and a part of the base structure by etching after applying the etch resist, wherein more particularly the method includes applying an etch protection to the second plating layer before the etching; wherein the method includes forming the first plating layer by flash plating.

14. A method, comprising: providing a component carrier with a stack including at least one electrically conductive layer structure and at least one electrically insulating layer structure, electrically conductive wiring structures being part of the at least one electrically conductive layer structure, wherein a value of the passive intermodulation for signals propagating along the electrically conductive wiring structures of the component carrier is less than 153 dBc; propagating a signal in the component carrier for a high-frequency application.

15. The method according to claim 14, comprising at least one of the following features: wherein the component carrier is used for wireless communication, in particular according to 5G; wherein the component carrier is used for high-frequency applications above 1 GHz, in particular above 100 GHz.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0052] FIG. 1, FIG. 2, FIG. 3, FIG. 4, FIG. 5 and FIG. 6 illustrate cross-sectional views of structures obtained during performance of a method of manufacturing a component carrier according to an exemplary embodiment of the invention, shown in a cross-sectional view in FIG. 7.

[0053] FIG. 8 illustrates an electrically conductive wiring structure of a component carrier according to an exemplary embodiment of the invention obtained by PIM structuring.

[0054] FIG. 9 illustrates a detail of the electrically conductive wiring structure of FIG. 8 obtained by PIM structuring and shows that the roughness Rz of a surface of the wiring structure can assume a very small value of less than 200 nm.

[0055] FIG. 10 illustrates a diagram showing values of the roughness Ra of electrically conductive wiring structures of component carriers according to exemplary embodiments of the invention in comparison to conventional component carriers.

[0056] FIG. 11 illustrates a component carrier configured for carrying out a radio frequency application according to an exemplary embodiment of the invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0057] The illustrations in the drawings are schematically presented. In different drawings, similar or identical elements are provided with the same reference signs.

[0058] Before referring to the drawings, exemplary embodiments will be de-scribed in further detail, some basic considerations will be summarized based on which exemplary embodiments of the invention have been developed.

[0059] According to an exemplary embodiment of the invention, a component carrier (in particular a printed circuit board, PCB) for an antenna application with a PIM value of below 153 dBc, preferably below 160 dBc, is provided. Such a unique PIM performance may be obtained, for instance, by ensuring a low roughness of a base structure (such as a copper foil) and a very low roughness of a plated structure formed by pattern plating on such a base structure. By properly controlling the roughness of electrically conductive wiring structures on their (in particular rising and/or falling) edges and/or on their top and/or bottom surface, preferably in combination with a chemical tin type surface finish on a top and/or bottom surface of the electrically conductive wiring structures has turned out as an efficient way of reducing the PIM losses in the described way. This may in particular allow preventing interruptions of communication due to interruptions of data transmission caused by a component carrier. Furthermore, fluctuations of transmission quality during wireless communication involving the component carrier may be reduced.

[0060] For instance, such an architecture allows manufacturing component carriers with an antenna being suitable for demanding high-frequency applications, as required for instance by 4G or 5G. More specifically, the component carrier may be used for mobile applications, automotive applications (in particular car-to-car applications), cloud applications, fog applications, Internet-of-Things (IOT) applications, etc.

[0061] FIG. 1 to FIG. 7 illustrate cross-sectional views of structures obtained during carrying out a method of manufacturing a component carrier 100 according to an exemplary embodiment of the invention, shown in FIG. 7.

[0062] Referring to FIG. 1, a stack 102 is provided which comprises two electrically conductive layer structures 104 on both opposing main surfaces of a central electrically insulating layer structure 106. The electrically insulating layer structure 106 may for instance comprise resin (such as epoxy resin), optionally comprising reinforcing particles such as glass fibers. For instance, the electrically insulating layer structure 106 may be made of prepreg. The two electrically conductive layer structures 104 may be copper layers laminated onto the opposing main surfaces of the electrically insulating layer structure 106. For instance, the stack 102 may be a fully cured core with laminated copper foils.

[0063] The electrically conductive layer structures 104 serve as preform of base structures 112 which, in turn, later form part of electrically conductive wiring structures 108 with highly appropriate passive intermodulation (PIM) behavior. The preform of the base structure 112 on each of the top main surface and the bottom main surface of the electrically insulating layer structure 106 may have a very small thickness in a range between 5 m and 30 m. Preferably, the surface of the preforms of the electrically conductive base structures 112 facing the electrically insulating layer structure 106 (i.e. the lower main surface of the upper preform of the electrically conductive base structure 112 and the upper main surface of the lower preform of the electrically conductive base structure 112) is selected to have a low roughness Rz of less than 1 m. The roughness between electrically insulating layer structure 106 and electrically conductive base structure 112 may also be denoted as treatment roughness. This will have a positive impact on the PIM properties of the readily manufactured component carrier 100.

[0064] FIG. 1 furthermore shows that one or more through holes 118 may be formed in the stack 102 to extend vertically through the entire stack 102. The through hole 118 may be formed by mechanically drilling, laser drilling, etc. and may later serve for electrically connecting electrically conductive wiring structures 108 on the opposing main surfaces of the stack 102 with a short path length. Such a short connection path for propagating electric signals may suppress signal distortion.

[0065] Referring to FIG. 2, a flash plating procedure may be carried out for depositing further copper material on the exposed surfaces of the preforms of the base structures 112. As a result, a further constituent of the electrically conductive wiring structures 108 may be formed in form of preforms of plated structures 110 deposited on the preforms of the base structures 112. More precisely, the flash plating procedure according to FIG. 2 only forms part of entire plated structures 110, namely forms a pre-form of first plating layers 122 of the plated structures 110 on the previously formed preforms of the base structures 112. Second plating layers 124 of the plated structures 110 will be formed later, as described below referring to FIG. 6.

[0066] Moreover, the described flash plating procedure also deposits electrically conductive material (more specifically copper) on the vertical walls of the stack 102 delimiting the through hole 118. Thereby, the through hole 118 is filled partially (or alternatively entirely) with electrically conductive filling medium 120 for electrically connecting the opposing main surfaces of the stack 102.

[0067] In order to promote adhesion, it is also possible to apply a chemical adhesion promoter (not shown) on the preforms of the base structures 112 prior to the plating of the preforms of the first plating layers 122.

[0068] Referring to FIG. 3, an etch resist 126 (such as a photoresist) is applied (in particular by lamination) to both opposing main surfaces of the extended stack 102 shown in FIG. 2. Thus, the preforms of the first plating layers 122 on the preforms of the base structures 112 are covered by the etch resist 126.

[0069] Referring to FIG. 4, specific portions of the etch resist 126 on both opposing main surfaces of the structure shown in FIG. 3 are exposed to electromagnetic radiation 130 generated by an electromagnetic radiation source 132. The electromagnetic radiation source 132 may for instance be a laser source configured for generating laser light, such as ultraviolet laser light or visible laser light. A mask 134 (such as a film mask) having alternating transparent and opaque portions can be arranged between the electromagnetic radiation source 132 and the structure shown in FIG. 3 for exposure.

[0070] Referring to FIG. 5, the result of a developing procedure is illustrated. As a result of the illumination of only selected portions of the etch resist 126 with electromagnetic radiation 130, only illuminated portions of the etch resist 126 remain on the stack 102, whereas non-illuminated portions of the etch resist 126 can be removed by stripping, etching or the like. As a result, a patterned etch resist 126 remains on both opposing main surfaces of the stack 102.

[0071] Alternatively, it is also possible that the material of the etch resist 126 is selected so that, as a result of the illumination of only selected portions of the etch resist 126 with electromagnetic radiation 130, only non-illuminated portions of the etch resist 126 remain on the stack 102, whereas illuminated portions of the etch resist 126 can be removed by stripping, etching or the like.

[0072] Referring to FIG. 6, the structure shown in FIG. 5 is firstly made subject to a further plating procedure and is subsequently made subject to a surface finish deposition procedure.

[0073] Thus, the method comprises continuing formation of the plated structure 110 by plating second plating layers 124 selectively on exposed surface portions of the preforms of the first plating layer 122, i.e., surface portions of the first plating layers 122 being not covered by the remaining portions of the patterned etch resist 126. For instance, formation of the second plating layers 124 may be carried out by galvanic plating. Thus, the second plating layers 124 are formed only on specific surface portions of the preforms of the first plating layers 122 between remaining portions of the etch resist 126. Hence, the shown preform of the plated structure 110 comprises two stacked plating layers 122, 124 and is thus embodied as a double plating layer. Exposed portions of the dielectric etch resist 126 will not be covered by copper material of the second plating layers 124. As can be taken from FIG. 6 and FIG. 2, the preforms of the first plating layers 122 on the one hand and the second plating layers 124 on the other hand are formed in separate plating procedures. The preform of the plated structure 110 may have an overall very small thickness in a range between 20 m and 70 m.

[0074] After having formed the patterned second plating layers 124, an etch protection 113 is deposited selectively on exposed surface portions of the second plating layers 124. Material of the etch protection 113 will not be deposited on exposed surface portions of the dielectric etch resist 126.

[0075] In order to promote adhesion, it is also possible to apply a chemical adhesion promoter (not shown) on the exposed surfaces of the preforms of the first plating layers 122 prior to the plating of the second plating layers 124. In order to additionally promote adhesion, it is also possible to apply a chemical adhesion promoter (not shown) on the exposed surfaces of the second plating layers 124 prior to the deposition of the etch protection 113.

[0076] Referring to FIG. 7, etching and stripping may be carried out. More specifically, the method comprises commonly etching away the etch resist 126, the portions of the preforms of the first plating layers 122 below the etch resist 126 and portions of the preforms of the base structures 112 below said portions of the preforms of the first plating layers 122. No etching of the etch protection 113 and the corresponding portions of the layer structures 112, 122 and 124 beneath the etch protection 113 occurs. As a result, patterning of the layer structures on the two opposing main surfaces of electrically insulating layer structure 106 is carried out according to FIG. 7. As a result, electrically conductive traces composed of portions of base structure 112, plated structure 110 (composed of first plating layer 122 and second plating layer 124) and of etch protection 113 are formed. The described patterning procedure may be adjusted in such a way that an antenna structure is formed by the electrically conductive wiring structures 108.

[0077] The etch protection 113 may then be removed. A surface finish 114 may then be formed on top of the electrically conductive wiring structures 108. Preferably, the surface finish 114 is made of chemical tin. Surprisingly, chemical tin has turned out to be capable of properly adhering on a very smooth copper surface, and thus also on the exposed main surfaces of the second plating layers 124 which may preferably have a very small roughness Rz of less than 200 nm. However, galvanic tin or hot air leveling may also be used as material of the surface finish 114.

[0078] The described plating procedures may be carried out in such a way that at least part of the surface of the electrically conductive wiring structures 108 has a roughness Rz of preferably less than 200 nm. In particular, the surface portions of the electrically conductive wiring structures 108 relating to the (for instance slanted) sidewalls and/or the surface portions of the electrically conductive wiring structure 108 opposing the electrically insulating layer structure 106 may have a roughness Rz of preferably less than 200 nm. The surface portions of the electrically conductive wiring structures 108 facing the electrically insulating layer structure 106 may have a low roughness Rz of less than 1 m. It has turned out that this smoothness of the electrically conductive wiring structures 108 has a highly positive impact on the PIM behavior of the obtained component carrier 100. In particular in view of the low surface roughness of the electrically conductive wiring structures 108 and the specific selection of the surface finish 114, electrically conductive wiring structures 108 are obtained ensuring that the value of the passive intermodulation PIM for electric high-frequency signals propagating along the electrically conductive wiring structures 108 may be less than 160 dBc. Thus, a component carrier 100 according to an exemplary embodiment of the invention with excellent PIM performance and thus a proper capability of transporting radiofrequency signals with low signal loss can be obtained.

[0079] The obtained component carrier 100 is embodied as a plate-shaped laminate-type printed circuit board (PCB) with excellent PIM behavior. The component carrier 100 is composed of the stack 102 of electrically conductive layer structures 104 on both opposing main surfaces of the central electrically insulating layer structure 106. Electrically conductive wiring structures 108 forming part of the electrically conductive layer structures 104 form an antenna structure and are configured for high frequency signal transport on both opposing main surfaces of the electrically insulating layer structure 106. The chemical tin type surface finish 114 covers exposed upper and lower surfaces of the electrically conductive wiring structures 108. Via the plated through hole(s) 118, high-frequency signals may propagate along a very short and thus low loss path between the two opposing main surfaces of the electrically insulating layer structure 106.

[0080] FIG. 8 illustrates an electrically conductive wiring structure 108 of a component carrier 100 according to an exemplary embodiment of the invention formed by PIM structuring. FIG. 9 illustrates a detail of the electrically conductive wiring structure 108 of FIG. 8 obtained by PIM structuring and shows that the roughness Rz of a surface of the wiring structure 108 can assume a very small value of less than 200 nm.

[0081] FIG. 10 illustrates a diagram 150 showing values of the roughness Ra of electrically conductive wiring structures 108 of component carriers 100 according to exemplary embodiments of the invention in comparison to conventional component carriers.

[0082] Reference numeral 151 relates to an exemplary embodiment of the invention using tin as surface finish 114. Reference numeral 152 relates to another exemplary embodiment of the invention using NaPs as surface finish 114. Reference numeral 153 relates to still another exemplary embodiment of the invention using SiT as surface finish 114. Reference numeral 154 relates to yet another exemplary embodiment of the invention using electroless nickel immersion gold (ENIG) as surface finish 114. Reference numeral 155 relates to still another exemplary embodiment of the invention using copper.

[0083] Reference numeral 156 relates to a conventional approach without the above described plating and patterning procedure and using ENIG as surface finish. Reference numeral 157 relates to another conventional approach without the above described patterning procedure and using standard copper.

[0084] As can be taken from diagram 150, only the five exemplary embodiments of the invention allow obtaining a roughness Ra around an advantageous value of 200 nm. In contrast to this, the conventional approaches fail to obtain a sufficiently low roughness and do not show a sufficient PIM behavior.

[0085] FIG. 11 illustrates a component carrier 100 configured for carrying out a radio-frequency application according to an exemplary embodiment of the invention.

[0086] In the component carrier 100 shown in a cross-sectional view in FIG. 11, an electronic component 116 is embedded in the stack 102 and is connected to copper wiring structures 108 between prepreg layer structures 106 via a pad 186 and a copper filled via as vertical through connection or electrically conductive filling medium 120. The wiring structures 108 are embedded in dielectric material of the electrically insulating layer structures 106. The wiring structures 108 have been formed by a method corresponding to the one described referring to FIG. 1 to FIG. 7. A detail 188 shows a portion of the wiring structures 108 from above, wherein the wiring structures 108 may be configured for example with a geometry similar to FIG. 7 and with smooth (i.e., low roughness) walls. In the shown embodiment, the electronic component 116 may be a semiconductor chip configured for executing a radio-frequency application by transmitting electric signals via the wiring structures 108 having frequencies of for example 10 GHz or more.

[0087] Due to the skin effect, electronic signals with very high frequencies will propagate substantially only within a thin skin surface 197 of the electrically conductive wiring structures 108. Thickness of the skin surface 197 depends, inter alia, on the frequency but may be in the order of magnitude of 2 m. A roughened surface, which is conventionally used for promoting adhesion of a wiring structure to surrounding dielectric material involves microstructures in the same order of magnitude of few micrometers and can therefore disturb the propagation of radiofrequency signals. In contrast to this, the wiring structures 108 of the component carrier 100 according to an exemplary embodiment of the invention accomplishes improvement of surface adhesion by the above-described adhesion promoter and can therefore render a roughening procedure dispensable. Surfaces of the wiring structures 108 may therefore be provided with very small roughness. This reduces losses of the electric radiofrequency signal.

[0088] It should be noted that the term comprising does not exclude other elements or steps and the article a or an does not exclude a plurality. Also, elements described in association with different embodiments may be combined.

[0089] Implementation of the invention is not limited to the preferred embodiments shown in the figures and described above. Instead, a multiplicity of variants is possible which use the solutions shown and the principle according to the invention even in the case of fundamentally different embodiments.