ELECTROLYTE-BASED FIELD EFFECT TRANSISTOR AND ASSOCIATED METHOD OF FABRICATION

Abstract

An electrolyte-based field effect transistor includes a dielectric layer; a source electrode and a drain electrode located on top of the dielectric layer; the electrolyte-based transistor further including an electrolyte layer between and on top of the source electrode and the drain electrode, the part of the electrolyte layer located between the source electrode and the drain electrode being in direct contact with the dielectric layer; and a gate electrode on top of the electrolyte layer, the orthogonal projection of the gate electrode in a plane including the source and drain electrodes being located, at least in part, between the source and the drain electrodes.

Claims

1. An electrolyte-based field effect transistor comprising: a dielectric layer; a source electrode and a drain electrode located on top of the dielectric layer; a lithium-based solid-state electrolyte layer between and on top of the source electrode and the drain electrode, a part of the lithium-based solid-state electrolyte layer located between the source electrode and the drain electrode being in direct contact with the dielectric layer, and a gate electrode on top of the lithium-based solid-state electrolyte layer and in direct contact with the electrolyte layer, an orthogonal projection of said gate electrode in a plane comprising the source and drain electrodes being located, at least in part, between the source and the drain electrodes.

2. The electrolyte-based field effect transistor according to claim 1, wherein the lithium-based solid state electrolyte is an oxide solid electrolyte, a sulfide solid electrolyte or a solid polymer electrolyte.

3. The electrolyte-based field effect transistor according to claim 1, wherein no semi-conductor layer is present between the source electrode and the drain electrode.

4. The electrolyte-based field effect transistor according to claim 1, wherein the dielectric material of the dielectric layer has an energy band gap higher than 8 eV.

5. The electrolyte-based field effect transistor according to claim 1, wherein the distance between the source electrode and the drain electrode is between 1.5 μm and 5 μm.

6. The electrolyte-based field effect transistor according to claim 1, wherein the width of the source electrode and the drain electrode is between 8 μm and 15 μm.

7. The electrolyte-based field effect transistor according to claim 6, wherein the width is 10 μm.

8. The electrolyte-based field effect transistor according to claim 1, wherein a thickness of the source electrode, the drain electrode and/or the gate electrode is between 200 nm and 400 nm.

9. The electrolyte-based field effect transistor according to claim 8, wherein the thickness is 300 nm.

10. The electrolyte-based field effect transistor according to claim 1, wherein a thickness of the dielectric layer is between 400 nm and 600 nm.

11. The electrolyte-based field effect transistor according to claim 10, wherein the thickness is 500 nm.

12. The electrolyte-based field effect transistor according to claim 1, wherein a thickness of a thicker part of the lithium-based solid-state electrolyte layer is between 10 nm and 300 nm.

13. The electrolyte-based field effect transistor according to claim 12, wherein the thickness is 200 nm.

14. A spiking neural network comprising a plurality of electrolyte-based field effect transistors according to claim 1.

15. A method for fabricating an electrolyte-based field effect transistor, said method starting from a substrate and comprising: full-sheet depositing a dielectric layer on the substrate; full-sheet depositing a first conductive layer on the dielectric layer; patterning the first conductive layer to form a source electrode and a drain electrode in said conductive layer; full-sheet depositing an electrolyte layer, a thickness of said electrolyte layer being chosen so as to cover the source and drain electrodes formed during the patterning; depositing a second conductive layer on the electrolyte layer, and patterning the second conductive layer to form a gate electrode, an orthogonal projection of said gate electrode in a plane comprising the source and drain electrodes being located, at least in part, between the source and the drain electrodes.

16. The method according to claim 15, wherein a material of the dielectric layer is the silicon oxide and the full-sheet depositing of a dielectric layer on the substrate is implemented using a thermal growth.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0035] Other characteristics and benefitss of the invention will become clear from the description that is given thereof below, by way of indication and in no way limiting, with reference to the appended figures.

[0036] FIG. 1 illustrates an electric double layer transistor of the prior art.

[0037] FIG. 2 illustrates a red-ox transistor of the prior art.

[0038] FIGS. 3 to 5 illustrate an electrolyte-based transistor according to an aspect of the invention.

[0039] FIGS. 6A to 6E illustrate a method of fabrication according to an aspect of the invention.

[0040] FIG. 7 illustrates a logogram of the method of fabrication according to an aspect of the invention.

[0041] FIG. 8 shows the evolution of the source drain current as a function of the source drain voltage for different value of the gate voltage.

[0042] FIG. 9 shows the evolution of the conductance between the source electrode and the drain electrode as a function of the gate voltage for different distance between the source electrode and the drain electrode.

[0043] FIG. 10 shows the evolution of the conductance in time after voltage pulses of different amplitude (1V, 2V, 3V and 4V) and a duration of 0.5 second applied to the gate electrode.

[0044] FIG. 11 shows, in red the hysteresis of the source-drain current as a function of the gate voltage and, in blue the hysteresis of the gate current as a function of the gate voltage.

[0045] FIG. 12A shows the evolution of the paired-pulse facilitation as a function of the width of the pulse.

[0046] FIG. 12B shows one measurement that allows to extract the PPF for a given pulse width.

DETAILED DESCRIPTION

[0047] For greater clarity, identical or similar elements are marked by identical reference signs in all the figures.

Electrolyte-Based Field Effect Transistor

[0048] A first aspect of the invention illustrated in FIGS. 3 to 5 concerns an electrolyte-based field effect transistor comprising a dielectric layer OX, a source electrode S and a drain electrode D located on top of the dielectric layer OX. In an embodiment, the dielectric material of the dielectric layer has an energy band gap higher than 8 eV. In an embodiment, the distance between the source electrode S and the drain electrode D is between 1.5 μm and 5 μm. In an embodiment, the width of the source electrode S and the drain electrode D (i.e, measured along a direction perpendicular to an axis going through the center of the source electrode S and the drain electrode D) is between 8 μm and 15 μm, and in an embodiment 10 μm. In an embodiment, the thickness of the dielectric layer OX is between 400 nm and 600 nm, and in an embodiment 500 nm. In an embodiment, the material of the dielectric layer OX comprises SiO.sub.2 or any insulating metal oxide such as Al.sub.2O.sub.3.

[0049] The electrolyte-based transistor according to an aspect of the invention further comprises an lithium-based solid-state electrolyte layer EC between and on top of the source electrode S and the drain electrode D, the part of the electrolyte layer located between the source electrode S and the drain electrode D being in direct contact with the dielectric layer OX. In particular, there is no semi-conductor layer between the source S and the drain D electrodes in the electrolyte-based field effect transistor according to an aspect of the invention. In an embodiment, the electrolyte material of the electrolyte layer EC comprises lithium phosphorous oxynitride. In an embodiment, the thickness of the electrolyte layer EC is comprised between 10 nm and 300 nm, and in an embodiment 200 nm. In an embodiment, when the thickness if not uniform, the thickness of the electrolyte layer EC relates to the thickness of the electrolyte layer EC between the source electrode S and the drain electrode D. In another embodiment, the lithium-based solid state electrolyte is an oxide solid electrolyte (e.g. LiPON, LI.sub.3PO.sub.4 or Li.sub.3PO.sub.xSe.sub.x), a sulfide solid electrolyte (e.g. Li.sub.6PS.sub.5X where X is chosen among CI, Br or I) or a solid polymer electrolyte (e.g. PVA (LiCIO.sub.4) or PEO (LiCIO.sub.4)).

[0050] The electrolyte-based transistor according to an aspect of the invention also comprises a gate electrode G on top of the electrolyte layer EC and in direct contact with the electrolyte layer EC, the orthogonal projection of the gate electrode G in a plane comprising the source electrode S and drain electrode D being located, at least in part, between the source electrode S and the drain electrode D. In an embodiment, the thickness of the source electrode S, the drain electrode D and/or the gate electrode G is between 200 nm and 400 nm, and in an embodiment 300 nm.

[0051] As shown in FIG. 4, when a voltage is applied to the gate voltage, charges are formed at the gate/electrolyte interface and at the electrolyte/dielectric interface. Those charges are believed to play a role in the transport properties of the transistor according to the invention. As shown in FIG. 5, when the gate voltage is brought back to zero, the charges vanish. The measures performed on such a transistor (see FIGS. 10 to 13 described later) have shown that it displays a low working voltage, a high on/off ratio, wide conductance range and a high endurance. Furthermore, it operates in a three terminals configuration structure and with low working voltage and can be used in a spiking neural network to obtain a spiking neural network according to a second aspect of the invention.

Fabrication of a Electrolyte-Based Field Effect Transistor

[0052] A third aspect of the invention illustrated in FIGS. 6A-E and FIG. 7 concerns a method 100 for fabricating a electrolyte-based field effect transistor, the method starting from a substrate SB.

[0053] The method according to an aspect of the invention comprises a step E1 of full-sheet deposition of a dielectric layer OX on the substrate. In an embodiment, the thickness of the dielectric layer OX is between 400 nm and 600 nm, and in an embodiment 500 nm.

[0054] This step E1 is followed by a step E2 of full-sheet deposition of a first conductive layer CL on the dielectric layer OX. In an embodiment, the thickness of the conducive layer CL is between 200 nm and 400 nm, and in an embodiment 300 nm.

[0055] The structure obtained after these two steps E1-E2 is illustrated in FIG. 6A.

[0056] As illustrated in FIG. 6B, the method 100 further comprises a step E3 of patterning the first conductive layer CL to form a source electrode S and a drain electrode D in the conductive layer CL.

[0057] As illustrated in FIG. 6C, the method 100 also comprises a step E4 of full-sheet deposition of an electrolyte layer EC, the thickness of the electrolyte layer EC being chosen so as to cover the source S and drain D electrodes formed during the preceding step E3. In an embodiment, the thickness of the electrolyte layer EC is between 10 nm and 300 nm, and in an embodiment 200 nm.

[0058] As illustrated in FIG. 6D, the method 100 further comprises a step E5 of deposition of a second conductive layer CL2 on the electrolyte EC. In an embodiment, the thickness of the second conducive layer CL2 is between 200 nm and 400 nm, and in an embodiment 300 nm.

[0059] As illustrated in FIG. 6E, this step E5 is followed by a step E6 of patterning the second conductive layer CL2 to form a gate electrode G, the orthogonal projection of the gate electrode G in a plane comprising the source electrode S and drain electrode D being located, at least in part, between the source electrode S and the drain electrode D.

Characterization of the Electrolyte-Based Field Effect Transistor

[0060] While the underlying mechanism of the current flowing though the transistor according to an aspect of the invention is not fully understood, the inventors were able to verify that it can be used as a transistor, for instance acting as a neuron in a neural network.

[0061] The FIG. 8 shows the evolution of the source drain current as a function of the source drain voltage for different value of the gate voltage (from 1 V to 5 V). The modulation of the current when applying voltages on the different electrodes of the transistors.

[0062] The FIG. 9 shows the evolution of the conductance between the source electrode and the drain electrode as a function of the gate voltage for different distances between the source electrode and the drain electrode. The dependence of the current with respect to the distance between the source electrode and the drain electrode is clearly visible.

[0063] The FIG. 10 shows the evolution of the conductance in time after voltage pulses of different amplitude (1 V, 2 V, 3 V and 4 V) and a duration of 0.5 second applied to the gate. The measurement clearly shows a high on/off ratio (up to 525) and a fast relaxation of the conductance after the pulse.

[0064] The FIG. 11 shows, in red the hysteresis of the source-drain current as a function of the gate voltage and, in blue the hysteresis of the gate current as a function of the gate voltage. The measurement clearly shows the decorrelation between the source-drain current and the gate current.

[0065] The FIG. 12A shows the evolution of the paired-pulse facilitation aka PPF (which corresponds to a synapse property) as a function of the width of the pulse (see FIG. 12B). The FIG. 12B shows one measurement that allows to extract the PPF for a given pulse width. This measurement is known of the skilled person and will not be detailed further.

[0066] It is clear from the measurements of FIGS. 8 to 12 that a transistor according to the invention display features that are characteristics of a field effect transistor and that are compatible with the use in emulating the synaptic plasticity.