Abstract
A plurality of small copper-filled TSV (through silicon via) interposer slivers dispersed in a fan-out wafer level package (FOWLP) for wire bonding interconnections forms a hybrid FOWLP/interposer multichip package that avoids the use of expensive large 2.5D TSV interposer modules for heterogeneous integration and for chiplets. Package fabrication on reconstituted wafers or panels can follow either the chip-first or RDL-first process.
Claims
1. An integrated circuit package, comprising: integrated circuit chips having face-up input/output wire bonding pads; small copper-filled TSV (through silicon via) interposer slivers having an OSP (organic solderability preservatives) coating covering all exposed TSV copper surfaces; a first plurality of chip-to-chip wire bonding interconnections; a second plurality of chip-to-interposer sliver wire bonding interconnections; an encapsulation encasing all chips, wires, interposer slivers; and a redistribution layer (RDL) having internal conductive traces coupling the small interposer sliver TSV bottom contacts to solder balls attached to the RDL outer bonding pads.
2. The package of claim 1, wherein at least one integrated circuit chip is connected to the small TSV interposer slivers by wire bonding.
3. The package of claim 1, wherein two or more integrated circuit chips are connected to a shared small TSV interposer sliver by wire bonding.
4. The package of claim 1, wherein at least one of the integrated circuit chips is a chiplet.
5. The package of claim 1, wherein the wire bonding wires are connected to the small interposer sliver TSV copper openings without surface bonding pads.
6. The package of claim 1, wherein both sides of the copper-filled TSV openings in the small interposer slivers are covered by VIP (via-in-pad) metal pads for wire bonding.
7. The package of claim 6, wherein at least one wire bonding pads on the small interposer sliver connect two or more copper-filled TSV for multiple wire bonding.
8. The package of claim 1, wherein the integrated circuit chips and the small interposer slivers are placed side-by-side on the RDL.
9. The package of claim 1, wherein at least one integrated circuit chip is stacked on another chip.
10. The package of claim 1, wherein at least one integrated circuit chip is connected to the RDL face-down by flip chip bumps.
11. The package of claim 10, wherein at least one small interposer sliver is connected to the RDL by TSV bottom micro-bumps.
12. The package of claim 10, wherein at least one integrated circuit chip is stacked on top of another chip.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The drawings are diagrammatic representations of exemplary aspects of the present invention and are neither limiting nor necessarily drawn to scale.
[0018] FIG. 1 illustrates a prior art 2.5D multichip package using a large TSV interposer module with an integrated RDL on top of the interposer and a package substrate connected to the interposer bottom.
[0019] FIG. 2 is the cross-sectional view of a FOWLP multichip package having two chips; one side of the chip I/O are connected by chip-to-chip wire bonding, and the other side of chip I/O are wire bonded to interpolets.
[0020] FIG. 3 is a perspective view of the two-die FOWLP multichip package with a first plurality of chip-to-chip wire bonding and a second plurality of chip-to interpolet fan-out wire bonding.
[0021] FIG. 4 shows the cross-sectional view of a FOWLP/interpolet package having two shared interpolets in between three chips and two outside interpolets for chip outer edge fan-out wire bonding.
[0022] FIG. 5 is the top view of the FOWLP package layout having three chips wire bonded to two shared interpolets in-between and two outside interpolets for fan-out wire bond connections.
[0023] FIG. 6 is the cross-sectional view of a large center chip wire-bonded to its side interpolets and two stacked small chips also wire-bonded to the same interpolets.
[0024] FIG. 7 is the plane view of a multichip package layout having five chips and four corner interpolets placed side-by-side and interconnected by different fan-out wire bonding.
[0025] FIG. 8 is the cross-sectional view of a 3D stacked multiple chip FOWLP package with the lower flip chip face-down and connected to the RDL by micro-bumps, while two stacked chips on top are connected to their respective interpolets using wire bonding for fan-out connection to the RDL below.
[0026] FIG. 9 is the cross-sectional view of a simple interpolet structure with an array of copper-filled TSV have relatively large diameters for direct wire bonding without wire bonding pads.
[0027] FIG. 10 is the cross-sectional view of a simple interpolet having an array of thin copper TSV and wire bonding pads on both ends.
[0028] FIG. 11 shows the perspective view of an interpolet sliver and an expanded top view of the via-in-pad (VIP) wire bond pads; one large bonding pad is connected to two adjacent TSV for multiple wire bonding.
DETAILED DESCRIPTION OF THE INVENTION
[0029] By way of illustration, the following detailed description refers to the accompanying drawings showing the details of various aspects of this invention disclosure.
[0030] The term chip refers to an integrated circuit (IC) die that can be a SOC (system on chip), MCU (micro controller unit), FPGA (field-programmable gate array) or memories such as DRAM, SRAM, and NAND; it also includes various types of chiplet in the illustrative drawings here. The term interpolet is used to represent a small copper-filled TSV interposer sliver, similar to a chiplet that is to a small sized chip.
[0031] A conventional 2.5D interposer package is illustrated by FIG. 1 to show the prior art of heterogeneous integration of multiple chips on a large piece of silicon TSV interposer module. In FIG. 1, a 2.5D package 100 without encapsulation is shown having two IC chips 101 and 102, respectively, attached to the RDL (redistribution layer) 107 of interposer 105 by micro-bumps 103 on chip 101 and micro-bumps 104 on chip 102. Interposer module 105 has a plurality of vertical copper-filled TSV arrays 106 linking the top RDL 107 to the bottom bumps 108. The interposer module 105 and its chip 101 and chip 102 subassembly are mounted onto a package substrate 109 having bottom lead-free C4 (controlled collapse chip connection) solder balls 110 for SMT (surface mount technology) assembly to a PCB motherboard (not shown). Package 100 requires the use of an expensive component, the TSV interposer module 105, and three levels of interconnection: micro-bumps 103 and 104 on chip 101 and 102, respectively; bumps 108 at the bottom of interposer 105; and solder balls 110 on the package substrate 109. With the intermediate interposer 105 and three levels of bump interconnections, the package 100 body height is generally thicker than typical FOWLP packages that do not have an interposer and a substrate.
[0032] Because the large-sized interposer module 105 requires intricate patterns of TSV array 106 and RDL 107, the fabrication cost of interposer module 105 remains prohibitively expensive due to low wafer edge utilization and poor yield from a silicon wafer. Some alternatives, including use of non-silicon materials such as glass or organic substrates, are being developed. Such materials may be used in a panel format to reduce the edge waste; however, materials different from silicon may pose other issues such as mismatch of CTE (coefficient of thermal expansion). Ideally, therefore, the best interposer material for silicon IC chips is still silicon, and prior art 2.5D packages such as device 100 using a large-sized silicon interposer 105 are generally reserved for high-end applications such as for high performance computing (HPC), networking, and datacenter applications.
[0033] FIG. 2 illustrates a simple design concept scheme of using two small-sized interpolets in a FOWLP package to replace the use of a large-sized interposer module and a supporting substrate in a conventional 2.5D package. The cross-sectional view of device 200 shows that two adjacent chips 21 and 22 are connected to each other by wire bond bundle 25 for chip-to-chip interconnection, while chip 21 is also linked to interpolet 23 on the outside by fan-out wires 24 and chip 22 to interpolet 27 on the other end by fan-out wires 26. All of the signal outputs from chip 21 are routed through interpolet 23 TSV arrays to the bottom RDL 30, and all of the signal outputs from chip 22 are routed through the interpolet 27 TSV arrays to RDL 30, and finally from RDL 30 to the outer solder balls 31. Encapsulant 20 is applied on the reconstituted wafer after the wire bonding step is completed.
[0034] To further illustrate the layout configuration, FIG. 3 shows a perspective view of package 200 with no solder balls underneath RDL 30. RDL 30 is fabricated on a reconstituted wafer after encapsulant 20 is molded; its internal conductive traces are connected to the bottom TSV contacts in interpolet 23 and interpolet 27 for rerouting to the bottom solder balls. Wire bond bundle 25 is chip-to-chip connection between chip 21 and chip 22; while the chip 21 signal outputs connect to interpolet 23 through fan-out wire bond bundle 24 and chip 22 outputs to interpolet 27 through fan-out wire bond bundle 26. With multiple fan-out rows of TSV contacts in interpolet 23 and interpolet 27, the alignment of internal conductive traces in RDL 30 is made much easier due to wider interconnection pitches.
[0035] Although FIG. 3 shows that just two interpolets 23 and 27 are used for rerouting all signals from chip 21 and chip 22 to RDL 30, additional interpolets can be added if needed to accept more fan-out wire bonding from chip 21 and chip 22.
[0036] The use of interpolets shared among multiple chips is illustrated by FIG. 4, wherein the cross-sectional view of package 300 is shown. Chip 01 connects to interpolet 06 through multi-row wire bundle 17; and chip 02 also connects to the shared interpolet 06 by multi-row wire bundle 18. The other side of chip 01 is connected to interpolet 05 by wire bundle 16, while chip 03 shares the same interpolet 05 using wire bundle 15. Chip 02 is further connected to interpolet 07 on the outer edge by wire bundle 19, and chip 03 connected to interpolet 04 through wire bundle 14. The bottom TSV contacts of interpolets 04, 05, 06, and 07, respectively, are coupled to the internal conductive traces of RDL 35 for rerouting to the bottom solder balls 36 of package 300. Encapsulant 31 covers all the chips and wires placed on RDL 35. The fabrication can be made using a silicon reconstituted wafer, chips face-down, or using panel as a fan-out panel level package (FOPLP).
[0037] The plane layout of package 300 is also shown by FIG. 5 in a top view. Chip 01 side I/O pads are wire bonded by wire bundle 16 to interpolet 05, and to interpolet 06 by wire bundle 17 in a multi-row manner so that the TSV pitches on interpolet 16 and interpolet 17 are spread out for wider pitches that allow for easier contact alignment by the RDL 35 connecting traces. Chip 02 is connected to interpolet 06 on one side by fan-out wire bundle 18, and to interpolet 07 on the other side by fan-out wire bonding bundle 19. Similarly, chip 03 connects to interpolet 05 by fan-out wire bonding bundle 15 and to interpolet 04 by fan-out wire bonding bundle 14. Hence, all of the chip I/O connections are rerouted though interpolet 04, interpolet 05, interpolet 06, and interpolet 07 to the connecting traces internal to RDL 35. If needed, more interpolets can be placed on the horizontal sides of chip 01, chip 02, and chip 03 for more fan-out wire interconnections.
[0038] In FIG. 6, a stacked chip option is shown by package 500, wherein chip 41 and chip 42 are stacked on top of a face-up bottom chip 40, which uses wire bond bundle 46 to connect to interpolet 43 and wire bond bundle 49 to connect to interpolet 44. Stacked chip 41 connects to the shared interpolet 43 using wire bond bundle 47, and stacked chip 42 connects to interpolet 44 by wire bond bundle 48. Thus, 3D stacked chip assembly is possible even for face-up wire bond chips under the encapsulation 50. The bottom RDL 45 has internal conductive traces linked to the TSV bottom contacts of interpolet 43 and interpolet 44 for rerouting to the external solder balls 59.
[0039] To further illustrate the flexibility in placement options of the interpolets and different fan-out wire bonding schemes, FIG. 7 illustrates a plane view of a package 400 having an underlying RDL 65. Chip 01 could be a large CPU or GPU, and chip 02 and chip 03 could each be a group of interconnected chiplets; chip 04 and chip 05 could each be a memory stack such as a HBM (high bandwidth memory). Chip-to-chip interconnections between chip 01 and chip 02 is through wire bond bundle 75, and between chip 01 and chiplet 03 by wire bond bundle 76. Chip 01 further has chip-to-chip connections to chip 04 through wire bond bundle 72 and to chip 05 through wire bond bundle 78. Chip 02 also has wire bond bundle 80 connected to interpolet 67 and wire bond bundle 81 to interpolet 69. Chip 03 has wire bond bundle 77 connected to interpolet 66 and wire bond bundle 70 to interpolet 68.
[0040] Similarly, chip 05 has wire bond bundle 74 and wire bond bundle 77 connected to interpolet 68 and 69, respectively. Chip 04 has wire bond bundle 71 linked to interpolet 66 and wire bond bundle 73 linked to interpolet 67. Lastly, chip 01 corners have four diagonal wire bond bundles 79 coupled to the four corner interpolets 66, 67, 68, and 69, respectively.
[0041] The chip and interpolet floor placement are flexible based on the number, size, and shape of the chips and interpolets. FIG. 5 and FIG. 7 are just two illustrations of different layout schemes as examples for interconnections by fan-out wire bonding. The key advantage of this invention remains in the flexibility in designing suitable small, inexpensive interpolet slivers with the right amount of TSV contacts and wider pitches for alignment connection to the underlying RDL traces with high yield.
[0042] Furthermore, the assembly of multiple chips in this FOWLP package invention is not limited to the chip-first, die face-up process. In the RDL-first approach, chips are connected to the RDL face-down with micro-bumps. FIG. 8 illustrates a face-down package 600 using the RDL-first approach, wherein the main center chip 06 is flip-chip bonded to its underlying RDL 56 by micro-bumps 57. At the same time, adjacent interpolet 51 and interpolet 52 are also bonded to RDL 56 using micro-bumps 57. Two thin chips, chip 07 and chip 08, are stacked on top of main chip 06 face-up, and wire bonding bundle 54 connect chip 07 to interpolet 52, while wire bond bundle 53 connects chip 08 to interpolet 51. Thus, all of the signal connections from chip 06, chip 07, and chip 08 are rerouted to the bottom solder balls 59 through the RDL 56. Package 600 is therefore a 3D stacked FOWLP package using the low-cost interpolets 51 and 52 and fan-out wire bonding for some of the multiple chips inside the packages.
[0043] The key enabling components for such hybrid FOWLP packages are the tiny copper-filled TSV interpolet slivers (or, interpolets). For low I/O count chips such as chiplets and memory, the size of an interpolet can be small and the TSV diameters can be made large enough to accept direct copper wire bonding to the copper-filled TSV without bond pads. FIG. 9 illustrates the cross-sectional view of a simple interpolet 80 having a TSV array 82 with opening sizes bigger than the bonding wires suitable for direct wire bonding to the top exposed surface 83. For copper oxidation protection, both the top exposed surface 83 and the bottom exposed surface 84 are covered by an OSP (organic solderability preservatives) coating (not shown).
[0044] As an example, the TSV 82 diameter can be 30-um or 40-um so that thin copper wires less than 20 um can be bonded directly to the exposed copper surface 83 of TSV 82. Interpolet 80 can be fabricated from a large, dummy silicon TSV wafer by dicing off different-sized interpolet slivers.
[0045] FIG. 10 illustrates the cross-section of another interpolet 90 having a silicon body 91 with an array of TSV 92, TSV 96, and TSV 97. The top end of TSV 92 is capped with a surface wire bonding pad 93, and the top ends of TSV 96 and TSV 97 are capped with a common wire bonding pad 95. Shared bonding pad 95 can be used for bonding by multiple power and ground wires that require a higher current-carrying capacity. The bottom openings of all TSV are also capped with bonding pads, as shown by pad 94 on TSV 93. Such bottom pads may be optional for linking to the RDL later. In the case for the RDL-first fabrication, interpolet 90 with bottom pads 94 and pad 98 may have micro-bumps attached first before bonding to the RDL. Both the top surface pads 93, 95 and bottom surface pads 94 and 98 are covered by the OSP coating for oxidation protection.
[0046] To further illustrate the structure of interposer sliver 90, FIG. 11 shows a perspective view of the sliver body 91, and an expanded partial top view of the surface wire bond pads. Pad 93 is a VIP (via in pad) on top of TSV 92, while the shared common pad 95 is on top of TSV 97 and TSV 98. Pad 95 can be bonded with multiple wires for higher current-carrying capacity used for power and ground wires. The interpolet sliver 90 can be fabricated from dummy copper-filled TSV silicon wafers, but glass panels or other materials such as ceramics or organic composite materials may also be used to make the copper-filled TSV interpolets.
[0047] By combining the use of inexpensive tiny interpolet slivers and flexible fan-out wire bonding interconnections, multiple chips and their accompanying interpolets can be placed on a fan-out reconstituted wafer in different manners, either chip-first or RDL-first with side-by-side or 3D stacking configurations. The chips may either be placed face-up for wire bonding, or some of the chips placed face-down in the RDL-first approach. For the RDL-first approach, the interpolet slivers may also need micro bumps for bonding to the finished RDL during the die-attach, die-bonding steps.
