Using an interconnect bump to traverse through a passivation layer of a semiconductor die

Abstract

A semiconductor die, which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed. The first passivation layer is over the first semiconductor device, which includes a first group of device fingers. The first interconnect bump is thermally and electrically connected to each of the first group of device fingers. Additionally, the first interconnect bump protrudes through a first opening in the first passivation layer.

Claims

1. A semiconductor die comprising: a transistor having a plurality of device fingers, each of the plurality of device fingers comprising a semiconductor material; a first passivation layer over the transistor; a second passivation layer over the transistor, wherein the first passivation layer is over the second passivation layer; an interconnect bump protruding through a first opening in the first passivation layer and protruding through each of a plurality of openings in the second passivation layer; and an interconnect layer deposited over each of the plurality of device fingers and thermally and electrically connecting the interconnect bump to each of the plurality of device fingers.

2. The semiconductor die of claim 1 wherein the transistor has a plurality of sub-cells, wherein each of the plurality of sub-cells has a corresponding portion of the plurality of device fingers.

3. The semiconductor die of claim 1 wherein the second passivation layer comprises Silicon Dioxide.

4. The semiconductor die of claim 1 wherein a thickness of the second passivation layer adjacent to each of the plurality of openings is between 150 nanometers and 5500 nanometers.

5. The semiconductor die of claim 1 wherein the first passivation layer comprises BenzoCycloButene.

6. The semiconductor die of claim 1 wherein the interconnect bump is configured to conduct heat away from the transistor and provide an electrical connection from the transistor to an external device.

7. The semiconductor die of claim 1 wherein the interconnect bump is a flip chip bump.

8. The semiconductor die of claim 1 wherein the interconnect bump comprises Copper.

9. The semiconductor die of claim 8 wherein the interconnect layer comprises Gold.

10. The semiconductor die of claim 9 wherein the semiconductor material comprises Gallium Arsenide.

11. The semiconductor die of claim 9 wherein the semiconductor material comprises N-type Gallium Arsenide.

12. The semiconductor die of claim 8 further comprising a first under bump metallization layer on the interconnect layer, wherein the interconnect bump is over the first under bump metallization layer.

13. The semiconductor die of claim 12 wherein the first under bump metallization layer comprises Titanium.

14. The semiconductor die of claim 12 wherein a thickness of the first under bump metallization layer is between 500 Angstroms and 1500 Angstroms.

15. The semiconductor die of claim 12 wherein the interconnect bump is on the first under bump metallization layer.

16. The semiconductor die of claim 12 further comprising a second under bump metallization layer, wherein the first under bump metallization layer is on the interconnect layer, the second under bump metallization layer is on the first under bump metallization layer, and the interconnect bump is on the second under bump metallization layer.

17. The semiconductor die of claim 1 wherein the transistor is a heterojunction bipolar transistor.

18. The semiconductor die of claim 1 wherein the transistor is a bipolar junction transistor.

19. The semiconductor die of claim 1 wherein an emitter of the transistor comprises the plurality of device fingers.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

(2) FIG. 1 shows a semiconductor die according to one embodiment of the semiconductor die.

(3) FIG. 2 shows the semiconductor die according to an alternate embodiment of the semiconductor die.

(4) FIG. 3 shows the semiconductor die according to an additional embodiment of the semiconductor die.

(5) FIG. 4 shows the semiconductor die according to another embodiment of the semiconductor die.

(6) FIG. 5 shows the semiconductor die according to a further embodiment of the semiconductor die.

(7) FIG. 6 shows a cross-section of a portion of the semiconductor die illustrated in FIG. 3 according to one embodiment of the cross-section.

(8) FIG. 7 shows the cross-section of the portion of the semiconductor die illustrated in FIG. 3 according to an alternate embodiment of the cross-section.

(9) FIG. 8 shows the cross-section of the portion of the semiconductor die illustrated in FIG. 3 according to an additional embodiment of the cross-section.

(10) FIG. 9 shows the cross-section of the portion of the semiconductor die illustrated in FIG. 3 according to another embodiment of the cross-section.

(11) FIG. 10 shows the semiconductor die attached to an external device according to one embodiment of the semiconductor die.

(12) FIG. 11 illustrates a process for forming the semiconductor die illustrated in FIG. 6 according to one embodiment of the semiconductor die.

(13) FIG. 12 illustrates a process for forming the semiconductor die illustrated in FIG. 9 according to an alternate embodiment of the semiconductor die.

DETAILED DESCRIPTION

(14) The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

(15) It will be understood that when an element such as a layer, region, or substrate is referred to as being over, on, in, or extending onto another element, it can be directly over, directly on, directly in, or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly over, directly on, directly in, or extending directly onto another element, there are no intervening elements present. It will also be understood that when an element is referred to as being coupled to another element, it can be directly coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being directly coupled to another element, there are no intervening elements present. It will also be understood that when an element is referred to as being connected to another element, it can be directly connected to the other element or intervening conductive elements may be present. In contrast, when an element is referred to as being directly connected to another element, there are no intervening conductive elements present.

(16) The term thermally connected is defined herein and for any claims that follow to require a coupling wherein the thermal conductivity of the coupling is greater than or equal to about 10 British thermal units per hour-degree Fahrenheit-foot. The term electrically connected is defined herein and for any claims that follow to require a coupling wherein the electrical resistivity is less than or equal to about 2510.sup.8 ohm-meters. Any intervening conductive elements would have an electrical resistivity of less than or equal to about 2510.sup.8 ohm-meters. Any intervening conductive elements would have a thermal conductivity of greater than or equal to about 10 British thermal units per hour-degree Fahrenheit-foot.

(17) Relative terms such as below or above or upper or lower or horizontal or vertical may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

(18) FIG. 1 shows a 3D view of a semiconductor die 10 according to one embodiment of the semiconductor die 10. The semiconductor die 10 includes a first passivation layer 12, a first interconnect bump 14, and a second interconnect bump 16. In one embodiment of the first passivation layer 12, the first passivation layer 12 is the uppermost layer of the semiconductor die 10.

(19) The first interconnect bump 14 protrudes through the first passivation layer 12 and the second interconnect bump 16 protrudes through the first passivation layer 12. Alternate embodiments of the semiconductor die 10 may include any number of interconnect bumps protruding through the first passivation layer 12.

(20) In one embodiment of the first interconnect bump 14, the first interconnect bump 14 is a flip chip bump. In one embodiment of the second interconnect bump 16, the second interconnect bump 16 is a flip chip bump. In one embodiment of the first interconnect bump 14, the first interconnect bump 14 includes Copper. In an alternate embodiment of the first interconnect bump 14, the first interconnect bump 14 consists of Copper. In another embodiment of the first interconnect bump 14, the first interconnect bump 14 includes any metal. In one embodiment of the second interconnect bump 16, the second interconnect bump 16 includes Copper. In an alternate embodiment of the second interconnect bump 16, the second interconnect bump 16 consists of Copper. In another embodiment of the second interconnect bump 16, the second interconnect bump 16 includes any metal.

(21) In one embodiment of the first interconnect bump 14, a thermal conductivity of the first interconnect bump 14 is greater than or equal to about 10 British thermal units per hour-degree Fahrenheit-foot. In one embodiment of the first interconnect bump 14, an electrical resistivity of the first interconnect bump 14 is less than or equal to about 2510.sup.8 ohm-meters. In one embodiment of the second interconnect bump 16, a thermal conductivity of the second interconnect bump 16 is greater than or equal to about 10 British thermal units per hour-degree Fahrenheit-foot. In one embodiment of the second interconnect bump 16, an electrical resistivity of the second interconnect bump 16 is less than or equal to about 2510.sup.8 ohm-meters.

(22) In one embodiment of the first interconnect bump 14, a height of the first interconnect bump 14 is between about 40 micrometers and about 100 micrometers. In one embodiment of the second interconnect bump 16, a height of the second interconnect bump 16 is between about 40 micrometers and about 100 micrometers. In one embodiment of the first interconnect bump 14, a width of the first interconnect bump 14 is between about 70 micrometers and about 90 micrometers and a length of the first interconnect bump 14 is between about 80 micrometers and about 500 micrometers. In one embodiment of the second interconnect bump 16, a width of the second interconnect bump 16 is between about 70 micrometers and about 90 micrometers and a length of the second interconnect bump 16 is between about 80 micrometers and about 500 micrometers.

(23) In one embodiment of the first interconnect bump 14, the vertical corners of the first interconnect bump 14 are rounded. In one embodiment of the first interconnect bump 14, the horizontal corners of the first interconnect bump 14 are rounded. In one embodiment of the second interconnect bump 16, the vertical corners of the second interconnect bump 16 are rounded. In one embodiment of the second interconnect bump 16, the horizontal corners of the second interconnect bump 16 are rounded. In an alternate embodiment of the first interconnect bump 14, the first interconnect bump 14 is of any shape. In an alternate embodiment of the second interconnect bump 16, the second interconnect bump 16 is of any shape.

(24) FIG. 2 shows a top view of the semiconductor die 10 according to an alternate embodiment of the semiconductor die 10. The semiconductor die 10 illustrated in FIG. 2 is similar to the semiconductor die 10 illustrated in FIG. 1, except in the semiconductor die 10 illustrated in FIG. 2, the first interconnect bump 14 and the second interconnect bump 16 are not shown for clarity.

(25) The first passivation layer 12 has a first opening 18 and a second opening 20. The first interconnect bump 14 (FIG. 1) protrudes through the first opening 18 in the first passivation layer 12 and the second interconnect bump 16 (FIG. 1) protrudes through the second opening 20 in the first passivation layer 12. The semiconductor die 10 further includes a first semiconductor device 22 and a second semiconductor device 24. The first semiconductor device 22 and the second semiconductor device 24 can be seen through the first opening 18 and the second opening 20, respectively. As such, the first passivation layer 12 is over the first semiconductor device 22 and the first passivation layer 12 is over the second semiconductor device 24. In one embodiment of the first semiconductor device 22 and the second semiconductor device 24, the first opening 18 is directly over the first semiconductor device 22 and the second opening 20 is directly over the second semiconductor device 24.

(26) The first semiconductor device 22 has a first group 26 of device fingers and the second semiconductor device 24 has a second group 28 of device fingers. The first interconnect bump 14 (FIG. 1) is thermally and electrically connected to each of the first group 26 of device fingers. The second interconnect bump 16 (FIG. 1) is thermally and electrically connected to each of the second group 28 of device fingers.

(27) In one embodiment of the semiconductor die 10, the first interconnect bump 14 (FIG. 1) is configured to conduct heat away from the first semiconductor device 22. Further, in one embodiment of the semiconductor die 10, the first interconnect bump 14 (FIG. 1) is further configured to provide an external electrical connection to the first semiconductor device 22. Due to its relative size and form factor, the first interconnect bump 14 (FIG. 1) may have high thermal conductivity and low electrical resistivity. Therefore, by thermally and electrically connecting to each of the first group 26 of device fingers through the first opening 18 in the first passivation layer 12, the first interconnect bump 14 (FIG. 1) may provide improved thermal and electrical connectivity over existing designs.

(28) In one embodiment of the semiconductor die 10, the second interconnect bump 16 (FIG. 1) is configured to conduct heat away from the second semiconductor device 24. Further, in one embodiment of the semiconductor die 10, the second interconnect bump 16 (FIG. 1) is further configured to provide an external electrical connection to the second semiconductor device 24. Due to its relative size and form factor, the second interconnect bump 16 (FIG. 1) may have high thermal conductivity and low electrical resistivity. Therefore, by thermally and electrically connecting to each of the second group 28 of device fingers through the second opening 20 in the first passivation layer 12, the second interconnect bump 16 (FIG. 1) may provide improved thermal and electrical connectivity over existing designs.

(29) In one embodiment of the first passivation layer 12, the first passivation layer 12 includes BenzoCycloButene. In an alternate embodiment of the first passivation layer 12, the first passivation layer 12 includes Polyimide. In another embodiment of the first passivation layer 12, the first passivation layer 12 includes any passivation material.

(30) The first semiconductor device 22 has a first group 30 of sub-cells, such that each of the first group 30 of sub-cells has a corresponding portion of the first group 26 of device fingers. For example, in the first semiconductor device 22 illustrated in FIG. 2, the first group 26 of device fingers has 12 device fingers and each of the first group 30 of sub-cells has 4 device fingers.

(31) Similarly, the second semiconductor device 24 has a second group 32 of sub-cells, such that each of the second group 32 of sub-cells has a corresponding portion of the second group 28 of device fingers. For example, in the second semiconductor device 24 illustrated in FIG. 2, the second group 28 of device fingers has 12 device fingers and each of the second group 32 of sub-cells has 4 device fingers.

(32) Alternate embodiments of the semiconductor die 10 may include any number of semiconductor devices. Each semiconductor device may include any number of device fingers. Further, each semiconductor device may include any number of sub-cells. Each sub-cell may include any number of device fingers. Further, the semiconductor die 10 may include any number of interconnect bumps and the first passivation layer 12 may include any number of openings as long as each interconnect bump protrudes through an opening in the first passivation layer 12.

(33) FIG. 3 shows the semiconductor die 10 according to an additional embodiment of the semiconductor die 10. The semiconductor die 10 illustrated in FIG. 3 is similar to the semiconductor die 10 illustrated in FIG. 2, except in the semiconductor die 10 illustrated in FIG. 3, the semiconductor die 10 further includes a second passivation layer 34. The first passivation layer 12 is over the second passivation layer 34. As such, the second passivation layer 34 is visible through the first opening 18 and through the second opening 20. The second passivation layer 34 is over the first semiconductor device 22 (FIG. 2) and over the second semiconductor device 24 (FIG. 2). Further, the second passivation layer 34 has a first group 36 of openings and a second group 38 of openings.

(34) In one embodiment of the second passivation layer 34, the second passivation layer 34 includes Silicon Dioxide. In one embodiment of the second passivation layer 34, the second passivation layer 34 includes Silicon Nitride. In another embodiment of the second passivation layer 34, the second passivation layer 34 includes any passivation material. In one embodiment of the second passivation layer 34, a thickness of the second passivation layer 34 adjacent to each of the first group 36 of openings is between about 150 nanometers and about 5500 nanometers. In one embodiment of the second passivation layer 34, a thickness of the second passivation layer 34 adjacent to each of the second group 38 of openings is between about 150 nanometers and about 5500 nanometers.

(35) In one embodiment of the second passivation layer 34, each of the first group 36 of openings is directly over a corresponding one of the first group 30 (FIG. 2) of sub-cells. As such, in one embodiment of the first interconnect bump 14 (FIG. 1), the first interconnect bump 14 (FIG. 1) further protrudes through each of the first group 36 of openings. In one embodiment of the second passivation layer 34, each of the second group 38 of openings is directly over a corresponding one of the second group 32 (FIG. 2) of sub-cells. As such, in one embodiment of the second interconnect bump 16 (FIG. 1), the second interconnect bump 16 (FIG. 1) further protrudes through each of the second group 38 of openings. A location of a cross-section 40 of a portion of the semiconductor die 10 is illustrated in FIG. 3.

(36) FIG. 4 shows the semiconductor die 10 according to another embodiment of the semiconductor die 10. The semiconductor die 10 illustrated in FIG. 4 is similar to the semiconductor die 10 illustrated in FIG. 1, except in the semiconductor die 10 illustrated in FIG. 4, the second interconnect bump 16 (FIG. 1) is omitted.

(37) FIG. 5 shows the semiconductor die 10 according to a further embodiment of the semiconductor die 10. The semiconductor die 10 illustrated in FIG. 5 is similar to the semiconductor die 10 illustrated in FIG. 2, except in the semiconductor die 10 illustrated in FIG. 5, the second opening 20 is omitted and the first opening 18 is elongated, such that the first opening 18 is over both the first semiconductor device 22 and the second semiconductor device 24. In this regard, the first interconnect bump 14 (FIG. 4) is thermally and electrically connected to both the first group 26 of device fingers and the second group 28 of device fingers.

(38) FIG. 6 shows the cross-section 40 of the portion of the semiconductor die 10 illustrated in FIG. 3 according to one embodiment of the cross-section 40. The cross-section 40 includes one of the first group 30 of sub-cells (FIG. 2) of the first semiconductor device 22 (FIG. 2); therefore, the cross-section 40 includes a portion of the first group 26 of device fingers. The cross-section 40 further includes a portion of the first passivation layer 12, a portion of the second passivation layer 34, a first semiconductor material 42, a base mesa 44, first semiconductor material contacts 46, base contacts 48, a second semiconductor material 50, a dielectric material 52, and a first interconnect layer 54. As such, four of the first group 26 of device fingers are illustrated.

(39) The first semiconductor material contacts 46 are on the first semiconductor material 42. The base mesa 44 is on the first semiconductor material 42. The base contacts 48 are on the base mesa 44. Each of the portion of the first group 26 of device fingers is on the base mesa 44. Further, each of the first group 26 of device fingers includes a corresponding portion of the second semiconductor material 50 and a corresponding portion of the first interconnect layer 54, such that each corresponding portion of the first interconnect layer 54 is on the corresponding portion of the second semiconductor material 50. The dielectric material 52 insulates the base contacts 48 from the portion of the first group 26 of device fingers.

(40) In the embodiment of the cross-section 40 illustrated in FIG. 6, the first interconnect layer 54 provides a connection between the portion of the first group 26 of device fingers of the one of the first group 30 of sub-cells (FIG. 2). In an alternate embodiment of the cross-section 40 (not shown), the first interconnect layer 54 does not provide the connection between the portion of the first group 26 of device fingers of the one of the first group 30 of sub-cells (FIG. 2).

(41) The second passivation layer 34 is on a portion of the first interconnect layer 54 and is on a portion of the dielectric material 52. The first passivation layer 12 is on a portion of the second passivation layer 34. Therefore, only a portion of the first interconnect layer 54, a portion of the second passivation layer 34, and the first passivation layer 12 are exposed. A portion of the first opening 18 and one of the first group 36 of openings are identified for clarity.

(42) In one embodiment of the first interconnect layer 54, the first interconnect layer 54 includes gold. In one embodiment of the first interconnect layer 54, the first interconnect layer 54 includes any metal. In one embodiment of the first semiconductor material 42, the first semiconductor material 42 includes Gallium Arsenide. In one embodiment of the first semiconductor material 42, the first semiconductor material 42 includes Gallium Nitride. In one embodiment of the first semiconductor material 42, the first semiconductor material 42 includes Silicon. In one embodiment of the first semiconductor material 42, the first semiconductor material 42 includes N-type Gallium Arsenide. In one embodiment of the first semiconductor material 42, the first semiconductor material 42 includes P-type Gallium Arsenide.

(43) In one embodiment of the second semiconductor material 50, the second semiconductor material 50 includes Gallium Arsenide. In one embodiment of the second semiconductor material 50, the second semiconductor material 50 includes Gallium Nitride. In one embodiment of the second semiconductor material 50, the second semiconductor material 50 includes Silicon. In one embodiment of the second semiconductor material 50, the second semiconductor material 50 includes N-type Gallium Arsenide. In one embodiment of the second semiconductor material 50, the second semiconductor material 50 includes P-type Gallium Arsenide. In one embodiment of the base mesa 44, the base mesa 44 includes Gallium Arsenide. In one embodiment of the base mesa 44, the base mesa 44 includes Gallium Nitride. In one embodiment of the base mesa 44, the base mesa 44 includes Silicon. In one embodiment of the base mesa 44, the base mesa 44 includes P-type Gallium Arsenide. In one embodiment of the base mesa 44, the base mesa 44 includes N-type Gallium Arsenide.

(44) In one embodiment of the first semiconductor device 22 (FIG. 2), the first semiconductor device 22 (FIG. 2) is a transistor. In one embodiment of the transistor, an emitter of the transistor includes the first group 26 of device fingers. In one embodiment of the transistor, a collector of the transistor includes the first group 26 of device fingers. In one embodiment of the first semiconductor device 22 (FIG. 2), the first semiconductor device 22 (FIG. 2) is a heterojunction bipolar transistor. In one embodiment of the first semiconductor device 22 (FIG. 2), the first semiconductor device 22 (FIG. 2) is a bipolar junction transistor.

(45) FIG. 7 shows the cross-section 40 of the portion of the semiconductor die 10 illustrated in FIG. 3 according to an alternate embodiment of the cross-section 40. The cross-section 40 illustrated in FIG. 7 is similar to the cross-section 40 illustrated in FIG. 6, except in the cross-section 40 illustrated in FIG. 7, the first interconnect bump 14 is on the first passivation layer 12, the second passivation layer 34, and the first interconnect layer 54. Further, the first interconnect bump 14 protrudes through the first passivation layer 12 and through the second passivation layer 34. Also, the first interconnect bump 14 is thermally and electrically connected to the first semiconductor device 22 (FIG. 2) via the first interconnect layer 54.

(46) FIG. 8 shows the cross-section 40 of the portion of the semiconductor die 10 illustrated in FIG. 3 according to an additional embodiment of the cross-section 40. The cross-section 40 illustrated in FIG. 8 is similar to the cross-section 40 illustrated in FIG. 7, except in the cross-section 40 illustrated in FIG. 8, the semiconductor die 10 (FIG. 3) further includes a first under bump metallization layer 56 on the first interconnect layer 54, such that the first interconnect bump 14 is on the first under bump metallization layer 56. In general, the first interconnect bump 14 is over the first interconnect layer 54. In one embodiment of the first under bump metallization layer 56, the first under bump metallization layer 56 includes Titanium. In one embodiment of the first under bump metallization layer 56, the first under bump metallization layer 56 includes any metal. In one embodiment of the first under bump metallization layer 56, a thickness of the first under bump metallization layer 56 is between about 500 Angstroms and about 1500 Angstroms. In one embodiment of the first under bump metallization layer 56, the first under bump metallization layer 56 is a seed layer for the first interconnect bump 14. In one embodiment of the first under bump metallization layer 56, the first under bump metallization layer 56 promotes adhesion to the first interconnect layer 54. In one embodiment of the first under bump metallization layer 56, the first under bump metallization layer 56 substantially prevents electro-migration of the first interconnect layer 54.

(47) FIG. 9 shows the cross-section 40 of the portion of the semiconductor die 10 illustrated in FIG. 3 according to another embodiment of the cross-section 40. The cross-section 40 illustrated in FIG. 9 is similar to the cross-section 40 illustrated in FIG. 8, except in the cross-section 40 illustrated in FIG. 9, the semiconductor die 10 (FIG. 3) further includes a second under bump metallization layer 58 on the first under bump metallization layer 56, such that the first interconnect bump 14 is on the second under bump metallization layer 58. In general, the semiconductor die 10 (FIG. 3) includes at least one under bump metallization layer 56, 58 on the first interconnect layer 54, such that the first interconnect bump 14 is on the at least one under bump metallization layer 56, 58.

(48) In one embodiment of the second under bump metallization layer 58, the second under bump metallization layer 58 includes Copper. In one embodiment of the second under bump metallization layer 58, the second under bump metallization layer 58 includes Tungsten. In one embodiment of the second under bump metallization layer 58, the second under bump metallization layer 58 includes any metal. In one embodiment of the second under bump metallization layer 58, a thickness of the second under bump metallization layer 58 is between about 3000 Angstroms and about 5000 Angstroms. In one embodiment of the first under bump metallization layer 56 and the second under bump metallization layer 58, the first under bump metallization layer 56 and the second under bump metallization layer 58 are seed layers for the first interconnect bump 14. In one embodiment of the first under bump metallization layer 56, the first under bump metallization layer 56 promotes adhesion to the first interconnect layer 54. In one embodiment of the first under bump metallization layer 56, the first under bump metallization layer 56 substantially prevents electro-migration of the first interconnect layer 54.

(49) FIG. 10 shows the semiconductor die 10 attached to an external device according to one embodiment of the semiconductor die 10. FIG. 10 illustrates a front-view of the semiconductor die 10 illustrated in FIG. 4. Solder 60 is on the first interconnect bump 14 and a laminate 62 is on the solder 60. As such, the first interconnect bump 14 is soldered to the laminate 62. Since the laminate 62 is an external device, the first interconnect bump 14 provides an electrical connection from the first semiconductor device 22 (FIG. 5) to an external device. Further, the first interconnect bump 14 provides an electrical connection from the second semiconductor device 24 (FIG. 5) to an external device. In one embodiment of the solder 60, a thickness of the solder 60 is equal to about 25 micrometers. In one embodiment of the solder 60, the solder 60 is a Tin/Silver alloy. Other embodiments of the solder 60 may include other metals or other metal alloys.

(50) In one embodiment of the laminate 62, the laminate 62 functions as a heatsink. In one embodiment of the laminate 62, the laminate 62 is configured to conduct heat away from the first semiconductor device 22 (FIG. 5) via the first interconnect bump 14. In an alternate embodiment of the laminate 62, the laminate 62 is configured to conduct heat away from both the first semiconductor device 22 (FIG. 5) and the second semiconductor device 24 (FIG. 5) via the first interconnect bump 14. In one embodiment of the laminate 62, the laminate 62 provides a ground connection to the semiconductor die 10 via the first interconnect bump 14. In an alternate embodiment of the laminate 62, the laminate 62 provides a power supply connection to the semiconductor die 10 via the first interconnect bump 14.

(51) FIG. 11 illustrates a process for forming the semiconductor die 10 illustrated in FIG. 6 according to one embodiment of the semiconductor die 10. Provide a semiconductor die 10 (FIG. 2), which includes a first semiconductor device 22 (FIG. 2) having a first group 26 (FIG. 2) of device fingers and a first passivation layer 12 (FIG. 2) over the first semiconductor device 22 (FIG. 2) (Step 100). Form a first interconnect bump 14 (FIG. 1), which is thermally and electrically connected to each of the first group 26 (FIG. 2) of device fingers, such that the first interconnect bump 14 (FIG. 1) protrudes through a first opening 18 (FIG. 2) in the first passivation layer 12 (FIG. 2) (Step 102).

(52) FIG. 12 illustrates a process for forming the semiconductor die 10 illustrated in FIG. 9 according to an alternate embodiment of the semiconductor die 10. Provide a semiconductor die 10 (FIG. 2), which includes a first semiconductor device 22 (FIG. 2) having a first group 26 (FIG. 2) of device fingers and a first passivation layer 12 (FIG. 2) over the first semiconductor device 22 (FIG. 2), wherein each of the first group 26 (FIG. 2) of device fingers includes a corresponding portion of a semiconductor material 50 (FIG. 9) and a corresponding portion of a first interconnect layer 54 (FIG. 9), such that each corresponding portion of the first interconnect layer 54 (FIG. 9) is on the corresponding portion of the semiconductor material 50 (FIG. 9) (Step 200). Form at least one under bump metallization layer 56, 58 (FIG. 9) on the first interconnect layer 54 (FIG. 9) (Step 202). In one embodiment of the at least one under bump metallization layer 56, 58 (FIG. 9), at least one under bump metallization layer 56, 58 (FIG. 9) is formed by sputtering. Form a first interconnect bump 14 (FIG. 1) on the at least one under bump metallization layer 56, 58 (FIG. 9), such that the first interconnect bump 14 (FIG. 1) protrudes through a first opening 18 (FIG. 2) in the first passivation layer 12 (FIG. 2) (Step 204). In one embodiment of the first interconnect bump 14 (FIG. 1), the first interconnect bump 14 (FIG. 1) is formed by electroplating.

(53) Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.