A system which identifies a memory device using a physical unclonable function. The system performs raw read operations on every page of a block; sorts the pages into low and high groups using an average number of ones based on the raw read operations; generates unordered page pairs by sequentially selecting a first page from the low group and a second page from the high group; generates ordered page pairs by selectively converting an order of pages in each pair of the unordered page pairs; and generates a sequence for identifying the selected block based on comparing the average number of ones for pages in each ordered page pair.

Apparatuses and techniques are described for obtaining a threshold voltage distribution for a set of memory cells based on a user read mode. The user read mode can be based on various factors including a coding of a page and an increasing or decreasing order of the read voltages. The read process for the Vth distribution is made to mimic the read mode which is used when the memory device is in the hands of the end user. This results in a Vth distribution which reflects the user's experience to facilitate troubleshooting. In some cases, one or more dummy read operations are performed, where the read result is discarded, prior to a read operation which is used to build the Vth distribution.

A non-volatile memory device, described herein, comprises: a plurality of memory strings and at least one control circuit in communication with the non-volatile memory cell array. The at least one control circuit is configured to perform, for the plurality of memory strings, one erase-verify iteration in an erase operation including determining whether at least one memory string of the plurality of memory strings passes an erase-verify test. The at least one control circuit is configured to, if the at least one memory string passes the erase-verify test, inhibit the at least one memory string for erase including ramping up, to an erase voltage, of a voltage applied to a gate of a SGD transistor of the at least one memory string and to perform a next erase-verify iteration in the erase operation for remaining memory strings of the plurality of memory strings other than the at least one memory string.

A storage device that includes a non-volatile memory is provided. The non-volatile memory includes a control circuitry that is communicatively coupled to a memory block that includes memory cells arranged word lines. The control circuitry is configured to program the memory cells of a selected word line in a plurality of programming loops to store a single bit of data in each memory cell of the selected word line. The programming loops include programming operations and verify operations. The programming operations include applying a programming voltage to the selected word line, and the verify operations include applying a verify voltage to the selected word line. At least one programming loop of the plurality of programming loops further includes a pre-verify operation. The pre-verify operation includes applying a pre-read voltage to the selected word line. The pre-read voltage is less than the verify voltage.

Integrated circuit devices might include a voltage regulator comprising an input and an output, a selectively activated current path connected between the input and output, and a controller configured to cause the integrated circuit device to connect the output to the input through the current path when a voltage level of the input has a first voltage level, maintain the connection of the output and the input through the current path until the voltage level of the input has a second voltage level higher than the first voltage level, isolate the output from the input through the current path after the voltage level of the input has the second voltage level, and regulate a voltage level of the output while the output is isolated from the input through the current path.

The present technology relates to an electronic device. According to the present technology, a memory device having improved verify accuracy may include a memory block including memory cells, a read and write circuit including a plurality of page buffers, a current sensing circuit configured to perform a verify operation of comparing sensing voltages with a reference voltage, and a control logic configured to control the current sensing circuit to perform the verify operation. The control logic controls performing a first verify operation on each of page buffer groups having a same logical group number, and performing a second verify operation on each of page buffer groups having a same physical group number, and the current sensing circuit outputs a verify pass signal in response to both results of the first verify operation and the second verify operation satisfying a pass criterion.

A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

A semiconductor storage device includes a memory cell array, a peripheral circuit configured to perform writing of data to the memory cell array and reading of data from the memory cell array, and a sampling circuit configured to execute a sampling process by which sampling data is collected from a predetermined node of the peripheral circuit, during a period in which the peripheral circuit performs the writing of data to the memory cell array or the reading of data from the memory cell array.

Systems, methods and apparatus to read target memory cells having an associated reference memory cell configured to be representative of drift or changes in the threshold voltages of the target memory cells. The reference cell is programmed to a predetermined threshold level when the target cells are programmed to store data. In response to a command to read the target memory cells, estimation of a drift of the threshold voltage of the reference is performed in parallel with applying an initial voltage pulse to read the target cells. Based on a result of the drift estimation, voltage pulses used to read the target cells can be modified and/or added to account for the drift estimated using the reference cell.

Sensing devices might include a first voltage node configured to receive a first voltage level, a second voltage node configured to receive a second voltage level lower than the first voltage level, a p-type field-effect transistor (pFET) selectively connected to a data line, and a sense node selectively connected to the pFET. The pFET might be connected between the first voltage node and the data line, between the second voltage node and the data line, and between the first voltage node and the data line. Memories might have controllers configured to cause the memories to determine whether a memory cell has an intended threshold voltage using similar sensing devices.