MEMS COMPONENT HAVING A HIGH INTEGRATION DENSITY

Abstract

A MEMS component having increased integration density and a method for manufacturing such a component are specified. The component comprises a base wafer and a cover wafer arranged over this. A first cavity is arranged between the base wafer and the cover wafer. A second cavity is arranged over the cover wafer, below a thin-layer covering. The cavities contain component structures.

Claims

1. MEMS component (MB) comprising a base wafer (BW) and a cover wafer (DW) arranged over this, a first cavity (H1) between the base wafer (BW) and the cover wafer (DW), and first component structures (BS1) in the first cavity (H1), a second cavity (H2) over the cover wafer (DW), and second component structures (BS2) in the second cavity (H2), a frame (R) that laterally encloses the first cavity (H1), and a thin-layer covering (DSA) that covers the second cavity (H2).

2. MEMS component according to the previous claim, also comprising a sealing layer (VS), wherein the thin-layer covering (DSA) contains a hole (L), and the sealing layer (VS) is arranged over the thin-layer covering (DSA) and seals the hole (L).

3. MEMS component according to any of the previous claims, also comprising a reinforcement layer (VST) that is arranged over the thin-layer covering (DSA) and mechanically reinforces this.

4. MEMS component according to any of the previous claims, also comprising a planarization layer (PS) that is arranged over the thin-layer covering (DSA) and has a flat top side.

5. MEMS component according to any of the previous claims, also comprising a rewiring layer (US) that contains a dielectric material as well as a signal conductor (SL) and is arranged over the thin-layer covering (DSA).

6. MEMS component according to the previous claim, also comprising a circuit element that is arranged in the rewiring layer and is selected from: a passive circuit element, an inductive element, a capacitive element, a resistive element, and a stripline.

7. MEMS component according to any of the previous claims, also comprising a passivation layer (PAS) that is arranged over the thin-layer covering (DSA).

8. MEMS component according to any of the previous claims, also comprising a first electrical connection surface on the top side of the component (MB) and a signal conductor (SL) that connects the first component structures (BS1) with the first connection surface and travels at least in segments on an outer, lateral surface (ASF) of the component (MB).

9. MEMS component according to any of the previous claims, also comprising a second connection surface on the top side of the component (MB) and a throughplating (DK) that connects the second component structures (BS2) with the second connection surface.

10. MEMS component according to any of the previous claims that contains no throughplating (DK) through the cover wafer (DW).

11. MEMS component according to any of the previous claims, wherein the first (BS1) and second (BS2) component structures are selected from: SAW structures, BAW structures, GBAW structures, microphone membranes, MEMS structures.

12. MEMS component according to any of the previous claims, comprising a sealing layer (VS) whose material is selected from: a dielectric material, an organic material, a polymer, BCB, an inorganic material, a silicon nitride, a silicon oxide, an aluminum oxide; a reinforcement layer (VST) whose material is selected from: a dielectric material, an organic material, a polymer, BCB, an inorganic material, a silicon nitride, a silicon oxide, an aluminum oxide; a planarization layer (PS) whose material is selected from: a dielectric material, an organic material, a polymer, BCB, a laminate, an inorganic material, a silicon nitride, a silicon oxide, an aluminum oxide; a passivation layer (PAS) and/or a rewiring layer (US) whose material is respectively selected from: a dielectric material, an organic material, a polymer, BCB, a solder resist, an inorganic material, a silicon nitride, a silicon oxide, an aluminum oxide.

13. MEMS component according to any of the previous claims, wherein the base wafer (BW) and the cover wafer (DW) are comprised of the same material or of materials having nearly identical coefficients of thermal expansion.

14. Method for producing a MEMS component (MB), including the steps: provide a base wafer (BW), generate first component structures (BS1) and a frame (R) on the same base wafer (BW), provide a cover wafer (DW), generate second component structures (BS2) on the cover wafer (DW), arrange the cover wafer (DW) on the frame (F), and form a first cavity (H1) between base wafer (BW), cover wafer (DW) and frame (R), form a thin-layer covering (DSA) over the second component structures (BS2).

15. Method according to the previous claim, wherein the steps to form the thin-layer covering (DSA) include the following sub-steps: apply a sacrificial material (OM) onto the second component structures (BS2), deposit a thin-layer covering (DSA) onto the sacrificial material (OM) in the form of a thin layer, by means of a layer deposition method, structure at least one hole (L) in the thin-layer covering (DSA), remove the sacrificial material (OM) below the thin-layer covering (DSA).

Description

[0053] Ideas and functional principles that form the basis of the MEMS component or of the method for producing such a component, as well as examples of designs and embodiments, are explained in detail using schematic Figures.

[0054] Shown are:

[0055] FIG. 1: a simple embodiment of the MEMS component,

[0056] FIG. 2: an additional embodiment of the component, with connection possibilities on its top side,

[0057] FIG. 3: a first intermediate step in the manufacturing of the component,

[0058] FIG. 4: a second intermediate step in the manufacturing of the component,

[0059] FIG. 5: an additional intermediate step in the manufacturing of the component,

[0060] FIG. 6: an additional intermediate step,

[0061] FIG. 7: an additional intermediate step,

[0062] FIG. 8: an additional intermediate step,

[0063] FIG. 9: an additional intermediate step,

[0064] FIG. 10: an additional intermediate step in the manufacturing of the upper part of the component,

[0065] FIG. 11: an additional intermediate step in which the upper part of the component and the lower part of the component are joined,

[0066] FIG. 12: an additional intermediate step,

[0067] FIG. 13: an additional intermediate step,

[0068] FIG. 14: finished components as a result, after manufacturing,

[0069] FIG. 15: an additional embodiment of the MEMS component.

[0070] FIG. 1 shows a possible embodiment of the component in which the BAW component structures are arranged as first component structures in the first cavity H1 and additional BAW component structures are arranged as second component structures in the second cavity H2. A frame R serves as a spacer and seal—for example a hermetic seal given use of metal as a frame material—between the cover wafer DW and the base wafer BW. The first component structures are arranged directly on the base wafer BW. Additional acoustic mirror layers arranged between the BAW structures in the first cavity H1 and the base wafer BW are likewise possible, but are not shown for the sake of a simplified overview. Acoustic mirror layers may likewise be arranged on the cover wafer DW and below the second component structures. A thin-layer covering DSA upwardly bounds the second cavity H2 and covers the second component structures. A planarization layer PS with flat top side is arranged on the thin-layer covering DSA. A signal conductor SL travels on the outside of the component MB, at least in segments. Via such a signal conductor SL, the various component structures may be connected with one another, and if applicable with connection pads on the outside (for example on the top side) of the component MB.

[0071] Via signal conductors SL directed on the outside of the component MB, the disadvantages linked with throughplatings through the cover wafer DW are avoided in particular.

[0072] FIG. 2 shows an embodiment of the component in which the lateral surfaces of the component are beveled and signal conductors SL are arranged on the beveled lateral surfaces, which signal conductors SL connect component structures with contact surfaces KF on the top side of the component. The first component structures BS1 as BAW component structures and the second component structures BS2 as BAW component structures are shown as examples. In addition to the first component structures BS1, additional component structures are contained in the first cavity. In addition to the second cavity H2, above the cover wafer DW exists a further cavity that has essentially a design similar to that of the second cavity H2. Arranged over the planarization layer PS is a rewiring layer US. Traveling therein are segments of signal conductors that are connected via throughplatings DK with contact surfaces KF. Via the rewiring layer US, it is essentially possible to select the layer of the contact surfaces KF so that the component may be directly connected with predetermined contact surfaces of an external circuit environment, and the layer of the component structures may nevertheless be freely selected in the component.

[0073] FIG. 3 shows a first intermediate step for the production of a corresponding MEMS component in which first component structures BS1 (here shown as BAW component structures, for example) are arranged on a large-area base wafer BW.

[0074] FIG. 4 shows an additional intermediate step in which additional frame structures R are arranged on the top side of the base wafer BW. The first component structures BS1 and the frame structures may thus be created in a repeat usage, meaning before the individualization of the base wafer into a plurality of individual component segments.

[0075] FIG. 5 shows an additional intermediate step, wherein second component structures are arranged on the top side of the cover wafer DW. The second component structures are covered by a thin-layer covering, such that no frame structures are necessary on the top side of the cover wafer DW. As shown in FIG. 6, instead a sacrificial material OM is generated and shaped over the second component structures. The shape of the sacrificial material OM therein significantly determines the shape of the later cavity H2.

[0076] As shown in FIG. 7, the material of the thin-layer covering DSA is deposited on the material of the sacrificial layer OM.

[0077] FIG. 8 shows an additional intermediate step, wherein holes L have been structured in the thin-layer covering DSA.

[0078] FIG. 9 shows an additional intermediate step, wherein the sacrificial material OM has been removed through the holes in the thin-layer covering.

[0079] FIG. 10 shows an additional intermediate step, wherein the holes in the thin-layer covering are sealed by a sealing layer VS, and the thin-layer covering DSA is reinforced by a reinforcement layer VST and covered by a planarization layer PS. A rewiring layer US was arranged over the planarization layer PS. Throughplatings DK through the material of the planarization layer PS connect signal conductors on the top side of the cover wafer DW with signal conductors on the top side of the planarization layer PS, i.e. with signal conductors embedded in the rewiring layer US. The component structures may be connected with contact surfaces on the top side of the component via an additional throughplating through the rewiring layer US. The component may have a passivation layer PAS. The passivation layer PAS may be an additional layer and one of the uppermost layers. The passivation layer may also coincide with one of the other layers, for example the rewiring layer US.

[0080] FIG. 11 shows an additional intermediate step in which the upper parts of the component (see FIGS. 5-10) are already individualized and connected with the frame structures R on the base wafer BW. Cover wafer DW and base wafer BW may be connected with one another via the frame R, for example via the typical bonding methods.

[0081] FIG. 12 shows an additional intermediate step in which segment [sic] of the lateral surfaces ASF of the components are beveled. Given beveling, material of the cover wafer of the planarization layer is removed so that signal conductors on the top side of the base wafer are uncovered.

[0082] FIG. 13 accordingly shows how the uncovered signal conductors are connected with one another by depositing a conductive material.

[0083] FIG. 14 shows finished components in which the base wafer is ultimately also cut through along the individualization lines provided for this. The contact surfaces on the top side of the components are occupied by solder balls so that a connection with external circuit environments is possible via bump joints BU.

[0084] FIG. 15 shows an embodiment of a MEMS component which, within the rewiring layer US, receives an embedded inductive element IE, for example. Other circuit elements are likewise possible, especially passive circuit elements within the rewiring layer US.

[0085] The component, or the method for manufacturing the component, is not limited to the shown exemplary embodiments. Components having additional cavities, additional wafers or additional thin-layer coverings, or manufacturing methods for accordingly more complex component elements, are likewise covered by the claims.

LIST OF REFERENCE SIGNS

[0086] ASF: beveled lateral surface [0087] BS1: first component structures [0088] BS2: second component structures [0089] BU: bump joint [0090] BW: base wafer [0091] DK: throughplating [0092] DSA: thin-layer covering [0093] DW: cover wafer [0094] H1: first cavity [0095] H2: second cavity [0096] IE: inductive element [0097] KF: contact surface [0098] L: hole [0099] MB: MEMS component [0100] OM: sacrificial material [0101] PAS: passivation layer [0102] PS: planarization layer [0103] R: frame [0104] SL: signal conductor [0105] US: rewiring layer [0106] VS: sealing layer [0107] VST: reinforcement layer