HETEROGENEOUS INTEGRATION OF 3D SI AND III-V VERTICAL NANOWIRE STRUCTURES FOR MIXED SIGNAL CIRCUITS FABRICATION

Abstract

A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or Si.sub.xGe.sub.1-x substrate; forming a conformal SiN, SiO.sub.xC.sub.yN.sub.z layer over side and bottom surfaces of the first trenches; filling the first trenches with SiO.sub.x; forming a first mask over portions of the Si, Ge, III-V, or Si.sub.xGe.sub.1-x substrate; removing exposed portions of the Si, Ge, III-V, or Si.sub.xGe.sub.1-x substrate, forming second trenches; forming III-V, III-V.sub.xM.sub.y, or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-V, III-V.sub.xM.sub.y, or Si nanowires and intervening first trenches; removing the SiO.sub.x layer, forming third trenches; and removing the second mask.

Claims

1. A method comprising: forming a substrate stack including an amorphous silicon (a-Si) followed by n or p doping or doped polysilicon (poly-Si) layer and a silicon oxycarbide (SiOC) layer; forming first and second groups of trenches in the substrate stack down to the doped a-Si/poly-Si layer of the substrate stack; forming a first mask over the second group of trenches; forming silicon (Si), germanium (Ge) or silicon germanium (Si.sub.xGe.sub.1-x) nanowires in the first group of trenches; removing the first mask and forming a second mask over the Si, Ge, or Si.sub.xGe.sub.1-x nanowires; forming III-V or III-V.sub.xM.sub.y nanowires in the second group of trenches; removing the second mask; and planarizing the Si, Ge, or Si.sub.xGe.sub.1-x and III-V or III-V.sub.xM.sub.y nanowires down to the SiOC layer.

2. The method according to claim 1, comprising forming the substrate stack by: forming a Si substrate; forming a buffer oxide layer over the Si substrate; forming the a-Si or doped poly-Si layer over the oxide layer; forming a first silicon nitride (SiN) layer over the a-Si or doped poly-Si layer; forming the SiOC layer over the first SiN layer; and forming a second SiN layer over the SiOC layer.

3. The method according to claim 1, comprising forming the trenches within the substrate stack by: self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), direct surface assembly (nanoimprint), or extreme ultraviolet (EUV) lithography.

4. The method according to claim 1, comprising forming the Si, Ge, or Si.sub.xGe.sub.1-x nanowires by: depositing a nickel (Ni) or gold (Au) nanoparticle in each of the first group of trenches by self-assembly in sol-gel or by metal organic chemical vapor deposition (MOCVD) or atomic layer growth (ALD); and growing the Si, Ge, or Si.sub.xGe.sub.1-x nanowires to a desired height.

5. The method according to claim 4, comprising pre-cleaning the first group of trenches prior to depositing the Ni or Au nanoparticle.

6. The method according to claim 1, comprising forming the III-V or III-V.sub.xM.sub.y nanowires by: depositing an aluminum (Al), Ni, or gallium (Ga) nanoparticle in each of the second group of trenches by self-assembly in sol-gel or by MOCVD, ALD; growing the III-V or III-V.sub.xM.sub.y nanowires to a desired height by a metal catalyst vertical vapor liquid solid (VLS) growth or chemical vapor deposition (CVD) growth with in-situ doping during growth; and removing the second mask prior to planarizing the Si, Ge, or Si.sub.xGe.sub.1-x and III-V or III-V.sub.xM.sub.y nanowires.

7. The method according to claim 6, comprising pre-cleaning the second group of trenches prior to depositing the Al, Ni, or Ga nanoparticle.

8. The method according to claim 6, comprising planarizing the Si, Ge, or Si.sub.xGe.sub.1-x and III-V or III-V.sub.xM.sub.y nanowires by chemical mechanical planarization (CMP).

9. The method according to claim 1, comprising forming the III-V or III-V.sub.xM.sub.y nanowires of a combination of indium phosphide (InP), indium arsenide (InAs), gallium nitride (GaN), or gallium arsenide (GaAs).

10. The method according to claim 1, wherein the metal catalyst comprises Ni, Al, Au, silver (Ag), titanium (Ti), erbium (Er), platinum (Pt), palladium (Pd), indium (In), Tin (Sn), antimony (Sb), Zirconium (Zr), vanadium (V), hafnium (Hf), tungsten (W), cobalt (Co), tantalum (Ta), lanthanum (La), ruthenium (Ru), molybdenum (Mo), Ga, or iron (Fe).

11. A device comprising: a substrate; a first group of silicon (Si) or germanium (Ge)-based vertically integrated nanowires formed on the substrate; and a second group of III-V-based vertically integrated nanowires formed on the substrate, separated from the first group, the first and second groups of vertically integrated nanowires being formed of heterogeneous materials.

12. The device according to claim 11, wherein the substrate comprises Si, silicon germanium (SiGe), III-V, a combination thereof, or a substrate stack.

13. The device according to claim 12, wherein the substrate stack comprises sequential layers of silicon, oxide, amorphous silicon (a-Si)/doped poly-Si, silicon nitride (SiN), silicon oxycarbide (SiOC), and SiO.sub.xC.sub.yN.sub.z.

14. The device according to claim 11, wherein the first group of Si or Ge-based vertically integrated nanowires comprises Si, Ge or silicon germanium (Si.sub.xGe.sub.1-x).

15. The device according to claim 11, wherein the second group of III-V-based vertically integrated nanowires comprises III-V or III-V.sub.xM.sub.y nanowires.

16. The device according to claim 11, wherein the III-V or III-V.sub.xM.sub.y nanowires comprises a combination of indium phosphide (InP), indium arsenide (InAs), gallium nitride (GaN), or gallium arsenide (GaAs).

17. A method comprising: forming a substrate stack including an amorphous silicon (a-Si) followed by n or p doping or doped polysilicon (poly-Si) layer and a silicon oxycarbide (SiOC) layer; forming first and second groups of trenches by self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), direct surface assembly (nanoimprint), or extreme ultraviolet (EUV) lithography in the substrate stack down to the doped a-Si/poly-Si layer of the substrate stack; forming a first mask over the second group of trenches; forming silicon (Si), germanium (Ge) or silicon germanium (Si.sub.xGe.sub.1-x) nanowires in the first group of trenches by VLS or chemical vapor deposition (CVD) process with in-situ doping; removing the first mask and forming a second mask over the Si, Ge, or Si.sub.xGe.sub.1-x nanowires; forming III-V or III-V.sub.xM.sub.y nanowires of a combination of indium phosphide (InP), indium arsenide (InAs), gallium nitride (GaN), or gallium arsenide (GaAs) in the second group of trenches by a metal catalyst VLS or CVD growth with in-situ doping; removing the second mask; and planarizing the Si, Ge, or Si.sub.xGe.sub.1-x and III-V or III-V.sub.xM.sub.y nanowires down to the SiOC layer by chemical mechanical planarization (CMP).

18. The method according to claim 17, comprising forming the substrate stack by: forming a Si substrate; forming a buffer oxide layer over the Si substrate; forming the a-Si or doped poly-Si layer over the oxide layer; forming a first silicon nitride (SiN) layer over the a-Si or doped poly-Si layer; forming the SiOC layer over the first SiN layer; and forming a second SiN layer over the SiOC layer.

19. The method according to claim 17, comprising forming the Si, Ge, or Si.sub.xGe.sub.1-x nanowires by: pre-cleaning the first group of trenches; depositing a nickel (Ni) or gold (Au) nanoparticle in each of the first group of trenches by self-assembly in sol-gel or by metal organic chemical vapor deposition (MOCVD) or atomic layer growth (ALD); and growing the Si, Ge, or Si.sub.xGe.sub.1-x nanowires to a desired height.

20. The method according to claim 17, comprising forming the III-V or III-V.sub.xM.sub.y nanowires by: pre-cleaning the second group of trenches; depositing an aluminum (Al), Ni, or gallium (Ga) nanoparticle in each of the second group of trenches by self-assembly in sol-gel or by MOCVD, ALD; growing the III-V or III-V.sub.xM.sub.y nanowires to a desired height by a metal catalyst vertical vapor liquid solid (VLS) growth or chemical vapor deposition (CVD) growth with in-situ doping during growth; and removing the second mask prior to planarizing the Si, Ge, or Si.sub.xGe.sub.1-x and III-V or III-V.sub.xM.sub.y nanowires.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:

[0017] FIGS. 1 through 14 schematically illustrate a process flow for forming Si or Ge-based and III-V-based vertically integrated nanowires on a single substrate for mixed signal circuits, in accordance with an exemplary embodiment; and

[0018] FIGS. 15 through 22 schematically illustrate another process flow for forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate for mixed signal circuits, in accordance with an exemplary embodiment.

DETAILED DESCRIPTION

[0019] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”

[0020] The present disclosure addresses and solves the current problems of having different (i) substrate, (ii) voltage, (iii) frequency, and (iv) fabrication requirements for digital and analog chips and resulting increased chip real estate demands and fabrication complexity attendant upon fabricating traditional CMOS devices.

[0021] Methodology in accordance with embodiments of the present disclosure includes forming first trenches in a Si, Ge, III-V, or Si.sub.xGe.sub.1-x substrate. A conformal SiN, SiO.sub.xC.sub.yN.sub.z, or DPN layer is formed over side and bottom surfaces of the first trenches. The first trenches are filled with SiO.sub.x, and a first mask is formed over portions of the Si, Ge, III-V, or Si.sub.xGe.sub.1-x substrate. Exposed portions of the Si, Ge, III-V, or Si.sub.xGe.sub.1-x substrate are removed, forming second trenches. III-V, III-V.sub.xM.sub.y, or Si nanowires are then formed in the second trenches. The first mask is removed, and a second mask is formed over the III-V, III-V.sub.xM.sub.y, or Si nanowires and intervening first trenches. The SiO.sub.x layer is removed, forming third trenches, and the second mask is removed.

[0022] Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

[0023] FIGS. 1 through 14 schematically illustrate a process flow for forming Si or Ge-based and III-V-based vertically integrated nanowires on a single substrate for mixed signal circuits, in accordance with an exemplary embodiment. FIGS. 1, 2, 4 through 12, and 14 are cross-sectional views, and FIGS. 3 and 13 are top views. Adverting to FIG. 1, a SiN layer 101 is deposited, e.g., to a thickness of 2 nm to 30 nm, over a Si, Ge, or Si.sub.xGe.sub.1-x substrate 103. The upper 50 nm to 500 nm of the Si, Ge, or Si.sub.xGe.sub.1-x substrate 103 may be doped n+ or p+ prior to forming the SiN layer 101. The Si, Ge, or Si.sub.xGe.sub.1-x substrate 103 may be doped, e.g., to form a conducting region for later contact formation for source-drain definitions. Next, a SiO.sub.2 layer 105 is deposited, e.g., to a thickness of 100 nm to 300 nm, over the SiN layer 101. The SiN and SiO.sub.2 layers 101 and 105, respectively, are then patterned, e.g., by reactive ion etching (RIE), as depicted in FIGS. 2 and 3.

[0024] Adverting to FIG. 4, the Si, Ge, or Si.sub.xGe.sub.1-x substrate 103 is etched, e.g., to a depth of 10 nm to 50 nm, forming trenches 401. The Si, Ge, or Si.sub.xGe.sub.1-x substrate 103 may be etched, e.g., with plasma based species including, but not limited to, bromine trifluoride (BrF.sub.3), chlorine trifluoride (ClF.sub.3), tetrafluoromethane (CF.sub.4), or fluoroform (CHF.sub.3), hydrogen fluoride (HF), boron trichloride (BCl.sub.3), boron trifluoride (BF.sub.3), and sulphur hexafluoride (SF.sub.6). The SiN and SiO.sub.2 layers 101 and 105, respectively, are then removed, as depicted in FIG. 5. Adverting to FIG. 6, a conformal SiN, SiO.sub.xC.sub.yN.sub.z, or DPN layer 601 is then deposited on the side and bottom surfaces of the trenches 401, e.g., to a thickness of 1 nm to 10 nm, and the remainder of the trenches 401 is filled with a SiO.sub.x layer 603. The SiO.sub.x layer 603 is then planarized, e.g., by CMP, down to the Si, Ge, or Si.sub.xGe.sub.1-x substrate 103, thereby defining the Si, Ge, or Si.sub.xGe.sub.1-x nanowires 103′. Alternatively, the SiN, SiO.sub.xC.sub.yN.sub.z, or DPN layer 601 and SiO.sub.x layer 603 may be deposited without first removing the SiN and SiO.sub.2 layers 101 and 105, respectively. Thereafter, all of the layers 601, 603, 101, and 105 may be planarized, e.g., by CMP, down to the Si, Ge, or Si.sub.xGe.sub.1-x substrate 103, thereby defining the Si, Ge, or Si.sub.xGe.sub.1-x nanowires 103′.

[0025] A photoresist and hardmask layer 701, e.g., titanium oxide (TiO.sub.2), titanium nitride (TiN), amorphous carbon (a-C), SOH, SOC, SiO.sub.2, or SiN, is formed over the Si, Ge, III-V, or Si.sub.xGe.sub.1-x nanowires 103′ with an opening to define III-V growth regions, as depicted in FIG. 7. Portions of the Si, Ge, or Si.sub.xGe.sub.1-x nanowires 103′ are then etched back to form trenches 801, as depicted in FIG. 8. Adverting to FIG. 9, the trenches 801 may be pre-cleaned (not shown for illustrative purposes), and a metal nanoparticle 901, e.g., Al, Ni, Ga, is deposited in each trench 801 by self-assembly in sol-gel or by direct deposit. Pre-cleaning the trenches 801 helps the nanoparticle 901 to stick to the Si, Ge, or Si.sub.xGe.sub.1-x substrate 103 in the trenches 801. The type of metal nanoparticles 901 deposited in the trenches 801 also depends on the type of doping of the Si, Ge, or Si.sub.xGe.sub.1-x substrate 103, e.g., Al or Ga may be deposited for p+ doping and antimony (Sb) or Ti may be deposited for n+ doping. Alternatively, in-situ doping of arsenic (As), phosphorous (P) (for n+), boron (B), nitrogen (N), Ga (for p+) can be done during the CVD or VLS growth of the nanowires.

[0026] Adverting to FIG. 10, the photoresist of the photoresist and hardmask layer 701 is removed, leaving just the hardmask 701′, and III-V or III-V.sub.xM.sub.y nanowires 1001 are grown to a desired height in the trenches 801, e.g., by a metal catalyst VLS growth or CVD. Ni, Al, Au, Ag, Ti, Er, Pt, Pd, In, Sn, Sb, Zr, V, Hf, W, Co, Ta, La, Ga, Ru, Mo, or Fe may be used as the metal catalyst depending on the type of doping performed on the Si, Ge, or Si.sub.xGe.sub.1-x substrate 103. Alternatively, the self-assembly of the III-V or III-V.sub.xM.sub.y nanowires 1001 could be achieved through plasma treatment of the exposed surfaces of trenches 801, wet chemistry treatment, or thiol molecule chemistry with axial and radial doping possible. The III-V or III-V.sub.xM.sub.y nanowires 1001 may also completely fill the trenches 801 (not shown for illustrative purposes). The remainder of masking layer 701 and metal nanoparticles 901 are then removed. Next, DPN or direct plasma oxidation (DPO) (not shown for illustrative convenience) is performed to passivate the nanowire surfaces and help with gap-fill. Thereafter, a protective layer 1101, e.g., formed of oxide/SOH, is deposited between each III-V or III-V.sub.xM.sub.y nanowire 1001 and the sidewalls of the corresponding trench 801. The protective layer 1101 is then planarized, e.g., by CMP, as depicted in FIG. 11.

[0027] Next, a photoresist and hardmask layer 1201 is formed over each III-V or III-V.sub.xM.sub.y nanowire 1001 to enable the Si, Ge, or Si.sub.xGe.sub.1-x nanowire 103′ regions to be opened, as depicted in FIG. 12. Adverting to FIG. 13, the photoresist and hardmask layer 1201 is then removed resulting in integrated Si, Ge, or Si.sub.xGe.sub.1-x nanowires 103′ and III-V or III-V.sub.xM.sub.y nanowires 1001 on a single substrate.

[0028] Alternatively, the substrate 103 may be formed of III-V material, in which case the planarization of the SiO.sub.x layer 603 and/or all of the layers 601, 603, 101, and 105 in FIG. 6 would define the III-V nanowires 103′. Further, the opening shown in FIG. 7 would define Si growth regions, and when the photoresist of the photoresist and hardmask layer 701 is removed in FIG. 10, leaving just the hardmask 701′, Si nanowires 1001 would be grown to a desired height in the trenches 801, e.g., by depositing a Ni or Au nanoparticle in each trench 801 by self-assembly in sol-gel, MOCVD, or ALD. Then, the removal of the photoresist and hardmask 1201 in FIG. 13 would result in integrated III-V nanowires 103′ and Si nanowires 1001 on a single substrate.

[0029] Adverting to FIG. 14, the SiO.sub.x layer 603 is removed forming trenches 1401, which can be subsequently used to perform source/drain and gate formation steps. The SiN, SiO.sub.xC.sub.yN.sub.z, or DPN layer 601 may also be removed (not shown for illustrative convenience). Further, shallow trench isolation regions (not shown for illustrative convenience) may also be formed between the Si, Ge, or Si.sub.xGe.sub.1-x nanowires 103′ and the III-V or III-V.sub.xM.sub.y nanowires 1001 or between the III-V nanowires 103′ and the Si nanowires 1001 depending on the substrate material.

[0030] FIGS. 15 through 22 (cross-sectional views) schematically illustrate another process flow for forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate for mixed signal circuits, in accordance with an exemplary embodiment. Adverting to FIG. 15, a substrate stack 1501 is sequentially formed with a Si substrate 1503, a buffered silicon oxide layer 1505, an a-Si or doped poly-Si layer 1507, a SiN layer 1509, a SiOC layer 1511, and a SiN layer 1513. The particular material composition of the substrate stack 1501 may be determined to achieve optimum RIE and wet etch selectivities, e.g., for fabricating gate contacts at a later time. Further, the single substrate may alternatively be formed of Si, SiGe, III-V, or a combination thereof.

[0031] Adverting to FIG. 16, trenches 1601 and 1603 are formed in the substrate stack 1501 down to the a-Si/poly-Si layer 1507 to define the areas for subsequent nanowire growth. A mask 1701 is then formed over the trenches 1603, as depicted in FIG. 17. Next, metal nanoparticles 1703, e.g., Ni or Au, are deposited, e.g., by self-assembly in sol-gel or MOCVD, in the trenches 1601. As described in FIG. 9, the trenches 1603 may be pre-cleaned (not shown for illustrative convenience) to help the nanoparticles 1703 to stick to the a-Si layer 1507. Si, Ge, or Si.sub.xGe.sub.1-x nanowires 1801 are then grown by a VLS or CVD process with in-situ doping to the desired height and the mask 1701 is removed, as depicted in FIG. 18.

[0032] Next, a mask 1901 is formed over the Si, Ge, or Si.sub.xGe.sub.1-x nanowires 1801, and metal nanoparticles 1903, e.g., Al, Ni, or Ga, are deposited, e.g., by self-assembly in sol-gel or by MOCVD, in the trenches 1603, as depicted in FIG. 19. Again, the trenches 1603 may be pre-cleaned before the metal nanoparticles 1903 are deposited. Thereafter, III-V or III-V.sub.xM.sub.y nanowires 2001, e.g., formed of InP or GaAs, are grown to a desired height by a metal catalyst VLS or CVD growth with in-situ doping. Again, Ni, Al, Au, Ag, Ti, Er, Pt, Pd, In, Sn, Sb, Zr, V, Hf, W, Co, Ta, La, Ga, or Fe may be used as the metal catalyst. Alternatively, the self-assembly of the III-V or III-V.sub.xM.sub.y nanowires 1903 could be achieved through plasma treatment of the exposed surfaces of trenches 1603, wet chemistry treatment, or thiol molecule chemistry with axial and radial doping possible. The mask 1901 is then removed, as depicted in FIG. 21. Adverting to FIG. 22, the nanoparticles 1703 and 1903 are removed, and the Si, Ge, or Si.sub.xGe.sub.1-x nanowires 1801 and III-V or III-V.sub.xM.sub.y nanowires 2001 are planarized, e.g., by CMP, down to the SiOC layer 1511, forming Si, Ge, or Si.sub.xGe.sub.1-x nanowires 1801′ and III-V or III-V.sub.xM.sub.y nanowires 2001′. Thereafter, source/drain and gate formation steps may be performed.

[0033] The embodiments of the present disclosure can achieve several technical effects including heterogeneous integration of Si or Ge-based and III-V-based channels for vertical FETs on a single substrate enabling, both digital and analog logic to be integrated on a single chip. Integration of self-assembled VLS or CVD growth of nanowires using a metal catalyst with different precursors can also enable the formation of self-aligned vertical nanowires that enable low voltage/power with multiple scaling options and substantial transistor packing density relative to known fin field effect transistor (FinFET) structures. Embodiments of the present disclosure enjoy utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure therefore enjoys industrial applicability with respect to FET structures with vertical nanowire channels.

[0034] In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.