III-V SEMICONDUCTOR DEVICES WITH SELECTIVE OXIDATION

Abstract

Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer.

Claims

1. (canceled)

2. A method of fabricating a semiconductor device, the method comprising: providing a stack of two layers disposed on a base layer, wherein a first layer of the two layers is an oxidized layer; forming a dummy gate; forming source and drain regions in contact with sides of the two layers; removing the dummy gate to provide a gate opening; etching the first layer through the gate opening to provide a lower gate region; and forming a replacement gate between a plurality of walls, the replacement gate comprising an upper gate portion having a first width and a lower gate portion having a second width, wherein the lower gate portion is located in the lower gate region below the upper gate portion, and wherein the second width is greater than the first width.

3. The method of claim 2, wherein providing the stack of two layers disposed on the base layer comprises: depositing two crystalline semiconductor layers on the base layer; and selectively oxidizing one of the two crystalline semiconductor layers to provide the first layer.

4. The method of claim 3, wherein selectively oxidizing the one of the two crystalline semiconductor layers comprises: exposing the semiconductor substrate in water vapor at a temperature in a range of approximately 350 degrees to approximately 550 degrees Celsius.

5. The method of claim 3, wherein the two crystalline semiconductor layers comprise a semiconducting material selected from a group consisting of indium gallium arsenide (InGaAs) and gallium arsenide (GaAs).

6. The method of claim 3, further comprising: performing shallow trench isolation within the base layer to form a plurality of trenches exposing the first layer and a second layer; and depositing an insulator into the plurality of trenches.

7. The method of claim 2, further comprising: depositing a high-K insulator around at least part of the replacement gate.

8. The method of claim 2, wherein the base layer comprises germanium (Ge).

9. The method of claim 8, wherein the Ge has a thickness in a range of approximately 100 nanometers to approximately 1 micrometer.

10. A method of fabricating a semiconductor device, the method comprising: disposing a stack of two crystalline semiconductor layers on a base layer; selectively oxidizing a first of the two crystalline semiconductor layers to provide a first layer; removing a dummy gate structure to provide a gate opening; etching the first layer through the gate opening to provide a lower gate region; and forming a replacement gate between a plurality of walls, the replacement gate comprising an upper gate portion having a first width and a lower gate portion having a second width, wherein the lower gate portion is located in the lower gate region, and wherein the second width is greater than the first width.

11. The method of claim 10, further comprising: forming source and drain regions in contact with the first layer and a second layer of the two crystalline semiconductor layers.

12. The method of claim 10, wherein selectively oxidizing the first of the two crystalline semiconductor layers comprises: exposing the semiconductor substrate in water vapor at a temperature in range of approximately 350 degrees to approximately 550 degrees Celsius.

13. The method of claim 10, wherein the stack of two crystalline semiconductor layers comprises a semiconducting material selected from a group consisting of indium gallium arsenide (InGaAs) and gallium arsenide (GaAs).

14. The method of claim 10, further comprising: performing shallow trench isolation within the base layer to form a plurality of trenches exposing the first layer and a second layer of the two crystalline semiconductor layers; and depositing an insulator into the plurality of trenches of the base layer.

15. The method of claim 10, further comprising: depositing a high-K insulator around at least part of the replacement gate.

16. The method of claim 10, wherein the base layer comprises germanium (Ge).

17. The method of claim 16, wherein the Ge has a thickness in a range of approximately 100 nanometers to approximately 1 micrometer.

18. A method of fabricating a semiconductor device, the method comprising: providing a stack of two layers disposed on a base layer, wherein a first layer of the two layers is an oxidized layer; forming source and drain regions in contact with sides of the two layers; removing a dummy gate to provide a gate opening; etching the first layer through the gate opening to provide a lower gate region; and forming a replacement gate between a plurality of walls, the replacement gate comprising an upper gate portion having a first width and a lower gate portion having a second width, wherein the lower gate portion is located in the lower gate region, and wherein the second width is greater than the first width.

19. The method of claim 18, wherein providing the stack of two layers disposed on the base layer comprises: depositing two crystalline semiconductor layers on the base layer; and selectively oxidizing one of the two crystalline semiconductor layers to provide the first layer.

20. The method of claim 19, further comprising: performing shallow trench isolation within the base layer to form a plurality of trenches exposing the first layer and a second layer of the two crystalline semiconductor layers; and depositing an insulator into the plurality of trenches of the base layer.

21. The method of claim 20, further comprising: depositing a high-K insulator around at least part of the replacement gate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIGS. 1A and 1B depict a plan view and a cross-sectional view of a starting semiconductor substrate on which a III-V device with selective oxidation may be formed, in accordance with an embodiment of the present invention;

[0010] FIGS. 2A-C depict a plan view and cross-sectional views of an embodiment where device regions are created on the starting substrate of FIGS. 1A and 1B through shallow trench isolation, in accordance with an embodiment of the present invention;

[0011] FIGS. 3A-C depict a plan view and cross-sectional views of the selective oxidation of one of the starting semiconductor substrate layers, in accordance with an embodiment of the present invention;

[0012] FIGS. 4A-C depict a plan view and cross-sectional views of the formation of dummy gates in the device regions created in FIGS. 2A-C, in accordance with an embodiment of the present invention;

[0013] FIGS. 5A-D depict a plan view and cross-sectional views of the formation of source and drain regions on either side of the dummy gates of FIGS. 4A-C, in accordance with an embodiment of the present invention;

[0014] FIGS. 6A-D depict a plan view and cross-sectional views of the deposition of an insulator layer over the device regions of FIGS. 2A-C, covering the source and drain regions of FIGS. 5A-D, and the subsequent planarization of the insulator layer to expose the tops of the dummy gates created in FIGS. 4A-C, in accordance with an embodiment of the present invention;

[0015] FIGS. 7A-D depict a plan view and cross-sectional views of the removal of the dummy gates created in FIGS. 4A-C, in accordance with an embodiment of the present invention;

[0016] FIGS. 8A-D depict a plan view and cross-sectional views of the release of the selectively oxidized layer created in FIGS. 3A-C, in accordance with an embodiment of the present invention; and

[0017] FIGS. 9A-D depict a plan view and cross-sectional views of depositing a high-K dielectric and forming replacement gates between sets of sidewall spacers, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION

[0018] The formation of nanowires on a Si substrate may be difficult when crystalline semiconductors are stacked on an insulator. Embodiments of the present invention provide a fabrication process for a III-V semiconductor device with crystalline starting layers which are subsequently selectively oxidized to become an insulator. Growing the starting layer as a semiconductor layer is less effective than growing a single crystal insulator starting layer. Detailed description of embodiments of the claimed structures and methods are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments is intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present disclosure.

[0019] References in the specification to one embodiment, an embodiment, an example embodiment, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0020] For purposes of the description hereinafter, the terms upper, lower, right, left, vertical, horizontal, top, bottom, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. The terms on, over, overlying, atop, positioned on, or positioned atop mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure, may be present between the first element and the second element. The terms direct contact, directly on, or directly over mean that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating, or semiconductor layers at the interface of the two elements. The terms connected or coupled mean that one element is directly connected or coupled to another element, or intervening elements may be present. The terms directly connected or directly coupled mean that one element is connected or coupled to another element without any intermediary elements present.

[0021] Referring now to the figures, FIG. 1A is a plan view of a starting substrate on which III-V devices with selective oxidation may be formed, and FIG. 1B is a cross-sectional view of FIG. 1A, taken along the line 1B-1B. The starting substrate includes base layer(s) 102, and may be composed of any crystalline material(s) known in the art. In this exemplary embodiment, base layer(s) 102 includes a layer of Ge, which is approximately from 100 nm to 1 micrometer in thickness, on top of an insulator. A stack of two crystalline semiconductor layers, layer 104 and layer 106 are grown on the top surface of base layer(s) 102. In this exemplary embodiment, layer 104 is a single crystal semiconductor material composed of AlAs, and is approximately 10 nm in thickness. In other embodiments, layer 104 may be composed of any semiconductor material capable of being oxidized to a mechanically stable insulator. Layer 106 is a single crystal semiconductor layer, and may be composed of InGaAs, GaAs, III-V materials, or any other semiconducting material. In this exemplary embodiment, layer 106 is composed of InGaAs and is approximately 10 nm in thickness. As depicted in FIG. 1B, there are two stacks (i.e., grouping of one layer 104 and one layer 106) formed on the top surface of base layer(s) 102. In other embodiments, more than two stacks or a single stack may be formed on the top surface of base layer(s) 102.

[0022] Referring now to FIGS. 2A-C, FIG. 2A is a plan view of the processing step of fin regions patterned on the starting substrate of FIGS. 1A and 1B, FIG. 2B is a cross-sectional view of FIG. 2A, taken along the line 2B-2B, and FIG. 2C is a cross-sectional view of FIG. 2A, taken along the line 2C-2C. The fins are formed using a standard etch process. Subsequent to the formation of the fins, device regions are created through shallow trench isolation (STI) within the starting substrate. In a preferred embodiment, the shallow trenches are filled with one or more insulating materials 108, such as SiO.sub.2, to isolate the fins from each other. This prevents electrical current leakage between adjacent semiconductor device components, preventing one device region from affecting another or shorting out through contact with another.

[0023] Referring now to FIGS. 3A-3C, FIG. 3A is a plan view of the processing step of selective oxidation of layer 104 of the starting substrate, FIG. 3B is a cross-sectional view of FIG. 3A, taken along the line 3B-3B, and FIG. 3C is a cross-sectional view of FIG. 3A, taken along the line 3C-3C. The starting substrate is exposed at a temperature between 350 C. to 550 C. in water vapor, to selectively oxidize layer 104 (AlAs in this embodiment) to become oxidized layer 110. The composition of layer 104 is initially chosen to be more readily oxidized than layer 106, and also as a close lattice match to layer 106. Oxidized layer 110 acts as an insulating layer within the stacked crystalline structure. In this exemplary embodiment, oxidized layer 110 is composed of Al.sub.2O.sub.3.

[0024] Referring now to FIGS. 4A-4C, FIG. 4A is a plan view of the processing step of dummy gates 112 and sidewall spacers 113 in the fin regions on the starting substrate, FIG. 4B is a cross-sectional view of FIG. 4A, taken along the line 4B-4B, and FIG. 4C is a cross-sectional view of FIG. 4A, taken along the line 4C-4C. Dummy gates 112 (i.e., sacrificial gate structures) are formed and, after formation of source and drain regions 116 (depicted in FIGS. 5A-D), may be selectively etched and replaced. One exemplary process for forming dummy gates 112 comprises depositing a dielectric layer over the starting substrate and a polysilicon layer over the dielectric layer. A lithography/gate etch process removes unnecessary portions of the stacked layers to leave dummy gates 112, comprised of a gate oxide (not pictured) and polysilicon layer 114. Ultimately, dummy gates 112 may be comprised of any material that can be etched selectively to the underlying upper semiconductor layer. A set of sidewall spacers 113 are formed adjacent to dummy gates 112, i.e., in direct contact with the sidewall of dummy gate 112. A sidewall spacer typically has a width ranging from 2 nm to 15 nm, as measured from the sidewall of a gate structure. Sidewall spacers 113 may be composed of a dielectric, such as a nitride, oxide, oxynitride, or a combination thereof. In one embodiment, sidewall spacers 113 are composed of silicon nitride (Si.sub.3N.sub.x). Those skilled in the art will recognize that a set of sidewall spacers 113 may actually comprise a single spacer formed around the entire gate.

[0025] Referring now to FIGS. 5A-D, FIG. 5A is a plan view of the processing step of source and drain regions 116 formation, FIG. 5B is a cross-sectional view of FIG. 5A, taken along the line 5B-5B, FIG. 5C is a cross-sectional view of FIG. 5A, taken along the line 5C-5C, and FIG. 5D is a cross-sectional view of FIG. 5A, taken along the line 5D-5D. Source and drain regions 116 formation includes a number of high-temperature steps (e.g., implants and anneals). In this exemplary embodiment, source and drain regions 116 are formed using epitaxy. In another embodiment, source and drain regions 116 are formed using an ion implantation process.

[0026] Referring now to FIGS. 6A-6D, FIG. 6A is a plan view of the processing step of depositing insulator 118, FIG. 6B is a cross-sectional view of FIG. 6A, taken along the line 6B-6B, FIG. 6C is a cross-sectional view of FIG. 6A, taken along the line 6C-6C, and FIG. 6D is a cross-sectional view of FIG. 6A, taken along the line 6D-6D. Insulator 118 is planarized using a standard planarization method in the art, and may be deposited using, for example, chemical vapor deposition (CVD). Variations of CVD processes may also be used, including, but not limited to, atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), and plasma enhanced CVD (PECVD). Other deposition techniques may also be used. Following deposition of insulator 118, insulator 118 is planarized until the upper surfaces of dummy gates 112 are exposed. Planarization is a material removal process that employs at least mechanical forces, such as frictional media, to produce a planar surface. In one embodiment, the planarization process includes chemical mechanical polishing (CMP) or grinding. CMP is a material removal process which uses both chemical reactions and mechanical forces to remove material and planarize a surface. The preferred method for exposing polysilicon layer 114 is known as poly open planarization (POP) chemical mechanical planarization (CMP), or poly open CMP.

[0027] Referring now to FIGS. 7A-7D, FIG. 7A is a plan view of the processing step of the removal of dummy gates 112, FIG. 7B is a cross-sectional view of FIG. 7A, taken along the line 7B-7B, FIG. 7C is a cross-sectional view of FIG. 7A, taken along the line 7C-7C, and FIG. 7D is a cross-sectional view of FIG. 7A, taken along the line 7D-7D. Once the gate stack is exposed, dummy gates 112 are removed through a selective etch process, selective to the substrate/channel material and sidewall spacers 113. In this exemplary embodiment, a first etch removes polysilicon layer 114 and is selective to sidewall spacers 113. The etchant may be an isotropic etch or an anisotropic etch. One example of an isotropic etch is a wet chemical etch. The anisotropic etch may include reactive-ion etching (RIE). Other examples of anisotropic etching that can be used during this process include ion beam etching, plasma etching, or laser ablation.

[0028] Referring now to FIGS. 8A-8D, FIG. 8A is a plan view of the processing step of the release of layer 110 (Al.sub.2O.sub.3), FIG. 8B is a cross-sectional view of FIG. 8A, taken along the line 8B-8B, FIG. 8C is a cross-sectional view of FIG. 8A, taken along the line 8C-8C, and FIG. 8D is a cross-sectional view of FIG. 8A, taken along the line 8D-8D. In this exemplary embodiment, an etching process known in the art, use of dilute HF, is used to etch layer 110, in order to release layer 110 selective to sidewall spacers 113, channel layer 106, and dielectric insulator 118.

[0029] Referring now to FIGS. 9A-D, FIG. 9A is a plan view of the processing step of the deposition of high-K material 126 and formation of replacement gates 124, FIG. 9B is a cross-sectional view of FIG. 9A, taken along the line 9B-9B, FIG. 9C is a cross-sectional view of FIG. 9A, taken along the line 9C-9C, and FIG. 9D is a cross-sectional view of FIG. 9A, taken along the line 9D-9D. High-K material 126 may be composed of, for example, HfO, ZrO, or TiO. Replacement gates 124 are formed between the existing sidewall spacers 113, and may be composed of any metal, for example, W or Cu. High-K material 126 is deposited around the formed replacement gates 124. Standard middle of the line and back end of the line (BEOL) processes known in the art may be performed to complete the semiconductor chip (not depicted).

[0030] Having described the preferred embodiments of a method for selectively oxidizing layers within a III-V semiconductor device (which are intended to be illustrative and not limiting), it is noted that modifications and variations may be made by persons skilled in the art in light of the above teachings. It is, therefore, to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention, as outlined by the appended claims.

[0031] In certain embodiments, the fabrication steps depicted above may be included on a semiconductor substrate consisting of many devices and one or more wiring levels to form an integrated circuit chip. The resulting integrated circuit chip(s) can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications, to advanced computer products having a display, a keyboard or other input device, and a central processor.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms a, an and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises and/or comprising, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.