PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT COMPRISING A PHASE OF FORMING TRENCHES IN A SUBSTRATE AND CORRESPONDING INTEGRATED CIRCUIT

Abstract

Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.

Claims

1. An integrated circuit, comprising: a semiconductor substrate having a front face, a first zone and a second zone; wherein the first zone of the semiconductor substrate includes a vertical gate of a buried transistor formed in a first trench extending vertically into the semiconductor substrate down to a first depth relative to the front face; and wherein the second zone of the semiconductor substrate includes a vertical electrode of a capacitive element formed in a second trench extending vertically into the semiconductor substrate down to a second depth relative to the front face; wherein the second depth is shallower than the first depth.

2. The integrated circuit according to claim 1, further including a transition trench delimiting the first zone on one side of the transition trench and the second zone on another side of the transition trench, wherein a bottom of the transition trench is asymmetric relative to a median plane of the transition trench and located between said one side and said another side.

3. The integrated circuit according to claim 1, wherein the first zone includes a non-volatile memory and the second zone includes a logic portion.

4. The integrated circuit according to claim 1, wherein the first zone includes a non-volatile memory and the second zone includes a non-volatile memory.

5. An integrated circuit, comprising: a semiconductor substrate having a front face; wherein a first zone of the semiconductor substrate includes at least one first element formed in a first trench extending vertically into the substrate down to a first depth relative to the front face; and wherein a second zone of the semiconductor substrate includes at least one second element formed in a second trench extending vertically into the substrate down to a second depth relative to the front face, the second depth being shallower than the first depth.

6. The integrated circuit according to claim 5, further including a transition trench delimiting the first zone on one side of the transition trench and delimiting the second zone on the other side of the transition trench, wherein a bottom of the transition trench is asymmetric relative to a median plane of the transition trench and located between said one side and said other side.

7. The integrated circuit according to claim 6, wherein said at least one first element comprises a vertical gate of a buried transistor and said at least one second element comprises a vertical electrode of a capacitive element.

8. The integrated circuit according to claim 5, wherein said at least one first element comprises a shallow trench isolation and said at least one second element comprises a shallow trench isolation.

9. The integrated circuit according to claim 5, wherein the first zone includes a non-volatile memory and the second zone includes a logic circuit.

10. The integrated circuit according to claim 5, wherein said at least one first element comprises a vertical gate of a buried transistor and said at least one second element comprises a vertical electrode of a capacitive element.

11. The integrated circuit according to claim 5, wherein the first zone includes a capacitive element and the second zone includes a non-volatile memory.

12. An integrated circuit, comprising: a semiconductor substrate having a front face; wherein a first zone of the semiconductor substrate comprises at least one first element formed in a first trench extending vertically into the semiconductor substrate at a first depth relative to the front face; wherein a second zone of the semiconductor substrate comprises at least one second element formed in a second trench extending vertically into the semiconductor substrate at a second depth from the front face; wherein the second depth is less than the first depth; and a transition trench delimiting the first zone on one side of the transition trench and delimiting the second zone on another side of the transition trench; wherein a bottom of the transition trench is asymmetrical with respect to a median plane of the transition trench and located between said one side and said another side.

13. The integrated circuit according to claim 12, wherein said at least one first element comprises a vertical gate of a buried transistor, and said at least one second element comprises a vertical electrode of a capacitive element.

14. The integrated circuit according to claim 12, wherein the first zone comprises a capacitive element, and the second zone comprises a non-volatile memory.

15. The integrated circuit according to claim 12, wherein the first zone comprises a non-volatile memory and the second zone comprises a logic circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Other advantages and features of the invention will become apparent on examining the detailed description of completely non-limiting embodiments and implementations, and the appended drawings, in which:

[0043] FIGS. 1-12 illustrate results of steps in implementations of a fabrication process.

DETAILED DESCRIPTION

[0044] FIG. 1 illustrates the result of a step in a phase of forming trenches in a semiconductor substrate 10 in a process for fabricating an integrated circuit.

[0045] The semiconductor substrate 10 is, for example, formed of silicon and comprises a first zone Z1 and a second zone Z2.

[0046] According to a first variant, the first zone Z1 may be intended to include a non-volatile memory region and the second zone Z2 may be intended to include a logic portion, for example both incorporated within a microcontroller.

[0047] According to a second variant, the first zone Z1 may be intended to include a capacitive element structured vertically in the substrate and the second zone Z2 may be intended to include a non-volatile memory, for example both incorporated within a microcontroller.

[0048] The capacitive element may have a vertical structure such as, for example, described in the French Application for Patent Nos. 1757907, 1757906 or 1902278 (the disclosure of which are incorporated by reference).

[0049] The substrate 10 includes a front face 11, which corresponds to the face of the substrate 10 on which electronic components, such as transistors or diodes, will be produced, in the portion also referred to as the “front end of line” (FEOL).

[0050] The front face 11 has been covered with a conventional buffer oxide layer 15. For example, the buffer oxide layer includes about 7 nm of silicon dioxide obtained by deposition or growth.

[0051] A first stop layer 20 has been formed on top of the buffer oxide layer 15 on the front face 11 of the substrate 10, in the first zone Z1 and in the second zone Z2.

[0052] For example, the first stop layer 20 is formed of silicon nitride, and is obtained by low-pressure chemical vapor deposition (LPCVD). The thickness of the first stop layer 20 may be about 80 nm.

[0053] A second stop layer 30 has been formed over the first stop layer 20, in the first zone Z1 and in the second zone Z2.

[0054] For example, the second stop layer 30 is formed of doped silicon nitride, and is obtained by plasma-enhanced chemical vapor deposition (PECVD). The doping may be carried out in situ during deposition or ex situ by later implantation. The thickness of the second stop layer 30 may be about 40 nm. Reference will be made to the description below relating to FIG. 12 for the evaluation of the thickness of the second stop layer 30.

[0055] As an alternative, the second stop layer 30 may be of another nature and be the result of other formation techniques as long as, for example, the conditions described below with reference to FIG. 12 are met.

[0056] An inter-nitride oxide layer 25 has been formed between the first stop layer 20 and the second stop layer 30, and may comprise a thickness of around 5 nm of silicon dioxide.

[0057] FIG. 2 shows the result of a step 200 of removing the second stop layer 30 from the first zone Z1 so that the second stop layer 30 is formed in the second zone Z2 only.

[0058] The removal operation 200 comprises an operation of forming a mask 31, which may be aligned roughly, and a selective etch for etching the second stop layer 30 without reacting with the inter-nitride oxide layer 25. Such a selective etch is typically implemented using a bath of phosphoric acid H.sub.3PO.sub.4.

[0059] FIG. 3 shows the formation of an etch mask 32 which is lithographed to reveal the pattern of the future trenches in the areas of the first stop layer 20 in the first zone Z1 and of the second stop layer 30 in the second zone Z2.

[0060] FIG. 4 shows the result after performing a dry etch 400 delimited by the etch mask 32.

[0061] The dry etch 400, for example using ion bombardment, is capable of etching the second stop layer 30, the inter-nitride oxide layer 25, the first stop layer 20, the buffer oxide layer 15 and the silicon of the substrate 10.

[0062] The dry etch 400 is applied to the structure described above with reference to FIG. 3 for a given amount of time so as to form trenches 410, 415 and 420 in the substrate 10, in the first zone Z1 and in the second zone Z2.

[0063] Thus, in the first zone Z1, the stop layer 20 is first etched in those portions which are not covered by the mask 32. Next, at least one first trench 410 is etched into the substrate 10 down to a first depth P1 relative to the front face 11.

[0064] At the same time, in the second zone Z2, the stack of the second stop layer 30 and of the first stop layer 20 which is not covered by the mask 32 is etched. Next, at least one second trench 420 is etched into the substrate 10 in the time remaining from said time given to the dry etch 400. The second trench 420 thus has a second depth P2 relative to the front face 11. Because of the time taken to remove the second stop layer 30, the substrate 20 has been exposed to the etch 400 for less time in zone Z2, and the second depth P2 is shallower than the first depth P1.

[0065] In this example, a trench 415, referred to as a transition trench, has been formed at the site of the transition between the first zone Z1 and the second zone Z2. Given that, at the site of said transition, one portion (on the right-hand side of the figure) of the opening in the etch mask 32 (FIG. 3) includes the stack of the first stop layer 20 and of the second stop layer 30 while the other portion of the opening (on the left-hand side of the figure) includes only the first stop layer, the bottom of the transition trench 415 will exhibit a variation in depth. The effect of the dry etch 400 on the substrate 10 will produce an inclined plane between the low portion and the high portion of the bottom of the transition trench, which will thereby be asymmetric relative to a median plane of the trench. The description of this asymmetry will be returned to below with reference to FIG. 11.

[0066] FIG. 5 shows the result of the performance of a wet etch 500 which is intended to laterally remove a portion 501 of the remnants of the first stop layer 20 and further to completely remove 502 the second stop layer 30.

[0067] The wet etch may be implemented using a bath of phosphoric acid H.sub.3PO.sub.4, as for example typically used to remove the lateral portions 501 of the first stop layer made of silicon nitride. This step is usually referred to by the term “nitride pullback”.

[0068] Reference is now made to FIG. 12.

[0069] FIG. 12 shows the structure obtained in the process for forming the trenches at the same time as in FIG. 5, after the wet etch 500. The same elements bear the same reference signs and are not described in detail again here.

[0070] As mentioned above with reference to FIG. 5, the wet etch 500 uses a bath of phosphoric acid H.sub.3PO.sub.4 and is therefore selective with respect to the dissolution of silicon nitride and does not react (or at the very least reacts negligibly) with silicon oxide SiO.sub.2 and the silicon of the substrate 10.

[0071] The first stop layer 20, made of silicon nitride, exhibits a given etch speed, or reactivity, with respect to phosphoric acid, the value ER20 of which is, for example, about 8 nm/min.

[0072] The wet etch 500 is configured to remove a width C laterally from the flanks 21 of the first stop layer 20, in the hole formed in the first stop layer 20 by the dry etch 400.

[0073] The second stop layer 30, made of doped silicon nitride or of another material, is configured to exhibit an etch speed, or reactivity, with respect to phosphoric acid, the value ER30 of which is, for example, about 40 nm/min.

[0074] It is assumed that the dry etch 400 is configured to etch the second stop layer 30, the first stop layer 20 and the silicon of the substrate 10 at the same speed such that the difference B2 between the first depth P1 and the second depth P2 is equal to the thickness B1 of the second stop layer 30. Of course, in practice, the abovementioned layers may be etched by the dry etch 400 at speeds that differ slightly from one another. Thus, the resulting difference in depth B2 between the depths P1 and P2 may differ from the thickness B1 of the second stop layer 30. In any case, a person skilled in the art will be able to calculate the difference in depth obtained using knowledge of the etch speeds of the chosen materials with respect to the dry etch 400 used in practice.

[0075] In summary, the wet etch 500 is intended and configured to remove a lateral portion 501 from the flanks 21 of the remnants of the first stop layer 20.

[0076] The second stop layer 30 is configured such that said wet etch 500 results in complete and total removal of the second stop layer 30. For example, the choice of dopant concentration in silicon nitride, or the choice of another material, may allow the second stop layer to be configured to this end.

[0077] Specifically, as will become apparent below with reference to FIG. 7, the first stop layer 20 must be exposed for the polishing step 700.

[0078] Thus, for cost reasons, it is preferable to design the second stop layer 30 for its reactivity with the wet etch 500 rather than to provide an additional etch for removing or completing the removal of the second stop layer 30.

[0079] The maximum thickness B1 of the second stop layer is therefore parametrized by the reactivity ER30 of the material of the second stop layer 30 with respect to phosphoric acid 500.

[0080] Lastly, this thickness B1 results in the difference in depth B2 between the first trenches 410 located in the first zone of the substrate 10 and the second trenches 420 located in the second zone of the substrate 10.

[0081] For example, in practice, if the “nitride pullback” wet etch is limited (by a given technology) to a lateral removal of 30 nm of thickness from the first stop layer 20, then, with k=ER30/ER20, the thickness B1 of the second stop layer 30 is limited to k*30 nm. The thickness B1=k*30 nm introduces a depth difference B2 according to the dry etch 400, for example B2=B1. Consequently, by choosing for example the doping of the silicon nitride of the second stop layer 30 so as to parametrize ratio k, it is possible to parametrize the value of the difference in depth B2 between the first trenches 410 and the second trenches 420.

[0082] The nature and concentration of dopants implanted into the silicon nitride may allow the ratio k to vary from 2 to 20.

[0083] FIG. 6 shows the result of a step of overfilling the trenches 410, 415 and 420 with a trench material 60.

[0084] For example, in the first variant mentioned above with reference to FIG. 1, the trench material 60 may be a dielectric, for example silicon dioxide, so as to form shallow trench isolations (STIs).

[0085] For example, in the second variant mentioned above with reference to FIG. 1, the trench material 60 may be, as an alternative, a conductive material such as polycrystalline silicon so as to form vertical electrodes of capacitive elements in the first zone Z1 and vertical gates of buried transistors in the second zone Z2.

[0086] FIG. 7 illustrates the result of a step 700 of chemically-mechanically polishing the trench material 60, which is stopped once the surface 22 of the first stop layer 20 is reached.

[0087] FIG. 8 shows the result of a typical step 800 of recessing the trench material 60, for example using a bath of hydrofluoric acid if the trench material 60 is silicon dioxide or using a dry etch if the trench material 60 is polycrystalline silicon.

[0088] FIG. 9 shows the result of a typical step 900 of removing the first stop layer 20 using a selective wet etch such as a bath of phosphoric acid H.sub.3PO.sub.4.

[0089] FIG. 10 shows the result of a typical wet etch 1000, in particular in order to remove the buffer oxide layer 15 from the front face 11 of the substrate 10.

[0090] FIG. 11 schematically shows the result of forming a structure 110 on top of the front face 11 of the substrate 10 thus exposed. The structure may, for example, comprise transistors having gates, for example gates that are connected to one another by a polycrystalline silicon bar made from the structure 110.

[0091] It will be noted in the structure of FIG. 11 that is obtained upon completion of the process described above with reference to FIGS. 1 to 11 that a trench 415, referred to as a transition trench, has been formed between the first zone Z1 and the second zone Z2.

[0092] The transition trench 415 runs lengthwise in the direction Y and delimits widthwise the first zone Z1 on one side of the transition trench 415 in the direction X and the second zone Z2 on the other side in the direction X.

[0093] The process that has made it possible to obtain the structure has created, at the bottom of the transition trench 415, an asymmetry relative to a median plane PM in the directions Y and Z, in the middle of the width (X) of the transition trench 415. In other words, the median plane of the transition trench 415 is located between said one side (Z1) and said other side (Z2).

[0094] Where X, Y and Z are three orthogonal directions in space such that the front face 11 of the substrate 10 lies in a plane in the directions X and Y.

[0095] An integrated circuit may advantageously include the structure of FIG. 11 and comprise, in the first zone Z1, at least one first element formed in a first trench 410 extending into the substrate 10 in a direction perpendicular to the front face 11, down to a first depth P1 relative to the front face 11, and, in the second zone Z2, at least one second element formed in a second trench 420 extending into the substrate 10 in a direction perpendicular to the front face 11, down to a second depth P2 relative to the front face 11, the second depth P2 being shallower than the first depth P1.

[0096] The integrated circuit may thus comprise a non-volatile memory with good lateral isolation so that, for example, parasitic effects from leakages are decreased, and a logic portion that is subjected to little or no mechanical stress from the shallow trench isolations.

[0097] The integrated circuit may also comprise a vertical capacitive structure in the substrate exhibiting a high capacitive value per unit area, and in parallel, for example, buried vertical-gate transistors with characteristics that are independent of the depth of the capacitive structure.

[0098] Of course, the invention is not limited to these embodiments but encompasses all variants thereof, and may be applied to portions of an integrated circuit and types of integrated circuit device other than the logic portion, the non-volatile memory and the capacitive element mentioned above.