Mixer bias circuit

Abstract

The present invention discloses a mixer bias circuit including a first reference voltage generation circuit, an amplifier, a first transistor array, a first switch array, a second reference voltage generation circuit, a second transistor array, a second switch array, a first resistive component, and a second resistive component. The mixer bias circuit provides multiple bias voltages by dynamically tracking the common mode voltage of a trans-impedance amplifier (TIA) and compensates for imbalance and mismatch effects by asymmetrically trimming the bias voltages to improve the second-order intercept point of a radio frequency (RF) receiver front-end (RXFE).

Claims

1. A mixer bias circuit applied to a radio frequency (RF) receiver front-end (RXFE), the RF RXFE including a mixer and a trans-impedance amplifier (TIA), the mixer bias circuit having a first output terminal, a second output terminal, and a third output terminal that respectively output a first bias voltage, a second bias voltage, and a third bias voltage, the mixer bias circuit comprising: a first reference voltage generation circuit configured to generate a reference voltage according to a common-mode voltage of the TIA; an amplifier that is coupled to the first reference voltage generation circuit and that has a first input terminal for receiving the reference voltage, a second input terminal coupled to the second output terminal and for receiving the second bias voltage, and an output terminal; a first transistor array including a plurality of first transistors; a first switch array coupled between the first transistor array and the first output terminal and including a plurality of first switches, wherein a total number of the first switches that are to be turned on is based on a calibration code; a second reference voltage generation circuit; a second transistor array including a plurality of second transistors coupled to the second reference voltage generation circuit; a second switch array coupled between the second transistor array and the third output terminal and including a plurality of second switches, wherein a total number of the second switches that are to be turned on is based on the calibration code; a first resistive component coupled between the first output terminal and the second output terminal and having a first resistance; and a second resistive component coupled between the second output terminal and the third output terminal and having a second resistance.

2. The mixer bias circuit of claim 1, wherein the first transistors are in one-to-one correspondence with the first switches, and the second transistors are in one-to-one correspondence with the second switches.

3. The mixer bias circuit of claim 2, wherein a total number of the first switches is equal to a total number of the second switches, and a total number of the first switches that are turned on is equal to a total number of the second switches that are turned on.

4. The mixer bias circuit of claim 2, wherein sources of the first switches are coupled to drains of the corresponding first transistors, gates of the first switches receive the calibration code, and drains of the first switches are coupled to the first output terminal; sources of the second switches are coupled to drains of the corresponding second transistors, gates of the second switches receive the calibration code, and drains of the second switches are coupled to the third output terminal.

5. The mixer bias circuit of claim 1, wherein a total number of the first switches is equal to a total number of the second switches.

6. The mixer bias circuit of claim 1 further comprising: a third resistive component having a third resistance; and a capacitor; wherein the third resistive component and the capacitor are connected in series between the output terminal of the amplifier and the first output terminal.

7. The mixer bias circuit of claim 1, wherein gates of the first transistors are coupled to the output terminal of the amplifier, and gates of the second transistors receive a bias voltage that the second reference voltage generation circuit provides.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG. 1 illustrates a direct-conversion receiver.

[0015] FIG. 2 illustrates a schematic diagram of a core of a conventional double-balanced mixer implemented with NMOSs.

[0016] FIG. 3 illustrates a schematic diagram for compensating an imbalanced mixer via trimming gate bias voltages of the switching transistors in a mixer.

[0017] FIG. 4 illustrates a schematic diagram of a mixer bias circuit of the present invention applied to a radio frequency (RF) receiver front-end (RXFE).

[0018] FIG. 5 illustrates a schematic diagram a mixer bias circuit of the present invention connected to a mixer core.

[0019] FIG. 6 illustrates a circuit diagram of a mixer bias circuit for the I-path according to an embodiment of the present invention.

[0020] FIG. 7 illustrates a circuit diagram of a reference voltage generation circuit according to an embodiment of the present invention.

[0021] FIG. 8 illustrates a detailed circuit diagram of a mixer bias circuit for the I-path or the Q-path according to one embodiment of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] The following description is written by referring to terms of this technical field. If any term is defined in this specification, such term should be explained accordingly. In addition, the connection between objects or events in the below-described embodiments can be direct or indirect provided that these embodiments are practicable under such connection. Said indirect means that an intermediate object or a physical space exists between the objects, or an intermediate event or a time interval exists between the events.

[0023] The disclosure herein includes a mixer bias circuit. On account of that some or all elements of the mixer bias circuit could be known, the detail of such elements is omitted provided that such detail has little to do with the features of this disclosure and this omission nowhere dissatisfies the specification and enablement requirements. A person having ordinary skill in the art can choose components equivalent to those described in this specification to carry out the present invention, which means that the scope of this invention is not limited to the embodiments in the specification.

[0024] FIG. 4 is a schematic diagram of a mixer bias circuit 400 of the present invention applied to a radio frequency (RF) receiver front-end (RXFE). The mixer bias circuit 400 can perform IP2 calibration on the mixer 120 for the I-path and the mixer 125 for the Q-path, respectively. For the I-path, the mixer bias circuit 400 generates the first bias voltage V.sub.IC+, the second bias voltage V.sub.IC and the third bias voltage V.sub.IC according to the calibration code CIP_I outputted by the baseband processor 160 and the common-mode voltage V.sub.CM_I of the TIA 130. The first bias voltage V.sub.IC+, the second bias voltage V.sub.IC and the third bias voltage V.sub.IC are supplied to the mixer 120. For the Q-path, the mixer bias circuit 400 generates the first bias voltage V.sub.QC+, the second bias voltage V.sub.QC and the third bias voltage V.sub.QC according to the calibration code CIP_Q outputted by the baseband processor 160 and the common-mode voltage V.sub.CM_Q of the TIA 135. The first bias voltage V.sub.QC+, the second bias voltage V.sub.QC and the third bias voltage V.sub.QC are supplied to the mixer 125. The calibration codes CIP_I and CIP_Q are generated by the baseband processor 160 according to the IP2 calibration algorithm. The IP2 calibration algorithm is a well-known technique.

[0025] FIG. 5 is a schematic diagram the mixer bias circuit 400 of the present invention connected to a mixer core. As discussed in the prior art, the mixer bias circuit 400 includes circuitry for the I-path and circuitry for the Q-path. FIG. 5 shows the schematic diagram for the I-path, and in this example circuit, the mixer core 320 is the core of the mixer 120. The mixer bias circuit 400a for the I-path generates the first bias voltage V.sub.IC+, the second bias voltage V.sub.IC and the third bias voltage V.sub.IC according to the common-mode voltage V.sub.CM_I and the calibration code CIP_I, and the first bias voltage V.sub.IC+, the second bias voltage V.sub.IC and the third bias voltage V.sub.IC are respectively outputted by the first, second and third output terminals of the mixer bias circuit 400a for the I-path. The mixer core 320 includes two transistor pairsM.sub.MIX_1 and M.sub.MIX_2 being the first pair and M.sub.MIX_3 and M.sub.MIX_4 being the second pair. The gate of one of the transistors of each transistor pair receives the second bias voltage V.sub.IC through the resistor R.sub.BIAS, and the gate of the other transistor receives the first bias voltage V.sub.IC+ or the third bias voltage V.sub.IC through the resistor R.sub.BIAS.

[0026] FIG. 6 is a circuit diagram of a mixer bias circuit 400a for the I-path according to an embodiment of the present invention. The mixer bias circuit 400a for the I-path includes a reference voltage generation circuit 410, an amplifier 420, a first transistor array 430, a first switch array 440, a second switch array 450, a second transistor array 460, a reference voltage generation circuit 470 and an inverter 480. The mixer bias circuit 400a for the I-path outputs the first bias voltage V.sub.IC+, the second bias voltage V.sub.IC and the third bias voltage V.sub.IC through the first output terminal O1, the second output terminal O2 and the third output terminal O3, respectively. The reference voltage generation circuit 410 generates the reference voltage V.sub.M according to the common-mode voltage V.sub.CM_I.

[0027] A first input terminal of the amplifier 420 (e.g., the inverting input terminal) receives the reference voltage V.sub.M. A second input terminal of the amplifier 420 (e.g., the non-inverting input terminal) is coupled to the second output terminal O2 and receives the second bias voltage V.sub.IC. The first transistor array 430 includes a plurality of first transistors, and the gates of the first transistors are coupled to the output terminal of the amplifier 420. The first switch array 440 is coupled between the first transistor array 430 and the first output terminal O1 and includes a plurality of first switches. The number of the turned-on switches in the first switch array 440 is controlled by the calibration code CIP_I.

[0028] The reference voltage generation circuit 470 provides the reference voltage V.sub.R. The second transistor array 460 includes a plurality of second transistors which are coupled to the reference voltage generation circuit 470. The second switch array 450 is coupled between the second transistor array 460 and the third output terminal O3 and includes a plurality of second switches. The number of turn-on switches in the second switch array 450 is controlled by the calibration code CIP_I. Because of the inverter 480, the calibration code received by the first switch array 440 is the inverse of the calibration code received by the second switch array 450.

[0029] The resistor R1_I and the resistor R2_I are connected in series between the first output terminal O1 and the third output terminal O3. More specifically, the resistor R1_I is coupled between the first output terminal O1 and the second output terminal O2, and the resistor R2_I is coupled between the second output terminal O2 and the third output terminal O3. The resistance value of the resistor R1_I may or may not be equal to that of the resistor R2_I.

[0030] The amplifier 420 can be implemented, for example, by an error amplifier. The reference voltage generation circuit 410 and the amplifier 420 constitute a common-mode voltage tracking circuit 405, that is, the second bias voltage V.sub.IC (i.e., the output of the second output terminal O2 and the input of the amplifier 420) is related to the common-mode voltage V.sub.CM_I. In one embodiment, the second bias voltage V.sub.IC increases as the common-mode voltage V.sub.CM_I increases, and the second bias voltage V.sub.IC decreases as the common-mode voltage V.sub.CM_I decreases. The reference voltage V.sub.M can be designed as V.sub.M=V.sub.CM_I+V.sub.th, where V.sub.th is the threshold voltage of the switching transistors M.sub.MIX_1 to M.sub.MIX_4 in the mixer core 320. FIG. 7 is a circuit diagram of the reference voltage generation circuit 410 according to an embodiment of the present invention. The reference voltage generation circuit 410 includes a current source 710, a transistor M.sub.N, and a resistor R.sub.CM. The voltage V.sub.CM is the common-mode voltage (V.sub.CM_I or V.sub.CM_Q) of the TIA.

[0031] FIG. 8 is a detailed circuit diagram of a mixer bias circuit for the I-path or the Q-path according to one embodiment of the present invention. The pass transistors M.sub.P0_I, M.sub.P1_I, . . . , M.sub.PN-1_I, M.sub.PN_I are first transistors that constitute the first transistor array 430. The switching transistors M.sub.PS0_I, M.sub.PS1_I, . . . , M.sub.PSN-1_I, M.sub.PSN_I are first switches that constitute the first switch array 440. The gates of the first transistors are coupled to the output terminal of the amplifier 420. The first transistors are in one-to-one correspondence with the first switches (there are N+1 first transistors and N+1 first switches). More specifically, the pass transistor M.sub.P0_I is connected in series with the switching transistor M.sub.PS0_I, the pass transistor M.sub.P0_I is connected in series with the switching transistor M.sub.PS1_I, and so on.

[0032] Similarly, the current cell transistors M.sub.N0_I, M.sub.N1_I, . . . , M.sub.NN-1_I, M.sub.NN_I are second transistors that constitute the second transistor array 460. The switching transistors M.sub.NS0_I, M.sub.NS1_I, . . . , M.sub.NSN-1_I, M.sub.NSN_I are second switches that constitute the second switch array 450. The gates of the second transistors are coupled to the reference voltage generation circuit 470. The second transistors are in one-to-one correspondence with the second switches (there are N+1 second transistors and N+1 second switches). More specifically, the current cell transistor M.sub.N0_I is connected in series with the switching transistor M.sub.NS0_I, the current cell transistor M.sub.N1_I is connected in series with the switching transistor M.sub.NS1_I, and so on.

[0033] The amplifier 420 controls the gate of pass transistors M.sub.P0_I to M.sub.PN_I to keep the input voltage of the non-inverting input terminal in the amplifier 420 at the same level as the reference voltage V.sub.M. When the common-mode voltage V.sub.CM_I is increased, the amplifier 420 lowers the gate voltage of pass transistors M.sub.P0_I to M.sub.PN_I. This increases the conduction level of pass transistors M.sub.P0_I to M.sub.PN_I, and the second bias voltage V.sub.IC rises again to the regulated voltage of the increased common-mode voltage V.sub.CM_I. Conversely, the second bias voltage V.sub.IC decreases as the common-mode voltage V.sub.CM_I decreases. In this configuration, the pass transistors M.sub.P0_I to M.sub.PN_I can be controlled very close to the MOSFET ON level, which makes it possible to operate the second bias voltage V.sub.IC very close to the reference voltage V.sub.M. Additionally, the feature of a common-mode voltage tracking is introduced to ensure that the gate bias voltages V.sub.IC, V.sub.IC+, and V.sub.IC of the switching transistors in the mixer 120 is dynamically working at a critical bias point versus a common-mode voltage variation from a TIA. As mentioned above, the gate bias voltages V.sub.IC, V.sub.IC+, and V.sub.IC are also dynamically tracking with the common-mode voltage V.sub.CM_I and subsequently minimizes the variation in the optimized IP2 calibration, when a common-mode voltage variation is caused by a TIA.

[0034] The reference voltage generation circuit 470 includes a voltage source 475, a current source I.sub.R, and a current sink transistor M.sub.B_I. The voltage source 475 is, for example, a bandgap voltage reference circuit that can provide a stable voltage. The reference voltage generation circuit 470 provides a reference voltage V.sub.R at the gate of the current sink transistor M.sub.B_I. The gate of each of the second transistors of the second transistor array 460 is coupled to the gate of the current sink transistor M.sub.B_I, such that each of the second transistors pairs with the current sink transistor M.sub.B_I to form a current mirror.

[0035] The number of bits of the calibration code CIP_I is equal to the number of the first (or second) switches (the number being N+1), and the bits of the calibration code CIP_I are in one-to-one correspondence with the first (or second) switches. That is to say, the least significant bit (LSB) of the calibration code CIP_I (b.sub.0_I) controls the transistors M.sub.PS0_I and M.sub.NS0_I to be turned on or off, and the most significant bit (MSB) of the calibration code CIP_I (b.sub.N_I) controls the transistors M.sub.PSN_I and M.sub.NSN_I to be turned on or off. The first switch and the second switch are turned on or off in pairs. For example, the transistors M.sub.PS0_I and M.sub.NS0_I are controlled by the bit b.sub.0_I to be simultaneously turned on or off, the transistors M.sub.PS1_I and M.sub.NS1_I are controlled by the bit b.sub.1_1 to be simultaneously turned on or off, . . . , the transistors M.sub.PSN_I and M.sub.NSN_I are controlled by the bit b.sub.N_I to be simultaneously turned on or off. In a preferred embodiment, N is an integer greater than or equal to one.

[0036] The correction current I.sub.CAL_I can be expressed as follows, where I.sub.MPn_I is the drain current of the n.sup.th pass transistor M.sub.Pn_I, and I.sub.MNn_I is the drain current of the n.sup.th current cell transistor M.sub.Nn_I):

I.sub.Cal_I.sub.n=0.sup.NI.sub.MPn_I.sub.n=0.sup.NI.sub.MNn_I(1)

[0037] By changing the value of the calibration code CIP_I, the correction current I.sub.CAL_I can be trimmed, which in turn trims the first bias voltage V.sub.IC+ and the third bias voltage V.sub.IC. Therefore, the voltage drops I.sub.Cal_IR1_I and I.sub.Cal_IR2_I can be generated according to N+1 bits calibration code for I-path (CIP_I) to trim the gate bias voltage of the switching transistors M.sub.MIX_1 and M.sub.MIX_4 in the mixer 120. The first bias voltage V.sub.IC+ and the third bias voltage V.sub.IC can be denoted as V.sub.IC+=V.sub.IC+I.sub.Cal_IR1_I and V.sub.IC=V.sub.ICI.sub.Cal_IR2_I, respectively. Because the characteristic of the I-path chain may be different from that of the Q-path chain, the baseband processor 160 generates the N+1 bits calibration code for the I-path chain (CIP_I) and the N+1 bits calibration code for the Q-path chain (CIP_Q). Because the calibration code CIP_I may be independent of the calibration code CIP_Q, the first bias voltage V.sub.IC+ and the third bias voltage V.sub.IC for the I-path may be different from the first bias voltage V.sub.QC+ and the third bias voltage V.sub.QC for the Q-path. Additionally, the calibration codes CIP_I and CIP_Q are controlled and generated according to an IP2 algorithm via the baseband processor 160.

[0038] The resistor R_I and capacitor C_I are connected in series to form a feedforward path and subsequently improves the stability of the I-path IP2 calibration working at the LSB of the N+1 bits calibration code for the I-path. The resistor R_I and the capacitor C_I are optional, that is, the output terminal of the amplifier 420 can alternatively be coupled to the first output terminal O1 directly. The current source I.sub.R can be a current source having characteristics independent of absolute temperature to prevent the variation in the IP2 performance versus temperature.

[0039] FIGS. 5, 6 and 8 are illustrative circuits for the I-path. The mixer bias circuits for the I-path and the Q-path are substantially the same; people having ordinary skill in the art can understand details for the Q-path based on the above discussions. The mixer bias circuits for the I-path and the Q-path can share the voltage source 475 and the current source I.sub.R. Although the transistors in the illustrative circuits as shown in the figures are implemented by MOSFETs, people having ordinary skill in the art can use other types of transistors based on the above discussions, such as bipolar junction transistors (BJTs).

[0040] The proposed mixer bias circuit, which has IP2 calibration function and acts as DC gate biasing for the switching transistors in a mixer, is used to reduce the imbalance between the I-path and Q-path chains of a direct-conversion RF RXFE, as shown in FIG. 4. By asymmetrically trimming the gate voltages V.sub.IC, V.sub.IC+, V.sub.IC, V.sub.QC, V.sub.QC+, and V.sub.QC of the switching transistors in the mixer 120 and the mixer 125, the imbalance and mismatch effects can be compensated, resulting in an IP2 improvement of an RF RXFE.

[0041] From another perspective, the mixer bias circuit 400a for the I-path comprises a common-mode voltage tracking circuit 405 and N+1 bits complementary array based low-dropout regulator (LDO). As shown in FIGS. 6 and 8, the N+1 bits complementary array based LDO includes the amplifier 420, the first transistor array 430, the first switch array 440, the resistor R1_I, the resistor R2_I, the second switch array 450, the second transistor array 460 and the current sink transistor M.sub.B_I. Here, the term complementary indicates that the P-channel MOSFETs (hereinafter referred to as PMOSs) and NMOSs are simultaneously employed in the circuits. The proposed N+1 bits complementary array based LDO, which is a multiple-input multiple-output (MIMO) architecture (multiple bits input and multiple voltages output), is useful for trimming the gate bias voltages of the switching transistors M.sub.MIX_1 to M.sub.MIX_4 in a mixer.

[0042] In some embodiments, the above-mentioned resistors are resistive components implemented by active components, such as MOSFETs or junction field-effect transistors (JFETs). For a JFET under certain operating conditions, the resistance of the drain-source channel is a function of the gate-source voltage alone and the JFET will behave as an almost pure ohmic resistor.

[0043] Please note that the shape, size, and ratio of any element and the step sequence of any flow chart in the disclosed figures are exemplary for understanding, not for limiting the scope of this invention.

[0044] The aforementioned descriptions represent merely the preferred embodiments of the present invention, without any intention to limit the scope of the present invention thereto. Various equivalent changes, alterations, or modifications based on the claims of the present invention are all consequently viewed as being embraced by the scope of the present invention.