ELECTRONIC CIRCUIT FOR A FIELD DEVICE USED IN AUTOMATION TECHNOLOGY

Abstract

The disclosure is related to an electronic circuit for a field device of automation technology, comprising: a first digital processor having a first set of machine commands for executing an algorithm running in the processor, wherein the first processor is adapted to execute a test algorithm to calculate output data, wherein the test algorithm uses for calculating the output data at least a part of the first set of machine commands, which are used for executing the algorithm, a second digital processor having a second set of machine commands for executing at least one verification algorithm, wherein the second processor is adapted to execute the verification algorithm to calculate verification data, and wherein the electronic circuit including the second processor is adapted, based on the output data calculated by the first processor and the verification data calculated by the second processor, to perform a checking of the first processor.

Claims

1-11. (canceled)

12. An electronic circuit for a field device of automation technology, comprising: a first digital processor having a first set of machine commands adapted for executing a measured value algorithm running in the first processor for calculating a digital measured value based on a raw measured value, wherein the first processor uses at least a part of the first set of machine commands for executing the algorithm, wherein the first processor is further adapted to execute a test algorithm to calculate an output data based on an input data, wherein the test algorithm is divided at least into a start section and an end section and the first processor is further adapted to execute at least a part of the measured value algorithm between the start section and the end section of the test algorithm, wherein the test algorithm uses for calculating the output data at least a part of the first set of machine commands which are used for executing the measured value algorithm; and a second digital processor having a second set of machine commands for executing a verification algorithm, wherein the second processor is fed the input data and the output data of the first processor and the second processor is adapted to execute the verification algorithm to calculate verification data based on the fed input data, wherein the verification algorithm uses for calculating the verification data machine commands of the second set corresponding to at least a part of the first set of machine commands which are used for executing the measured value algorithm, wherein the verification algorithm is permanently coded in the second processor so that the verification algorithm does not have to be written into the second processor upon starting the field device, wherein the electronic circuit including the second processor is adapted, based on the output data calculated by the first processor and the verification data calculated by the second processor, to perform a checking of the first processor.

13. The electronic circuit as claimed in claim 12, wherein the first processor is adapted to execute the test algorithm cyclically, and the second processor is adapted to execute the verification algorithm cyclically so that a cyclic checking of the first processor occurs.

14. The electronic circuit as claimed in claim 12, wherein the test algorithm and the verification algorithm each have less executed steps than the measured value algorithm for calculating the measured value.

15. The electronic circuit as claimed in claim 12, wherein the electronic circuit is adapted to produce an input data changing as a function of time for the test algorithm and to supply the changing input data to the first processor for executing the test algorithm and to the second processor for executing the verification algorithm.

16. The electronic circuit as claimed in claim 15, wherein the electronic circuit is further adapted such that the first processor and the second processor use the raw, measured values or values derived from the raw, measured values as input data for the test algorithm and for the verification algorithm.

17. The electronic circuit as claimed in claim 15, wherein the electronic circuit is further adapted such that the first processor and the second processor use a random signal as input data for the test algorithm and for the verification algorithm.

18. The electronic circuit as claimed in claim 15, wherein the electronic circuit is further adapted such that the first processor and the second processor use a counter signal as input data for the test algorithm and for the verification algorithm.

19. A method for cyclically checking a first digital processor having a first set of machine commands by a second digital processor having a second set of machine commands, the method comprising: executing cyclically a measured value algorithm for calculating a measured value in the first processor, wherein at least a part of the first set of machine commands of the first processor is used for the executing; executing cyclically in the first processor a test algorithm subdivided into at least a start section and an end section, wherein at least a part of the measured value algorithm is executed by the first processor between the start section and the end section of the test algorithm, wherein the test algorithm calculates output data based on input data, wherein at least a part of the first set of machine commands which are used for executing the measured value algorithm is used for calculating the output data; executing cyclically a verification algorithm in the second processor, wherein verification data are calculated by the verification algorithm based on the input data, wherein for calculating the verification data machine commands of the second set are used, which correspond to at least a part of the first set of machine commands which are used for executing the measured value algorithm, wherein the verification algorithm is permanently coded in the second processor, so that the verification algorithm does not have to be written into the second processor upon the starting the field device; and checking cyclically the first processor based on the output data calculated by the first processor and the verification data calculated by the second processor.

20. The method as claimed in claim 19, wherein used as input data are data changing as a function of time, including data of a counter or a random signal generator or data of the raw measured value or data derived from the raw measured value.

21. The method as claimed in claim 19, wherein the test algorithm is divided into at least a start section and an end section and the measured value algorithm is executed at least partially between the start section and the end section.

22. The method as claimed in claim 19, wherein in executing the test algorithm and the verification algorithm less steps are executed by the first and second processor than would be necessary in the case of executing the measured value algorithm for calculating the measured value.

Description

[0027] The invention will now be explained in greater detail based on the appended drawing, the figures of which show as follows:

[0028] FIG. 1 a schematic block diagram of a field device having an electronic circuit known from the state of the art, and

[0029] FIG. 2 a schematic block diagram of an example of an embodiment of a field device, which comprises an electronic circuit constructed according to the invention.

[0030] The field device 100 shown in FIG. 1 includes an electronic circuit, which is composed of a sensor module 10, a main electronics module 20, and digital communication interfaces 16, 24 complementary to one another.

[0031] Sensor module 10 includes a transducer element 11, for example, a capacitively or resistively working, pressure transducer element, and a sensor electronics 12, wherein raw, measured values in the form of a primary signal are led from the transducer element to an analog sensor input 14 of the sensor electronics 12. These raw, measured values are digitized by the sensor electronics 12 and then further processed, or conditioned, by a first digital processor 1, for example, a digital signal processor, by means of an algorithm Comp running on the processor 1, into corresponding measured values. Typically, there occurs by means of the algorithm Comp running in the digital signal processor 1 a temperature compensation of the raw measured value. The conditioned measured value is provided to the main electronics module via a first digital communication interface 16.

[0032] The main electronics module 20 includes in the illustrated example of an embodiment a logic unit 22, an electrical current regulator 32, a HART modem 34 and a communication interface, for example, an electrical current sink 36.

[0033] Logic unit 22 includes a second digital processor, for example, a microprocessor, and a second digital communication interface 24, which communicates with the first digital communication interface 16. For example, the digital measured value is transmitted via this digital communication connection during normal measurement operation, and the logic unit 22 causes the electrical current regulator 32 via a third digital communication interface 26 so to control the electrical current sink 36 that it carries an analog electrical current signal, which represents the digital measured value or a measured variable derived therefrom.

[0034] Furthermore, the logic unit 22 includes a fourth digital communication interface 30, via which the HART modem 34 is operated, in order to modulate onto the analog electrical current signal digital information, for example, status information.

[0035] The electronic circuits known from the state of the art are adapted in such a manner that in the first processor 1 the algorithm Comp is executed with at least partial use of the machine commands available for the first processor 1. In order to conform to the above-mentioned SIL measures, the algorithm Comp is employed likewise in the second processor 2. This calculates with the help of the machine commands of the second processor 2 the verification data V on the output. The verification data V obtained by the second processor 2 are then compared with the output data 0 obtained by the first processor 1, in order to enable a checking of the first processor 1.

[0036] FIG. 2 shows a schematic block diagram of an example of an embodiment of a field device, which comprises an electronic circuit constructed according to the invention. The field device 100 shown in FIG. 2 and especially its electronic circuit correspond as regards their physical embodiment essentially to the example of an embodiment of FIG. 1.

[0037] Different is that the first processor 1 is adapted in such a manner that in it are running both the algorithm Comp as well as also a test algorithm Opcode with the help of at least a part of the machine commands of the first processor 1. The test algorithm Opcode serves to calculate output data 0 based on input data I. The test algorithm Opcode is embodied in such a manner that it uses, at least once, all machine commands, or all Opcodes, which are required for executing the algorithm Comp. Furthermore, the test algorithm Opcode is divided into at least a start section OPCT1 and an end section OPCT2 and the first processor 1 is adapted in such a manner that at least a part of the algorithm Comp, preferably the entire algorithm Comp, is executed between the start section OPCT1 and the end section OPCT2. Another option provides that the test algorithm Opcode and the algorithm Comp are each divided into a plurality of sections C1 . . . Cn, and S1 . . . Sn, and the first processor 1 alternately executes a part of the test algorithm and then a part of the actual algorithm, until the two algorithms have been passed through.

[0038] Used as input data I for the test algorithm Opcode can be especially data changing as a function of time. For example, the raw, measured values coming from the transducer element 11 or values derived therefrom can be used. Likewise possible is to use a random signal, for example, a random signal produced by a random signal generator, or a counter signal as input data.

[0039] The second processor 2 is adapted in such a manner that a verification algorithm OPCT runs on such with the help of at least a part of the machine commands of the second processor 2. The verification algorithm OPCT serves exactly as the test algorithm Opcode in that, based on the supplied output data 0, which serve as input data, verification data V are calculated. It is embodied in such a manner that it uses at least a part, preferably all, of the machine commands of the second processor 2 corresponding to machine commands, which are required for executing the algorithm Comp in the first processor 1. Essentially, the verification algorithm corresponds, thus, to the test algorithm with the difference that the verification algorithm is adapted for the computer architecture of the second processor and is preferably not divided into sections in the second computer. Typically, however, not necessarily, the test algorithm and/or the verification algorithm have/has less executed steps than the algorithm Comp.

[0040] The electronic circuit is, furthermore, adapted to compare the output data calculated by the first processor based on the test algorithm and the verification data calculated by the second processor based on the verification algorithm, and, when a deviation is detected, to output a failure report.

[0041] As regards fulfillment of the above described SIL measures, it can be provided that the checking is performed cyclically, i.e. recurringly, in the ongoing measurement operation of the field device 100.

LIST OF REFERENCE CHARACTERS

[0042] 100 field device [0043] 1 first digital processor [0044] 2 second digital processor [0045] 10 sensor module [0046] 11 transducer element [0047] 12 sensor electronics [0048] 14 communication interface [0049] 16 communication interface [0050] 20 main electronics module [0051] 22 logic unit [0052] 24 communication interface [0053] 26 communication interface [0054] 30 communication interface [0055] 32 electrical current regulator [0056] 36 electrical current sink [0057] 34 HART modem [0058] Comp algorithm for calculating measured value [0059] Opcode test algorithm [0060] I input data [0061] O output data [0062] OPCT verification algorithm [0063] OPCT1 start section of the verification algorithm [0064] OPCT2 end section of the verification algorithm [0065] V verification data [0066] C1 . . . Cn program sequence, parts of the test algorithm [0067] S1 . . . Sn program sequence, parts of the algorithm