SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURE

Abstract

A semiconductor device is provided, including a leadframe, a die attached to the leadframe using a first solder, a source clip and a gate clip attached to the die using a second solder, and a drain clip attached to the leadframe. The semiconductor device is inverted, so that the source clip and the gate clip are positioned on the bottom side of the semiconductor device, and the leadframe is positioned on the top side of the semiconductor device so that the leadframe is a top exposed drain clip. The source clip and/or the drain clip comprise a half cut locking feature. The half cut locking feature can be formed as a wing and located at the sides of the source clip and the gate clip.

Claims

1. A semiconductor device comprising: a leadframe; a die attached to the leadframe using a first solder; a source clip and a gate clip attached to the die using a second solder a drain clip attached to the leadframe; wherein the semiconductor device is inverted, so that the source clip and the gate clip are positioned on a bottom side of the semiconductor device; wherein the leadframe is positioned on a top side of the semiconductor device so that the leadframe is a top exposed drain clip; and wherein the source clip and/or the gate clip comprise a half cut locking feature.

2. The semiconductor device as claimed in claim 1, wherein the half cut locking feature is formed as a wing and located at the sides of the source clip and the gate clip.

3. The semiconductor device as claimed in claim 1, wherein the half cut locking feature is about 50% as thick, as a thickness of the source clip and/or the gate clip.

4. The semiconductor device as claimed in claim 1, wherein the half cut locking feature, the source clip and the gate clip are made of copper.

5. The semiconductor device as claimed in claim 1, wherein the drain clip comprises a dual bending.

6. The semiconductor device as claimed in claim 1, wherein the semiconductor device is selected from the group consisting of: a PQFN semiconductor device, a HEMT semiconductor device, and a MOSFET semiconductor device.

7. The semiconductor device as claimed in claim 1, further comprising two cooling systems, a first cooling system positioned on the top side on the semiconductor device and a second cooling system positioned on the bottom side of the semiconductor device.

8. The semiconductor device as claimed in claim 2, wherein the half cut locking feature is about 50% as thick, as a thickness of the source clip and/or the gate clip.

9. The semiconductor device as claimed in claim 5, wherein the dual bended drain clip is made of copper.

10. The semiconductor device as claimed in claim 5, wherein the dual bending has a bending angle that is about 90 degrees.

11. The semiconductor device as claimed in claim 5, wherein the dual bending is arranged to prevent any mechanical tilting within the semiconductor device.

12. The semiconductor device as claimed in claim 5, wherein the dual bending is arranged to maintain a same level for all parts of the semiconductor device, allowing both drain terminals to be exposed on a top and a bottom side of the package.

13. The semiconductor device as claimed in claim 9, wherein the dual bending has a bending angle that is about 90 degrees.

14. The semiconductor device as claimed in claim 9, wherein the dual bending is arranged to prevent any mechanical tilting within the semiconductor device.

15. The semiconductor device as claimed in claim 9, wherein the dual bending is arranged to maintain a same level for all parts of the semiconductor device, allowing both drain terminals to be exposed on a top and a bottom side of the package.

16. The semiconductor device as claimed in claim 10, wherein the dual bending is arranged to prevent any mechanical tilting within the semiconductor device.

17. A method of producing a semiconductor device, the method comprising the steps of: creating a leadframe; dispensing a first solder on a top of the leadframe; attaching a die via the first solder to the leadframe; creating source, gate and drain clips; wherein the drain clip is bended and attached the respective leadframe; and wherein the source and drain clips are attached to the die; providing a molding; grinding or polishing so to expose the source, gate and drain terminals; singulation; inverting the semiconductor device; and mounting, wherein the source clip and/or the drain clip comprise a half cut locking feature.

18. The method of producing a semiconductor device as claimed in claim 17, wherein the half cut locking feature is formed as a wing and located at the sides of the source clip and the gate clip.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] So that the manner in which the features of the present disclosure can be understood in detail, a more particular description is made with reference to embodiments, some of which are illustrated in the appended figures. It is to be noted, however, that the appended figures illustrate only typical embodiments and are therefore not to be considered limiting of its scope. The figures are for facilitating an understanding of the disclosure and thus are not necessarily drawn to scale. Advantages of the subject matter claimed will become apparent to those skilled in the art upon reading this description in conjunction with the accompanying figures, in which like reference numerals have been used to designate like elements, and in which:

[0032] FIG. 1 shows a known semiconductor device.

[0033] FIG. 2 illustrates a semiconductor device according to an embodiment of the invention.

[0034] FIG. 3 illustrates a semiconductor device according to an embodiment of the invention.

[0035] FIG. 4 illustrates a method of manufacturing of a semiconductor device according to an embodiment of the invention.

DETAILED DESCRIPTION

[0036] FIG. 2 illustrates an embodiment of the present invention. A semiconductor device 100 comprises a leadframe 102, a die 106 attached to the leadframe 102 via a first solder 104, and a source clip 110, and a gate clip 119 attached to the die 106 via a second solder 108.

[0037] The semiconductor device 100 further comprises a mold 120, wherein the mold is arranged so that a source 110, gate 119 and a drain 114 of the semiconductor device 100 are partially exposed on a first side 124a of the semiconductor device 100. A partially exposed part of the source clip 110 is marked with the reference number 122. The leadframe 102 is acting as an exposed drain 112 of the semiconductor device, and this exposed drain 112 is on a second side 124 of the semiconductor device.

[0038] Such a semiconductor device is inverted, so that the source 110, the gate 119 and the drain 114 are positioned on the bottom of such a semiconductor device 100 and wherein the leadframe 102 is positioned on the top of such semiconductor device 100, which the leadframe 102 is the exposed drain 112.

[0039] According to an embodiment of the present invention, the leadframe 102 is comprising a dual bending 116, also called a dual step, at the end where the partially exposed drain 114 is located. The drain can be made of copper. Advantage of such a dual bending 116 is that the partially exposed drain 114 will contribute to an uncontrolled coplanarity due to spring back return and inconsistency of leads coplanarity with package surface. This is critical for moulding process. Controlling the coplanarity against the package surface of bended tip of the die paddle is also hard to control due to multiple tolerance to combine such as cutting the exposed lead tip followed by bending. An alternative way of controlling this is by flat leads, i.e. a single step continuous Cu with partially exposed flat leads. This is shown in FIG. 3, reference sign 130. The usage of the above described dual step forming is recommended so to form the drain exposed on both top and bottom of the package much easier to manufacture. A dual step forming will have a better control as spring back return during forming will be avoided, normally brought by reaction of variability of radius applied on the bending.

[0040] According to an embodiment of the present invention, the source clip 110 and/or gate clip 119 comprise a half cut locking (a half cut locking for source clip is marked with the reference number 118, a half cut locking for gate clip is marked with the reference number 118b), which half cut locking can be preferably about 50% of copper material thickness, and which half cut locking is/are located on the side of the source clip and/or gate clip, formed as a wing. Having such half cut locking 118/118b, significantly improve the reliability of the manufacturing process of such a semiconductor device, since partially exposing source and drain terminals without locking features will result to package crack during clip and package singulation.

[0041] Since partial embedding of source and drain terminals will guarantee fillet formations on the lead terminal sides, the effectivity of this also depends on how the clips are locked on the plastic, thus additional half cut feature, formed like a wing, located on the sides of the clips were added. This is to ensure locking that will be stable during clip singulation process.

[0042] The invention also relates to a method of producing a semiconductor device. The method is shown in FIG. 4.

[0043] The method comprises the steps: [0044] creating a leadframe 102, preferably with a dual step bending (reference number 202 in FIG. 4), [0045] a first solder 104 dispensed on the top of the leadframe 102 (reference number 204 in FIG. 4), [0046] attaching a die 106 via the solder 104 to the leadframe 102 (reference number 206 in FIG. 4), [0047] a second solder 108 dispensed on the top of the die 106 (reference number 208 in FIG. 4), [0048] attaching a source clip 110 and a gate clip 119 to the die 106 via a second solder 108 (reference number 210 in FIG. 4), wherein the source clip 110 is preferably created with a half cut locking feature 118, preferably formed like wings 118, and/or the gate clip 119 is preferably created with a half cut locking feature 118b, preferably formed like wings 118b, [0049] providing over molding 120 (reference number 212 in FIG. 4), wherein over molded package 121 is created, wherein the molding is arranged so that the source 110 and the drain 114 are partially exposed, [0050] grinding or polishing so to remove the top molding and to expose the drain terminal 112 (reference number 214 in FIG. 4), and [0051] singulation (reference number 216 in FIG. 4).

[0052] A semiconductor device created according to above described method is inverted and mounted.

[0053] A semiconductor device created by this method is shown in FIG. 4, wherein a top view of the semiconductor device marked with the reference numbers 217a and 217b, and wherein a bottom view of the semiconductor device marked with the reference numbers 217c and 217d.

[0054] The embodiments of the present invention are applicable for all semiconductor packages/devices using clips as interconnects.

[0055] A semiconductor device according to an embodiment of the present invention is especially advantageous for PQFN semiconductor devices used at the automotive markets.

[0056] The semiconductor device having the gate and source clips modified under EMC with side protrusions, made by half cut locking features, which are fully encapsulated provide a significantly improved robustness, i.e. a significant mechanical benefit.

[0057] A semiconductor discrete package with terminals on one side of the package that are partially embedded inside a plastic encapsulation, locked in the plastic through the use of single or multiple half cut locking features located at the side of the copper, formed like a wing, has advantages over the known semiconductor devices.

[0058] Such a semiconductor discrete package with top and bottom drain exposed will not have a problem of an uncontrolled coplanarity and inconsistency of leads coplanarity with package surface. Using dual step bending, as described in the embodiments of the present invention, so to form the drain exposed on both top and bottom of the package will have a better control as spring back return during forming will be avoided, normally brought by reaction of variability of radius applied on the bending. Therefore the semiconductor package will not suffer of a possible package crack during the clip singulation.

[0059] Furthermore, providing partially embedding of the terminals with additional half cut locking feature formed like a wing, located on the sides of the clips, will provide a further advantage. This feature will ensure locking so that the package is stable during clip singulation process.

[0060] The semiconductor device according to the embodiments of the present invention can be also used for semiconductor packages with dual exposed heatsink, dual cool packages, microlead packages, all semiconductor packages using a clip as interconnects (integrated to leads or internal clips), power packages using a solder as die attach material, and similar.

[0061] Particular and preferred aspects of the invention are set out in the accompanying independent claims. Combinations of features from the dependent and/or independent claims may be combined as appropriate and not merely as set out in the claims.

[0062] The scope of the present disclosure includes any novel feature or combination of features disclosed therein either explicitly or implicitly or any generalisation thereof irrespective of whether or not it relates to the claimed invention or mitigate against any or all of the problems addressed by the present invention. The applicant hereby gives notice that new claims may be formulated to such features during prosecution of this application or of any such further application derived therefrom. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in specific combinations enumerated in the claims.

[0063] Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub combination.

[0064] The term “comprising” does not exclude other elements or steps, the term “a” or “an” does not exclude a plurality. Reference signs in the claims shall not be construed as limiting the scope of the claims.