Component Carrier and Method of Manufacturing the Same

Abstract

A method of manufacturing a component carrier includes a step of stacking and connecting a first component and a second component to one another to form a cluster and thereafter, a step of inserting the cluster into a cavity of a base structure. A component carrier has a base structure with a cavity; a cluster having a first component stacked and connected with a second component, wherein the cluster is arranged in the cavity. A height difference between opposing lateral sidewalls of the cluster is less than 15 m.

Claims

1. A method of manufacturing a component carrier, comprising: stacking and connecting a first component and a second component to one another to form a cluster; thereafter, inserting the cluster into a cavity of a base structure.

2. The method according to claim 1, comprising at least one of the following features: the first component has at least one pad face up and the second component has at least one pad face down; at least one of the first component and the second component has at least one pad face up; at least one of the first component and the second component has at least one pad face down.

3. The method according to claim 1, wherein the cluster comprising the first component and the second component is encapsulated in a common encapsulant, in particular by molding.

4. The method according to claim 1, comprising at least one of the following features: the first component has another height than the second component; one main surface of the first component is in alignment with one main surface of the second component within the cluster; at least one of the first component and the second component is an active component, in particular a semiconductor chip; the method further comprises arranging at least one passive component in the cavity.

5. The method according to claim 1, wherein a direct electric connection is established between the first component and at least one of the second component and an electrically conductive layer structure of the base structure.

6. The method according to claim 1, wherein the method further comprises: connecting the base structure and the cluster by a filling medium, in particular by at least one of an adhesive and an at least partially uncured layer structure.

7. The method according to claim 1, wherein, prior to connecting the base structure and the cluster, a temporary carrier is connected to the base structure and the cluster, and after connecting the base structure and the cluster, the temporary carrier is removed.

8. The method according to claim 1, wherein, after connecting the base structure and the cluster, at least one pad of at least one of the first component and the second component is electrically connected to an electrically conductive layer structure of the component carrier.

9. The method according to claim 1, wherein an angle between a main surface of the first component and an opposing main surface of the second component, at which main surfaces the first component and the second component are connected, is less than 10, in particular less than 5.

10. The method according to claim 1, wherein the first component and the second component are connected on a wafer level.

11. A component carrier, comprising: a base structure having a cavity; and a cluster comprising a first component stacked and connected with a second component, wherein the cluster is arranged in the cavity; wherein a height difference between opposing lateral sidewalls of the cluster is less than 15 m, particularly less than 5 m.

12. The component carrier according to claim 11, comprising at least one of the following features: the first component has at least one pad face up and the second component has at least one pad face down; at least one of the first component and the second component has at least one pad face up; at least one of the first component and the second component has at least one pad face down.

13. The component carrier according to claim 11, wherein the cluster comprising the first component and the second component is encapsulated in a common encapsulant, in particular in a mold compound.

14. The component carrier according to claim 11, comprising at least one of the following features: the first component has another height than the second component; one main surface of the first component is in alignment with one main surface of the second component within the cluster; at least one of the first component and the second component is an active component, in particular a semiconductor chip; the component carrier further comprising at least one passive component in the cavity.

15. The component carrier according to claim 11, wherein a direct electric connection is established between the first component and at least one of the second component and an electrically conductive layer structure of the base structure.

16. The component carrier according to claim 11, wherein the base structure and the cluster are connected by a filling medium, in particular by at least one of an adhesive and an at least partially uncured layer structure.

17. The component carrier according to claim 11, wherein an angle between a main surface of the first component and an opposing main surface of the second component, at which main surfaces the first component and the second component are connected, is less than 10, in particular is less than 5.

18. The component carrier according to claim 11, wherein the first component and the second component are connected on a wafer level.

19. The component carrier according to claim 11, wherein a height difference between opposing lateral sidewalls of the cluster is less than 1 m, particularly less than 500 nm, more particularly less than 100 nm.

20. The component carrier according to claim 11, wherein at least one of the first component and the second component, in particular an electronic component, is mounted on and/or embedded in at least one electrically insulating layer structure and/or at least one electrically conductive layer structure of the cavity of the base structure.

21. The component carrier according to claim 11, comprising at least one of the following features: the component carrier comprises at least one component being surface mounted on and/or embedded in the component carrier, wherein the at least one component is in particular selected from a group consisting of an electronic component, an electrically non-conductive and/or electrically conductive inlay, a heat transfer unit, a light guiding element, an energy harvesting unit, an active electronic component, a passive electronic component, an electronic chip, a storage device, a filter, an integrated circuit, a signal processing component, a power management component, an optoelectronic interface element, a voltage converter, a cryptographic component, a transmitter and/or receiver, an electromechanical transducer, an actuator, a microelectromechanical system, a microprocessor, a capacitor, a resistor, an inductance, an accumulator, a switch, a camera, an antenna, a magnetic element, a further component carrier, and a logic chip; wherein at least one of the electrically conductive layer structures of the component carrier comprises at least one of the group consisting of copper, aluminum, nickel, silver, gold, palladium, and tungsten, any of the mentioned materials being optionally coated with supra-conductive material such as graphene; wherein the electrically insulating layer structure comprises at least one of the group consisting of resin, in particular reinforced or non-reinforced resin, for instance epoxy resin or Bismaleimide-Triazine resin, FR-4, FR-5, cyanate ester, polyphenylene derivate, glass, prepreg material, polyimide, polyamide, liquid crystal polymer, epoxy-based Build-Up Film, polytetrafluoroethylene, a ceramic, and a metal oxide; wherein the component carrier is shaped as a plate; wherein the component carrier is configured as one of the group consisting of a printed circuit board, a substrate, and an interposer; wherein the component carrier is configured as a laminate-type component carrier.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0055] FIG. 1 illustrates a cross-sectional view of a preform of a component carrier being presently under manufacture according to an exemplary embodiment of the invention.

[0056] FIG. 2 illustrates a method of manufacturing a component carrier according to an embodiment of the invention.

[0057] FIG. 3 illustrates a method of manufacturing a component carrier according to another embodiment of the invention.

[0058] FIG. 4 illustrates a cross-sectional view of a schematic preform of a component carrier according to an exemplary embodiment of the invention.

[0059] FIG. 5 illustrates a cross-sectional view of a schematic preform of a component carrier according to an exemplary embodiment of the invention.

[0060] FIG. 6 illustrates a cross-sectional view of a schematic preform of a component carrier according to an exemplary embodiment of the invention.

[0061] FIG. 7 illustrates a cross-sectional view of a schematic preform of a component carrier according to an exemplary embodiment of the invention.

[0062] FIG. 8 illustrates a cross-sectional view of a schematic preform of a component carrier according to an exemplary embodiment of the invention.

[0063] FIG. 9 illustrates a cross-sectional view of a schematic preform of a component carrier according to an exemplary embodiment of the invention.

[0064] FIG. 10 illustrates a cross-sectional view of a schematic preform of a component carrier according to an exemplary embodiment of the invention.

DETAILED DESCRIPTION OF ILLUSTRATED EMBODIMENTS

[0065] The aspects defined above and further aspects of the invention are apparent from the examples of embodiment to be described hereinafter and are explained with reference to these examples of embodiment.

[0066] The illustrations in the drawings are schematically presented. In different drawings, similar or identical elements are provided with the same reference signs.

[0067] Before, referring to the drawings, exemplary embodiments will be de-scribed in further detail, some basic considerations will be summarized based on which exemplary embodiments of the invention have been developed.

[0068] According to an exemplary embodiment, a nano-coated structure may be used for component carrier technology, in particular as a dry-adhesive structure. An adhesive layer implementing such a surface configuration may also be denoted as gecko film. The adhesive effect of such a surface may be based on van der Waals forces. Descriptively speaking, a plurality of low dimensioned suction cups may be formed by such a concept. According to an exemplary embodiment of the invention, a reliable substrate and/or structured material is provided for embedding and/or surface mounting applications having specific adhesion properties due to a corresponding configuration of nano- and/or microstructures on this surface. Exemplary embodiments have the advantage that the mentioned adjustability of the surface adhesion properties may be obtained with low material consumption, low production costs, small contamination risk, and high process reliability.

[0069] In an embodiment, the mentioned materials may be used as support for component placement in embedding technologies. Compared to a traditional adhesive tape system that is depending on temperature and time, an exemplary embodiment uses the surface of a support (which may be rigid or flexible) or a PCB elements (such as cores, prepregs, copper foils, etc.), that exhibits, thanks to the nano- and/or microstructures, van der Waals attraction forces, a gecko effect, a high grip, and that is dry and thus can be cleaned and reused. A sheet with nano- and/or microstructures can also be included in the final product. When used for an embedding concept, components may be placed on the dry surface and can be held in position by weak bonds (like van der Waals forces, gecko effect, high grip values) prior to the component lamination.

[0070] Such an architecture allows to obtain a dry interaction between the component and the holding substrate. No additional liquid adhesive is required. This has the advantages of a dry interaction, and a reduction of risk of contamination from the substrate.

[0071] FIG. 1 illustrates a cross-sectional view of a preform of a component carrier 1 being presently under manufacture according to an exemplary embodiment of the invention.

[0072] The component carrier 1 comprises a base structure 5 having a cavity 4, and a cluster 2, 3 comprising a first component 2 stacked and connected with a second component 3, wherein the cluster 2, 3 is arranged in the cavity 4. The cluster 2, 3 may have a height larger than 200 m.

[0073] In addition, the component carrier 1 can further comprise a passive component in the cavity 4.

[0074] The first component 2 and the second component 3 can be an active component, in particular a semiconductor chip. For example, one of the first and second components 2, 3 can be a processor chip, while the other one of the first and second components 2, 3 can be a memory chip. The first component 2 and the second component 3 can be connected on a wafer level. A main surface of the first component 2 is in alignment with one main surface of the second component 3 within the cluster 2, 3. An angle between a main surface of the first component 2 and an opposing main surface of the second component 3, at which main surfaces the first component 2 and the second component 3 are connected, is less than 10, in particular is less than 5. A height difference between opposing lateral sidewalls of the cluster 2, 3 is less than 15 m, particularly less than 5 m. If the first component 2 and the second component 3 are connected on wafer level, the height difference between opposing lateral sidewalls of the cluster 2, 3 can be less than 1 m, particularly less than 500 nm, more particularly less than 100 nm.

[0075] Although not visible in FIG. 1, the first component 2 may have another height than the second component 3.

[0076] The first component 2 has three pads 6 face up and the second component 3 has two pads 7 face down.

[0077] The cluster 2, 3 comprising the first component 2 and the second component 3 and the passive component, if any, is encapsulated in a common encapsulant 8. The encapsulant 8 is a mold compound. Alternatively, the base structure 5 and the cluster 2, 3 can be connected by a filling medium 11 (cf. FIG. 2), in particular by at least one of an adhesive and an at least partially uncured layer structure.

[0078] A direct electric connection is established between the first component 2 and the second component 3. Further, a direct electric connection is also established between the first component 2 and an electrically conductive layer structure 10 of the base structure 5.

[0079] FIG. 2 illustrates a method of manufacturing a component carrier 1 according to an embodiment of the invention.

[0080] In a step S21, a temporary carrier 12 is connected to a base structure 5 having vias 9. Then, a cavity 4 is formed into the base structure 5.

[0081] In a step S22, a cluster 2, 3 is inserted into the cavity 4. The cluster 2, 3 has been prepared beforehand by stacking and connecting a first component 2 and a second component 3 to one another to form the cluster 2, 3. Because of inserting the cluster 2, 3 into the cavity 4 after having stacked and connected the first component 2 and the second component 3 to one another, a height difference between opposing lateral sidewalls of the cluster 2, 3 can be controlled before the same is inserted into the cavity 4. As a result, the planarity of the component carrier 1 can be improved and warpage can be avoided.

[0082] The first component 2 and the second component 3 are semiconductor chips, and they are connected on a wafer level so that the manufacturing process is facilitated. That means that a first wafer comprising a plurality of first components 2 is connected to a second wafer comprising a plurality of second components 3. After having connected both wafers, the first and second components 2, 3 are singularized to obtain the cluster 2, 3.

[0083] In the present embodiment, the first component 2 has been coupled to the second component 3 by means of an adhesive. By the use of the adhesive, possible height differences of the opposing lateral sidewalls of the cluster 2, 3 can be controlled or compensated for. One main surface of the first component 2 is in alignment with one main surface of the second component 3 within the cluster 2, 3. The first component 2 has been provided with three pads 6 face up, and the second component 3 has been provided with two pads 7 face down, as shown in FIG. 1. The cluster 2, 3 may have a height larger than 200 m.

[0084] Although not visible in the figures, the first component 2 may have another height than the second component 3, and an angle between a main surface of the first component 2 and an opposing main surface of the second component 3, at which main surfaces the first component 2 and the second component 3 are connected, is less than 10, in particular less than 5.

[0085] It is possible that at least one passive component is additionally inserted in the cavity 4. The passive component can be connected to the cluster 2, 3 before the same is inserted into the cavity 4. However, the passive component and the cluster 2, 3 can also separately be inserted into the cavity 4.

[0086] In a step S23, the base structure 5 and the cluster 2, 3 are connected by a filling medium 11. The filling medium 11 can be an adhesive or a partially uncured layer structure. In the step S23, the filling medium 11 covers upper surfaces of the base structure 5 and the cluster 2, 3.

[0087] In a step S24, after having connected the base structure 5 and the cluster 2, 3, the temporary carrier 12 is removed or detaped. The filling medium 11 is then applied on the backside of the stack so that the filling medium 11 covers bottom surfaces of the base structure 5 and the cluster 2, 3.

[0088] In steps S25 through S28, the filling medium 11 is patterned to provide vias 17 therein, and further layers of electrically conductive materials and electrically insulating materials are built-up onto the so far manufactured stack of the component carrier 1. After having connected the base structure 5 and the cluster 2, 3, the pads 6, 7 of the first component 2 and the second component 3 are electrically connected to an electrically conductive layer structure 10 of the component carrier 1. In particular, not only the filling medium 11 but also the layers of electrically insulating material are patterned to form the vias 17 therein. The vias 17 are part of the electrically conductive layer structure 10. A direct electric connection is established between the first component 2 and the electrically conductive layer structure 10 of the base structure 5. A direct electric connection can also be established between the first component 2 and the second component 3. Several vias 17 can be bridged by at least one layer of electrically conductive material.

[0089] In the step S28, the component carrier 1 is further provided with soldering or bonding points 15. Such soldering or bonding points 15 can be bumps which are adapted to a flip-chip connection with other chips, which is described later. The soldering or bonding points 15 can be confined by a solder resist layer 19.

[0090] FIG. 3 illustrates a method of manufacturing a component carrier 1 according to another embodiment of the invention.

[0091] In a step S31, a temporary carrier 12 is connected to a base structure 5 having vias 9. Then, a cavity 4 is formed into the base structure 5.

[0092] In a step S32, a cluster 2, 3 is inserted into the cavity 4. The cluster 2, 3 has been prepared beforehand by stacking and connecting a first component 2 and a second component 3 to one another to form a cluster 2, 3. The first component 2 and the second component 3 are semiconductor chips, and they are connected on wafer level. In the present embodiment, the first component 2 has been coupled to the second component 3 by means of an adhesive. One main surface of the first component 2 is in alignment with one main surface of the second component 3 within the cluster 2, 3. The first component 2 has been provided with three pads 6 face up, and the second component 3 has been provided with two pads 7 face down.

[0093] Although not visible in the figures, the first component 2 has another height than the second component 3, and an angle between a main surface of the first component 2 and an opposing main surface of the second component 3, at which main surfaces the first component 2 and the second component 3 are connected, is less than 10, in particular less than 5.

[0094] It is possible that at least one passive component is additionally inserted in the cavity 4.

[0095] In a step S33, the cluster 2, 3 comprising the first component 2 and the second component 3 is encapsulated in a common encapsulant 8, which is carried out as molding. In a first sub step, the upper part of the so far manufactured stack is molded. In a second sub step, the temporary carrier 12 is removed. In an optional third sub step, the bottom part of the so far manufactured stack is molded. Instead of the third sub step, bridges 14 can be formed between the electrically conductive layer structure 10 of the base structure 5 and the pads 7 of the second component 3.

[0096] Anyway in step S33, the encapsulant 8 can be patterned to form bridges 14 between the electrically conductive layer structure 10 of the base structure 5 and the pads 6, 7 of the first and second components 2, 3, and/or between the vias 9 and the pads 6, 7 of the first and second components 2, 3. The bridges 14 comprise at least one horizontal portion and two vertical portions. The bridges 14 may comprise only the horizontal portion.

[0097] In a step S34, a layer 15 of an electrically insulating material is applied on both sides of the encapsulant 8, thereby embedding the bridges 14.

[0098] In steps S35 through S38, the layer 15 of an electrically insulating material is patterned to form vias 17 therein. Further layers of electrically conductive material and layers of electrically insulating material are built-up onto the so far manufactured stack of the component carrier 1. After having connected the base structure 5 and the cluster 2, 3, the pads 6, 7 of the first component 2 and the second component 3 are electrically connected to an electrically conductive layer structure 10 of the component carrier 1. In particular, the vias 17 are formed in the layers of electrically insulating material. Such vias 17 are connected to the layers of electrically conductive material and the bridges 14. A direct electric connection is thus established between the first component 2 and the electrically conductive layer structure 10 of the base structure 5. A direct electric connection can also be established between the first component 2 and the second component 3. The component carrier 1 is further provided with soldering or bonding points 15. Such soldering or bonding points 15 can be bumps which are adapted to a flip-chip connection with other chips, which is described later. The soldering or bonding points 15 can be confined by a solder resist layer 19.

[0099] FIG. 4 illustrates a cross-sectional view of a schematic preform of a component carrier according to an exemplary embodiment of the invention.

[0100] In this embodiment, only the cluster 2, 3, the base structure 5 and the temporary carrier 12 are depicted. The left-hand picture in FIG. 4 shows a component carrier according to the prior art, while the right-hand picture in FIG. 4 shows a component carrier 1 according to the present invention. The prior art component carrier includes a core 101 instead of a cluster. The height of the core 101 is usually less than 110 m. In contrast thereto, the height of the cluster 2, 3 of the component carrier 1 according to the present invention can be more than 200 m. Advantageously, the present invention enables an easier HVM process handling because of the thicker cluster 2, 3 (CCE core).

[0101] In the prior art, the core may be tilted within the cavity so that there is a remarkable height difference between opposing lateral sidewalls of the core. In contrast thereto, the cluster 2, 3 according to the present invention is inserted into the cavity after having stacked the first component 2 to the second component 3. Moreover, the adhesive between the first component 2 and the second component 3 can adjust and compensate for a possible height difference between opposing lateral sidewalls of the cluster 2, 3. As a result, the planarity of the component carrier 1 is improved, warpage is avoided and the height difference between opposing lateral sidewalls of the cluster 2, 3 is less than 15 m.

[0102] FIG. 5 illustrates a cross-sectional view of a schematic preform of a component carrier according to another exemplary embodiment of the invention. The first component 2 is a high-end chip, where face-up bonding is performed with the high-end chip 2. The second component 3 is a low-end chip, where face-down bonding is performed with the low-end chip 3. A high process capability for via to die pad alignment can be achieved. A first reference pad 21 is embedded in the filling medium 11 and exposed to the front side (upper side of the component carrier 1) through a through-hole which is formed in the filling medium 11. A second reference pad 22 is embedded in the filling medium 11 and exposed to the back side (bottom side of the component carrier 1) through a through-hole which is formed in the filling medium 11. The position of the first and second reference pads 21, 22 is measured, for example by optical (for example X-ray), inductive or capacitive detection. The first reference pad 21 is used for chip bonding and the formation of the vias at the front side. The second reference pad 22 is used for the formation of the vias at the back side.

[0103] FIG. 6 illustrates a cross-sectional view of a schematic preform of a component carrier according to another exemplary embodiment of the invention. Two chips 31, 32 are bonded at the front side of the component carrier 1, while two chips 33, 34 are bonded at the back side of the component carrier 1. Thereby, the component carrier 1 achieves a multi functionality by the stacked chips 31, 32, 33, 34, which progresses to FO-SiB (for example AP+Memory, AP+PMIC, etc.).

[0104] FIG. 7 illustrates a cross-sectional view of a schematic preform of a component carrier according to another exemplary embodiment of the invention. In this embodiment, only stacked chips 2, 3 are used to form a cluster.

[0105] FIG. 8 illustrates a cross-sectional view of a schematic preform of a component carrier according to another exemplary embodiment of the invention. In this embodiment, the cluster is formed by the first component 2, the second component 3 and a third component 41 which is arranged adjacent to the first component 2 and adhered onto the second component 3.

[0106] FIG. 9 illustrates a cross-sectional view of a schematic preform of a component carrier according to another exemplary embodiment of the invention. In this embodiment, the cluster is formed by the first component 2, the second component 3 and the third component 41 which is arranged adjacent to the first component 2 and adhered onto the second component 3. The second component 3 in turn comprises three chips 51, 52, 53 which are embedded in an encapsulant. The second component 3 is a so called cluster chip. Thus, the cluster in the embodiment comprises the stacked multi chips 2, 3, 41, wherein the cluster chip 3 formed by the chips 51, 52, 53.

[0107] FIG. 10 illustrates a cross-sectional view of a schematic preform of a component carrier according to another exemplary embodiment of the invention. In this embodiment, the cluster is formed by the first component 2 and the second component 3. The first component 2 comprises two chips 61, 62, which are embedded in a first encapsulant 81. The second component 3 comprises three chips 63, 64, 65 which are embedded in a second encapsulant 82. The first component 2 and the second component 3 are both so called cluster chips. Thus, the cluster in the embodiment comprises the cluster chip 2 formed by the chips 61, 62 and the cluster chip 3 formed by the chips 63, 64, 65. The cluster 2, 3 forms a stacked cluster chip.

[0108] In summary, the present invention achieves an optimized space of the embedded area, the component carrier 1 is flatter and less encapsulant material 8 flows in. The dimple amount of the encapsulant 8 can be reduced. Furthermore, the planarity of the component carrier 1 is improved, i.e. it has a flatter surface without image transfer/undulations.

[0109] It should be noted that the term comprising does not exclude other elements or steps and the article a or an does not exclude a plurality. Also, elements described in association with different embodiments may be combined.

[0110] Implementation of the invention is not limited to the preferred embodiments shown in the figures and described above. Instead, a multiplicity of variants are possible which use the solutions shown and the principle according to the invention even in the case of fundamentally different embodiments.

[0111] The present invention is particularly applicable for FO-PLPs for mobile phones and related to electronic devices.