A semiconductor device includes a substrate, a conductive part, a controller module and a sealing resin. The substrate has a substrate obverse surface and a substrate reverse surface facing away from each other in a z direction. The conductive part is made of an electrically conductive material on the substrate obverse surface. The controller module is disposed on the substrate obverse surface and electrically connected to the conductive part. The sealing resin covers the controller module and at least a portion of the substrate. The conductive part includes an overlapping wiring trace having an overlapping portion overlapping with the electronic component as viewed in the z direction. The overlapping portion of the overlapping wiring trace is not electrically bonded to the controller module.

A semiconductor device includes a substrate, a conductive part, a controller module and a sealing resin. The substrate has a substrate obverse surface and a substrate reverse surface facing away from each other in a z direction. The conductive part is made of an electrically conductive material on the substrate obverse surface. The controller module is disposed on the substrate obverse surface and electrically connected to the conductive part. The sealing resin covers the controller module and at least a portion of the substrate. The conductive part includes an overlapping wiring trace having an overlapping portion overlapping with the electronic component as viewed in the z direction. The overlapping portion of the overlapping wiring trace is not electrically bonded to the controller module.

A package that includes a second redistribution portion, a die coupled to the second redistribution portion, an encapsulation layer encapsulating the die, and a first redistribution portion coupled to the second redistribution portion. The first redistribution portion is located laterally to the die. The first redistribution portion is located over the second redistribution portion. The first redistribution portion and the second redistribution portion are configured to provide one or more electrical paths for the die.

A package that includes a second redistribution portion, a die coupled to the second redistribution portion, an encapsulation layer encapsulating the die, and a first redistribution portion coupled to the second redistribution portion. The first redistribution portion is located laterally to the die. The first redistribution portion is located over the second redistribution portion. The first redistribution portion and the second redistribution portion are configured to provide one or more electrical paths for the die.

A method of fabricating an integrated fan-out package is provided. The method includes the following steps. An integrated circuit component is provided on a substrate. An insulating encapsulation is formed on the substrate to encapsulate sidewalls of the integrated circuit component. A redistribution circuit structure is formed along a build-up direction on the integrated circuit component and the insulating encapsulation. The formation of the redistribution circuit structure includes the following steps. A dielectric layer and a plurality of conductive vias embedded in the dielectric layer are formed, wherein a lateral dimension of each of the conductive vias decreases along the build-up direction. A plurality of conductive wirings is formed on the plurality of conductive vias and the dielectric layer. An integrated fan-out package of the same is also provided.

A method of fabricating an integrated fan-out package is provided. The method includes the following steps. An integrated circuit component is provided on a substrate. An insulating encapsulation is formed on the substrate to encapsulate sidewalls of the integrated circuit component. A redistribution circuit structure is formed along a build-up direction on the integrated circuit component and the insulating encapsulation. The formation of the redistribution circuit structure includes the following steps. A dielectric layer and a plurality of conductive vias embedded in the dielectric layer are formed, wherein a lateral dimension of each of the conductive vias decreases along the build-up direction. A plurality of conductive wirings is formed on the plurality of conductive vias and the dielectric layer. An integrated fan-out package of the same is also provided.

An embodiment of the present invention is an IC chip mounting apparatus includes: a conveyor configured to convey an antenna continuous body on a conveying surface, the antenna continuous body having a base material and plural inlay antennas continuously formed on the base material, the antenna continuous body having an adhesive and an IC chip placed at a reference position of each of the antennas; a measurement unit configured to measure an interval between adjacent two of the antennas of the antenna continuous body; a press unit moving machine configured to sequentially feed out press units each having a pressing surface, from a waiting position, to move each of the press units along the conveying surface; and a controller configured to control timing of feeding out each of the press units from the waiting position based on the interval measured by the measurement unit, so that the pressing surface of each of the press units presses a predetermined region containing the reference position of each of the antennas on the conveying surface.

An embodiment of the present invention is an IC chip mounting apparatus includes: a conveyor configured to convey an antenna continuous body on a conveying surface, the antenna continuous body having a base material and plural inlay antennas continuously formed on the base material, the antenna continuous body having an adhesive and an IC chip placed at a reference position of each of the antennas; a measurement unit configured to measure an interval between adjacent two of the antennas of the antenna continuous body; a press unit moving machine configured to sequentially feed out press units each having a pressing surface, from a waiting position, to move each of the press units along the conveying surface; and a controller configured to control timing of feeding out each of the press units from the waiting position based on the interval measured by the measurement unit, so that the pressing surface of each of the press units presses a predetermined region containing the reference position of each of the antennas on the conveying surface.

A semiconductor device includes a semiconductor die, an electrical contact arranged on a surface of the semiconductor die, and a metal layer arranged on the electrical contact, wherein the metal layer includes a singulated part of at least one of a metal foil, a metal sheet, a metal leadframe, or a metal plate. When viewed in a direction perpendicular to the surface of the semiconductor die, a footprint of the electrical contact and a footprint of the metal layer are substantially congruent.

A semiconductor device includes a semiconductor die, an electrical contact arranged on a surface of the semiconductor die, and a metal layer arranged on the electrical contact, wherein the metal layer includes a singulated part of at least one of a metal foil, a metal sheet, a metal leadframe, or a metal plate. When viewed in a direction perpendicular to the surface of the semiconductor die, a footprint of the electrical contact and a footprint of the metal layer are substantially congruent.