SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT

Abstract

A semiconductor component may have a semiconductor body, an electrically conductive carrier layer, and an electrically poorly conductive insulation. The semiconductor body may include a first semiconductor layer and a second semiconductor layer, a first main face and a second main face, situated opposite the first main face, wherein the first main face is formed by a surface of the first semiconductor layer and the second main face is formed by a surface of the second semiconductor layer. The electrically conductive carrier layer may regionally cover the second main face the carrier layer is structured in such a way that it has at least one contact-free depression. The insulation may be located between the carrier layer and the semiconductor body and covers at least part of the second main face and extends up to at least one lateral face of the semiconductor body.

Claims

1. A semiconductor component comprising: a semiconductor body having: a first semiconductor layer and a second semiconductor layer; a first main face and a second main face (2B), opposite from the first main face, the first main face being formed by a surface of the first semiconductor layer and the second main face being formed by a surface of the second semiconductor layer; at least one side face joining the first main face to the second main face; an electrically conducting carrier layer covering the second main face at least in certain regions; and an electrically weakly conducting insulation; which is arranged between the carrier layer and the semiconductor body; covers the second main face at least in certain regions and extends to at least one side face of the semiconductor body; and has a first insulating layer and a second insulating layer, the second insulating layer being arranged on a side of the first insulating layer that is facing away from the semiconductor body and the first and second insulating layers differing from one another in their stiffness and/or elasticity, wherein the second insulating layer has a structuring in such a way that at least one cavity is formed between the electrically weakly conducting insulation and the electrically conducting carrier layer and/or the first insulating layer has a structuring in such a way that at least one cavity is formed between the semiconductor body and the electrically conducting carrier layer.

2. (canceled)

3. (canceled)

4. The semiconductor component as claimed in claim 1, wherein the cavity extends from a first main face of the semiconductor component, along at least one side face of the semiconductor body, in the direction of the second main face of the semiconductor body.

5. The semiconductor component as claimed in claim 1, wherein the electrically weakly conducting insulation extends from the second main face to at least one side face of the first semiconductor layer, and at least one side face of the second semiconductor layer being completely covered by the electrically weakly conducting insulation.

6. The semiconductor component as claimed in claim 1, wherein the electrically weakly conducting insulation being conformally covered by the electrically conducting carrier layer.

7. The semiconductor component as claimed in claim 1, wherein at least one side face of the semiconductor component being formed in certain regions by a side face of the first and/or second insulating layer.

8. The semiconductor component as claimed in claim 1, wherein the electrically weakly conducting insulation extending to a first main face of the semiconductor component.

9. The semiconductor component as claimed in claim 1, wherein the first insulating layer and the second insulating layer are formed from different materials.

10. The semiconductor component as claimed in claim 1, wherein the first insulating layer and the second insulating layer are formed from materials comprising Si.

11. The semiconductor component as claimed in claim 1, wherein the semiconductor body has at least one first recess, which extends from the second main face in the direction of the first main face and ends in the first semiconductor layer, the electrically conducting carrier layer being arranged in the first recess and serving for the electrical contacting of the first semiconductor layer.

12. The semiconductor component as claimed claim 1, wherein a surface of the semiconductor body that peripherally delimits the first recess is covered by the electrically weakly conducting insulation.

13. The semiconductor component as claimed in claim 1, wherein the carrier layer has at least one second recess, in which a terminal contact that serves for the electrical contacting of the second semiconductor layer is arranged.

14. The semiconductor component as claimed in claim 13, wherein a surface of the carrier layer that peripherally delimits the second recess is covered by a further insulating layer, which adjoins the electrically weakly conducting insulation.

15. The semiconductor component as claimed in claim 1, further comprising a molded-on main body, which is arranged on the semiconductor body, the electrically conducting carrier layer being arranged in the vertical direction between the semiconductor body and the main body.

16. A method for producing a semiconductor component as claimed in claim 1, wherein the method comprises: providing a semiconductor body having a first semiconductor layer and a second semiconductor layer; a first main face and a second main face, opposite from the first main face, the first main face being formed by a surface of the first semiconductor layer and the second main face being formed by a surface of the second semiconductor layer; at least one side face joining the first main face to the second main face; applying an electrically weakly conducting insulation to the second main face, the electrically weakly conducting insulation covering the second main face at least in certain regions and extending to at least one side face of the semiconductor body; and having a first insulating layer and a second insulating layer, the second insulating layer being arranged on a side of the first insulating layer that is facing away from the semiconductor body and the first and second insulating layers differing from one another in their stiffness and/or elasticity, and wherein the second insulating layer has a structuring in such a way that at least one cavity is formed between the electrically weakly conducting insulation and the electrically conducting carrier layer and/or the first insulating layer has a structuring in such a way that at least one cavity is formed between the semiconductor body and the electrically conducting carrier layer; applying an electrically conducting carrier layer to the electrically weakly conducting insulation.

17. (canceled)

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the illumination apparatus. In the following description, various aspects are described with reference to the following drawings, in which:

[0054] FIG. 1A shows a schematic plan view and FIG. 1B shows a schematic cross-sectional view of a method step and of a semiconductor component in an intermediate stage of a method according to an embodiment,

[0055] FIG. 2A shows a schematic plan view and FIG. 2B shows a further schematic cross-sectional view of the same method step and of the same semiconductor component in the intermediate stage of the method according to the previous embodiment,

[0056] FIG. 3 shows a schematic cross-sectional view of a method step and of a semiconductor component in a final stage of a method according to a first embodiment,

[0057] FIG. 4 shows a schematic cross-sectional view of a method step and of a semiconductor component in a final stage of a method according to a second embodiment,

[0058] FIG. 5 shows a schematic cross-sectional view of a method step and of a semiconductor component in a final stage of a method according to a third embodiment,

[0059] FIG. 6 shows a schematic cross-sectional view of a method step and of a semiconductor component in a final stage of a method according to a fourth embodiment,

[0060] FIG. 7 shows a schematic cross-sectional view of a method step and of a wafer assemblage and a main body assemblage in an intermediate stage of a method according to an embodiment,

[0061] FIG. 8 shows a comparative example of a semiconductor component in a schematic cross-sectional view,

[0062] FIG. 9 shows an FIB (known as a focused ion beam) micrograph of a semiconductor component according to a comparative example.

DETAILED DESCRIPTION

[0063] FIGS. 1A and 1B illustrate an intermediate stage of a method for producing a semiconductor component 1 and an intermediate stage of a semiconductor component 1 described in the present case. FIG. 1A shows the unfinished semiconductor component 1 in a plan view of a second main face 2B of the semiconductor body 2. FIG. 1B shows a cross section of the unfinished semiconductor component 1 along the line AA represented in FIG. 1A.

[0064] The unfinished semiconductor component 1 includes a semiconductor body 2 with a first semiconductor layer 3, a second semiconductor layer 4 and a growth substrate 3A, on which the first and second semiconductor layers 3, 4 are arranged. Furthermore, the semiconductor body 2 has a first main face 2A and a second main face 2B, opposite from the first main face 2A, the first main face 2A being formed by a surface of the first semiconductor layer 3 and the second main face 2B being formed by a surface of the second semiconductor layer 4. In addition, the semiconductor body 2 has multiple side faces 2C, 2D, which join the first main face 2A to the second main face 2B. In particular, the first main face 2A and the second main face 2B delimit the semiconductor body 2 in the finished semiconductor component (cf. FIG. 3) in a vertical direction V, while the side faces 2C, 2D delimit the semiconductor body 2 in lateral directions L. The lateral directions L in this case run transversely, in particular perpendicularly, to the vertical direction V. The side faces 2C, 2D may be made up in each case of multiple sub-faces, in particular the individual sub-faces being in each case planar surfaces and the surface normals of two sub-faces that are adjacent to one another running transversely, that is to say not parallel, to one another.

[0065] Between the first semiconductor layer 3 and the second semiconductor layer 4, the semiconductor body 2 has an active zone 5, which is intended for radiation generation. In particular, the active zone 5 is a p-n junction zone. The active zone 5 may in this case be formed as one layer or as a series of multiple layers.

[0066] The first semiconductor layer 3 may have a first conductivity and the second semiconductor layer 4 may have a second conductivity. In a non-limiting embodiment, the first semiconductor layer 3 is an n-conducting layer. Furthermore, the second semiconductor layer 4 is in particular a p-conducting layer.

[0067] Materials based on nitride-compound semiconductors come into consideration for the layers of the semiconductor body 2.

[0068] The semiconductor component 1 includes an electrically conducting carrier layer 8, which covers the second main face 2B and the side faces 2C, 2D of the semiconductor body 2 at least in certain regions. In this case, the carrier layer 8 extends from the second main face 2B over side faces of the second semiconductor layer 4 to side faces of the first semiconductor layer 3. For example, Au, Zn, Al, Sn, Ni and Cu or compounds of these materials, such as for example AuSn and NiAu and additionally NiPdAu, come into consideration for the carrier layer 8. The carrier layer 8 may contain at least one of these materials or consist of one of these materials. The carrier layer 8 is in particular a galvanic layer, which is galvanically deposited on a starting layer 7 arranged on the semiconductor body 2. For example, the starting layer 7 may contain one of the materials Au, Ti, Cu, Al, Ag, Sn, Rh, Ni or Pt or consist of one of these materials. Because of its nature, for example its thickness and/or its material, the carrier layer 8 is a stabilizing component of the semiconductor component 1. The thickness D1 of the carrier layer 8 may be between 2 m and 100 m inclusive, in particular between 5 m and 30 m, between 5 m and 15 m, deviations from the values specified of up to 10% being tolerable.

[0069] Furthermore, the semiconductor component 1 has an electrically weakly conducting insulation 6, which is arranged between the carrier layer 8 and the semiconductor body 2. In this case, the second main face 2B is covered at least in certain regions by the insulation 6. Furthermore, the insulation 6 extends from the second main face 2B along the side faces of the second semiconductor layer 4 to the side faces of the first semiconductor layer 3.

[0070] The insulation 6 is of a multilayer form, including a first insulating layer 61 and a second insulating layer 62. The second insulating layer 62 is arranged on a side of the first insulating layer 61 that is facing away from the semiconductor body 2. The first and second insulating layers 61 extend from the second main face 2B over side faces of the second semiconductor layer 4 to side faces of the first semiconductor layer 3. For example, the first and second insulating layers 61, 62 are formed from materials containing Si. In a non-limiting embodiment, the first and second insulating layers are formed from different materials. The materials containing Si may be a stoichiometric or non-stoichiometric composition of silicon oxide or silicon nitride. Furthermore, materials containing Al, in particular a stoichiometric or non-stoichiometric composition of aluminum oxide, also come into consideration.

[0071] Between the insulation 6 and the semiconductor body 2, the semiconductor component 1 may have further layers. For example, a terminal layer 9, which directly adjoins the second semiconductor layer 4, may be provided. With preference, the terminal layer 9 is formed from an electrically conducting and highly reflective material. For example, the terminal layer 9 is an electrically conducting mirror layer. For example, the terminal layer 9 may contain Ag or consist thereof. However, it is also possible that the terminal layer 9 is formed from a transparent conducting oxide (transparent conductive oxides, TCO for short), such as for example zinc oxide.

[0072] Furthermore, a current spreading layer 10 may be arranged adjacent to the terminal layer 9. The current spreading layer 10 may be formed as a stack of layers including multiple metal layers. In particular, the current spreading layer 10 may include metals such as Pt, Au, Cu, Al, Ag, Sn, Rh and Ti.

[0073] In the case of the embodiment represented, the carrier layer 8 has a number of second recesses 12, in which a second terminal contact can in each case be arranged. In particular, the second recesses 12 extend in each case from a delimiting area 8A of the carrier layer 8 that is facing away from the semiconductor body 2 through the carrier layer 8 to a delimiting area 8B of the carrier layer 8 that is facing the semiconductor body 2. That is to say that the carrier layer 8 is completely penetrated in the vertical direction V by the second recess 12. Furthermore, the second recess 12 may continue into the insulation 6 and completely penetrate it (cf. FIG. 3).

[0074] FIG. 2B shows the intermediate stage described above of a method and of a semiconductor component 1 in another view, a cross section along the line BB that is represented in FIG. 2A being shown in FIG. 2B.

[0075] The semiconductor body 2 has a first recess 11, which extends from the second main face 2B in the direction of the first main face 2A and ends in the first semiconductor layer 3. The first recess 11 is surrounded in lateral directions L around the full periphery by the semiconductor body 2. As can be seen from FIG. 2A, the semiconductor body 2 has a plurality of such first recesses 11. In the first recess 11, the carrier layer 8 is arranged. This advantageously serves for the electrical contacting of the first semiconductor layer 3 from the side of the second main face 2B. For improved electrical contacting of the first semiconductor layer 3, a contact element 13 may be arranged in direct contact with it in the first recess 11.

[0076] A surface of the semiconductor body 2 that peripherally delimits the first recess 11 is covered by the insulation 6. The insulation 6 in this case extends from the second main face 2B of the semiconductor body 2 into the first recess 11. The carrier layer 8 arranged in the recess 11 is electrically insulated from the adjacent layers by the insulation 6 laterally surrounding it.

[0077] Between the intermediate stage, described in connection with FIGS. 1 and 2, and the final stage, represented in FIG. 3, of a method and of a semiconductor component 1, further method steps are performed.

[0078] On the one hand, a further insulating layer 14 is formed on a delimiting area 8A of the carrier layer 8 that is facing away from the semiconductor body 2, the insulating layer 14 extending into the recess 12. On the other hand, terminal contacts 15, 16 are formed. In this case, a further starting layer 17, which is in particular sputtered on or vapor-deposited, may serve as the seed layer for the terminal contacts 15, 16. In addition, a main body 18, into which the terminal contacts 15, 16 are embedded, is molded on. The main body 18 advantageously represents a further stabilizing component. The growth substrate 3A may be at least partially removed, so that the first main face 2A or a surface of the first semiconductor layer 3 is at least partially exposed. For the stripping away of the growth substrate 3A, a laser lifting process or an etching process comes into consideration for example.

[0079] FIG. 3 shows a finished semiconductor component 1 in a cross-sectional view along the line AA represented in FIG. 1A. The semiconductor component 1 is in particular an optoelectronic semiconductor component. The semiconductor component 1 is intended for the emission of radiation. In this case, during the operation of the semiconductor component 1 the active zone 5 can emit electromagnetic radiation, for instance in the visible, ultraviolet or infrared spectral range. In particular, the electromagnetic radiation is predominantly coupled out of the semiconductor component 1 at the first main face 2A.

[0080] The semiconductor component 1 has a first terminal contact 15 for the electrical contacting of the first semiconductor layer 3 and a second terminal contact 16 for the electrical contacting of the second semiconductor layer 4. In this case, the first terminal contact 15 is in electrical contact with the carrier layer 8. Furthermore, the second terminal contact 16 is arranged in the second recess 12 and extends in the vertical direction V through the carrier layer 8 and the insulation 6, the second terminal contact 16 being in electrical contact with the terminal layer 9. The second terminal contact 16 is electrically insulated from the carrier layer 8 by the further insulating layer 14 arranged in the recess 12. The further insulating layer 14 may be formed from an electrically insulating material, such as silicon oxide and/or silicon nitride.

[0081] Furthermore, the semiconductor component 1 has a molded-on main body 18, which is arranged on the semiconductor body 2. In the vertical direction V, the insulation 6 and the carrier layer 8 are arranged between the semiconductor body 2 and the main body 18. The first and second terminal contacts 15, 16 extend from the side of the semiconductor body 2 through the main body 18 to a surface 18A of the main body 18 which is arranged on a side of the main body 18 that is facing away from the semiconductor body 2. The terminal contacts 15, 16 are enclosed in lateral directions L around the full periphery by the main body 18.

[0082] In the case of the embodiment represented, side faces 1A, 1B of the semiconductor component 1 are formed in certain regions by side faces of the carrier layer 8 and of the insulation 6. In this case, both side faces of the first insulating layer 61 and side faces of the second insulating layer 62 form part of the side faces 1A, 1B of the semiconductor component 1. The semiconductor component 1 is therefore partially delimited in lateral directions L by side faces of both insulating layers 61, 62. Furthermore, the first insulating layer 61 extends to the first main face 2A of the semiconductor component 1, so that the first main face 2A of the semiconductor component 1 is formed in certain regions by a surface of the first insulating layer 61.

[0083] The two insulating layers 61 and 62 may be formed from different materials and have different elasticities. The second insulating layer 62 advantageously has a greater elasticity than the first insulating layer 61. As a result, the second insulating layer 62 is more easily deformable than the first insulating layer 61, so that stresses that occur for example during the assembly or production of the semiconductor component 1 can be reduced better by means of the second insulating layer 62 than by the first insulating layer 61. However, it is also possible that the second insulating layer 62 is more rigid, that is to say in particular is formed with a lower elasticity, than the first insulating layer 61, so that the second insulating layer 62 serves as a predetermined breaking point. Overall, mechanical loads in the semiconductor component 1 can therefore be specifically reduced by the second insulating layer 62. In this case, it proves to be advantageous that the second insulating layer 62 is arranged close to the less flexible carrier layer 8, and consequently can compensate for stresses occurring in the region of the carrier layer 8.

[0084] FIG. 4 illustrates a final stage of a method for producing a semiconductor component 1 and a semiconductor component 1 according to a second embodiment.

[0085] The semiconductor component 1 includes a semiconductor body 2 as well as a carrier layer 8, arranged on the semiconductor body 2, and a main body 18, arranged on said carrier layer. Between the carrier layer 8 and the semiconductor body 2, the semiconductor component 1 has a terminal layer 9, a current spreading layer 10 and an insulation 6. The semiconductor body 2 and the further elements already mentioned in connection with the first embodiment have the aforementioned properties.

[0086] With regard to their structure, however, the insulation 6 according to the second embodiment differs from the first embodiment. In the case of the second embodiment, the side faces 1A, 1B of the semiconductor component 1 are formed in certain regions by side faces of the second insulating layer 62, but not by side faces of the first insulating layer 61. Furthermore, the second insulating layer 62 also extends to the first main face 2A, so that the first main face 2A of the semiconductor component 1 is formed in certain regions by surfaces of the first and second insulating layer 61, 62. In the case of the second embodiment, as a result of the region on the first main face 2A, the second insulating layer 62 has a larger exposed surface than in the case of the first embodiment, which further assists the deformability of the second insulating layer 62.

[0087] FIG. 5 illustrates a final stage of a method for producing a semiconductor component 1 or a semiconductor component 1 according to a third embodiment.

[0088] The semiconductor component 1 includes a semiconductor body 2 as well as a carrier layer 8, arranged on the semiconductor body 2, and a main body 18, arranged on said carrier layer.

[0089] Between the carrier layer 8 and the semiconductor body 2, the semiconductor component 1 has a terminal layer 9, a current spreading layer 10 and an insulation 6. The semiconductor body 2 and the further elements already mentioned in connection with the first embodiment have the aforementioned properties.

[0090] With regard to their structure, however, the insulation 6 according to the third embodiment differs from the first embodiment. In the case of the third embodiment, the side faces 1A, 1B of the semiconductor component 1 are formed in certain regions by side faces of the first insulating layer 61, but not by side faces of the second insulating layer 62. Furthermore, only the first insulating layer 61 extends to the first main face 2A of the semiconductor component 1, so that the first main face 2A of the semiconductor component 1 is formed in certain regions by a surface of the first insulating layer 61. Between the insulation 6 and the carrier layer 8 there is formed at least one cavity 19, in which the second insulating layer 62 is stripped away. That is to say that the cavity 19 is free of the second insulating layer 62. The cavity 19 may extend from the first main face 2A of the semiconductor component 1, along at least one side face 2C, 2D of the semiconductor body 2, in the direction of the second main face 2B of the semiconductor body 2. The cavity 19 may surround the semiconductor body 2 laterally around the full periphery. Alternatively, a number of cavities 19 may be provided in the second insulating layer 62, a region of the second insulating layer 62 being respectively arranged between two cavities 19. For example, the cavity 19 may have a thickness D2 of 50 nm to 2 m, between 100 nm and 500 nm. The thickness D2 of the cavity 19 may correspond to the layer thickness of the second insulating layer 62 or deviate from it by 10% to 50%. The size of the cavity 19 is set such that there is compensation for stresses.

[0091] The at least one cavity 19 allows the various layers in the semiconductor component 1 to have space for slight flexural distortions, without directly causing defects in the semiconductor component 1. In particular, the structuring of the second insulating layer 62, that is to say an altered geometrical shape of the second insulating layer 62, can have the effect that the stiffness of the second insulating layer 62 is reduced as compared to the first insulating layer 61, even when there is equally great elasticity.

[0092] FIG. 6 illustrates a final stage of a method for producing a semiconductor component 1 or a semiconductor component 1 according to a fourth embodiment.

[0093] With regard to its structure, the insulation 6 according to the fourth embodiment differs from the third embodiment. In the case of the fourth embodiment, the side faces 1A, 1B of the semiconductor component 1 are formed in certain regions by side faces of the second insulating layer 62, but not by side faces of the first insulating layer 61. Furthermore, only the second insulating layer 62 extends to the first main face 2A of the semiconductor component 1, so that the first main face 2A of the semiconductor component 1 is formed in certain regions by a surface of the second insulating layer 62. Between the semiconductor body 2 and the carrier layer 8 there is formed at least one cavity 19, in which the first insulating layer 61 is stripped away. That is to say that the cavity 19 is free of the first insulating layer 61. The cavity 19 may extend from the first main face 2A of the semiconductor component 1, along at least one side face 2C, 2D of the semiconductor body 2, in the direction of the second main face 2B of the semiconductor body 2. The cavity 19 may surround the semiconductor body 2 laterally around the full periphery. Alternatively, a number of cavities 19 may be provided in the first insulating layer 61, a region of the first insulating layer 61 being respectively arranged between two cavities 19. For example, the cavity 19 may have a thickness D2 of 50 nm to 2 m, between 100 nm and 500 nm. The thickness D2 of the cavity 19 may correspond to the layer thickness of the first insulating layer 61 or deviate from it by 10% to 50%. The size of the cavity 19 is set such that there is compensation for stresses.

[0094] The at least one cavity 19 allows the various layers in the semiconductor component 1 to have space for slight flexural distortions, without directly causing defects in the semiconductor component 1. In particular, the structuring of the first insulating layer 61, that is to say an altered geometrical shape of the first insulating layer 61, can have the effect that the stiffness of the first insulating layer 61 is reduced as compared to the second insulating layer 62, even when there is equally great elasticity.

[0095] FIG. 7 illustrates the production of a plurality of semiconductor components 1. This involves providing a wafer assemblage 20 having a molded-on main body assemblage 21, the wafer assemblage 20 having a plurality of semiconductor bodies 2 and a carrier layer 8, joining the semiconductor bodies 2, as well as a first insulating layer 61 and a second insulating layer 62, arranged between the semiconductor bodies 2 and the carrier layer 8. In addition, a number of separating trenches 22 are provided, along which the wafer assemblage 20 and the main body assemblage 21 can be separated into a plurality of semiconductor components 1. The first and second insulating layers 61, 62 extend into the separating trenches 22 and in the region of the separating trenches 22 are formed without any interruption.

[0096] For producing semiconductor components 1 according to the first embodiment, the first and second insulating layers 61, 62 are left without any interruption in the region of the separating trenches 22.

[0097] For producing semiconductor components 1 according to the second embodiment, the wafer assemblage 20 is worked further, the first insulating layer 61 on the first main face 2A being at least partially removed, so that the second insulating layer 62 appears (not represented in FIG. 7).

[0098] For producing semiconductor components 1 according to the third and fourth embodiments, the wafer assemblage 20 is likewise worked further in comparison with the stage represented in FIG. 7, stripping away of the second insulating layer 62 and of the first insulating layer 61 having the effect of creating cavities, which extend in each case from the first main face 2A, along at least one side face of a semiconductor body 2, in the direction of the second main face 2B.

[0099] FIG. 8 shows a comparative example of a semiconductor component 1, which as a difference from the semiconductor components 1 described in connection with FIGS. 3, 4, 5 and 6 does not have an insulation with insulating layers of different characteristics. As a consequence, because of the rigidity of the carrier layer 7, defects, for example cracks and delaminations, may occur in the course of production or assembly and impair the mechanical stability of the semiconductor component 1.

[0100] FIG. 9 shows in an FIB micrograph a detail of the cross section of a comparative example, as represented in FIG. 8, of a semiconductor component that has a largely homogeneous insulation. The semiconductor component 1 exhibits defects 23 in the further insulating layer 14, which can be prevented by means of an insulation as described in the present case.

[0101] The invention is not restricted by the description on the basis of the embodiments. Rather, the invention includes every novel feature and every combination of features, which includes in particular any combination of features in the patent claims, even if this feature or this combination itself is not explicitly specified in the patent claims or embodiments.

LIST OF REFERENCE SIGNS

[0102] 1 Semiconductor component [0103] 1A, 1B Side face [0104] 2 Semiconductor body [0105] 2A, 2A First main face [0106] 2B Second main face [0107] 2C, 2D Side face [0108] 3 First semiconductor layer [0109] 3A Growth substrate [0110] 4 Second semiconductor layer [0111] 5 Active zone [0112] 6 Insulation [0113] 61 First insulating layer [0114] 62 Second insulating layer [0115] 7, 17 Starting layer [0116] 8 Carrier layer [0117] 8A, 8B Delimiting area [0118] 9 Terminal layer [0119] 10 Current spreading layer [0120] 11 First recess [0121] 12 Second recess [0122] 13 Contact element [0123] 14 Insulating layer [0124] 15 First terminal contact [0125] 16 Second terminal contact [0126] 18 Main body [0127] 18A Surface [0128] 19 Cavity [0129] 20 Wafer assemblage [0130] 21 Main body assemblage [0131] 22 Separating trench [0132] 23 Defect [0133] D1, D2 Thickness [0134] V Vertical direction [0135] L Lateral directions