IMPLANTABLE DEVICE AND MANUFACTURING METHOD OF THE SAME

Abstract

Disclosed is an implantable device including: a first insulation layer; a second insulation layer arranged on the first insulation layer; a first semiconductor layer arranged between the first and second insulation layers; a second semiconductor layer doped into the first semiconductor layer, with the second semiconductor layer forming a closed loop as seen in a top view; a metal layer disposed on the second insulation layer, with the metal layer forming an electrode; a third insulation layer covering the metal layer; and an insulation region including the first and second semiconductor layers.

Claims

1. An implantable device comprising: a first insulation layer; a second insulation layer arranged on the first insulation layer; a first semiconductor layer arranged between the first and second insulation layers; a second semiconductor layer doped into the first semiconductor layer, with the second semiconductor layer forming a closed loop as seen in a top view; a metal layer disposed on the second insulation layer, with the metal layer forming an electrode; a third insulation layer covering the metal layer; and an insulation region including the first and second semiconductor layers.

2. The implantable device according to claim 1, wherein the metal layer is formed further inside the second semiconductor layer as seen in the top view.

3. The implantable device according to claim 1, further comprising: a device region arranged between insulation regions.

4. The implantable device according to claim 1, wherein the third insulation layer is removed to expose the electrode.

5. The implantable device according to claim 1, wherein the electrode is formed of platinum.

6. The implantable device according to claim 1, wherein at least one of the first, second or third insulation layer is SiO.sub.2.

7. The implantable device according to claim 1, wherein the first and second semiconductor layers have the same height as seen in a sectional view.

8. The implantable device according to claim 1, wherein the insulation region has both a diode and an inverse diode.

9. A manufacturing method of an implantable device, the method comprising: preparing a supporting substrate having a first insulation layer; arranging a first semiconductor layer on the first insulation layer; forming a second semiconductor layer within the first semiconductor layer to form a closed loop as seen in a top view; forming a second insulation layer within the first semiconductor layer; forming, on the second insulation layer, a metal layer having an electrode; forming a third insulation layer on the metal layer; and removing the supporting substrate.

10. The method according to claim 9, further comprising: prior to forming a second insulation layer on the first semiconductor layer, forming a device region inside the closed loop as seen in the top view.

11. The method according to claim 9, wherein in forming, on the second insulation layer, a metal layer having an electrode, the metal layer is formed inside the second insulation layer as seen in the top view.

12. The method according to claim 9, wherein in forming a third insulation layer on the metal layer, the third insulation layer is formed of a stack of multiple layers.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIGS. 1A and 1B illustrate an example of an optical probe LED chip module for bio stimulation and a manufacturing method of the same described in Korean Patent Application Publication No. 10-2013-0078956.

[0032] FIGS. 2A, 2B, 2C, 2D, 2E, 2F, 3A, 3B, 3C, 3D, 3E and 3F describe an exemplary CMOS process in the prior art.

[0033] FIGS. 4A and 4B illustrate an implantable biometric chip for checking vitals through a micro semiconductor chip inserted in the body, as described in Korean Patent Application Publication No. 10-2018-0069319.

[0034] FIGS. 5A and 5B illustrate an exemplary embodiment of an implantable device according to the present disclosure.

[0035] FIGS. 6A, 6B, 6C, 6D, 6E, 6F and 6G show an exemplary embodiment of a manufacturing method of an implantable device according to the present disclosure.

[0036] FIGS. 7A and 7B show another exemplary embodiment of a manufacturing method of an implantable device according to the present disclosure.

[0037] FIG. 8 shows another exemplary embodiment of a manufacturing method of an implantable device according to the present disclosure.

[0038] FIG. 9 shows another exemplary embodiment of a manufacturing method of an implantable device according to the present disclosure.

DETAILED DESCRIPTION

[0039] The present disclosure will now be described in detail with reference to the accompanying drawing(s).

[0040] FIGS. 5A and 5B illustrate an exemplary embodiment of an implantable device 100 according to the present disclosure.

[0041] FIG. 5A is a sectional view of the implantable device 100, and FIG. 5B is a top view with a second insulation layer 140 and a third insulation layer 160 being removed from FIG. 5A.

[0042] The implantable device 100 includes a first insulation layer 100, the second insulation layer 140, a first semiconductor layer 120, a second semiconductor layer 130, a metal layer 150 and the third insulation layer 160.

[0043] The first insulation layer 110 is disposed at the very bottom of the device 100. The first insulation layer 110 can be an oxide layer. For instance, the first insulation layer 110 can be SiO.sub.2. The second insulation layer 140 is arranged on the first insulation layer 110, and can be SiO.sub.2, for example.

[0044] The first semiconductor layer 120 is arranged between the first insulation layer 110 and the second insulation layer 140. The second semiconductor layer 130 is formed within the first semiconductor layer 120 in such a manner that the second semiconductor layer 130 forms a closed loop in the first semiconductor layer 120 as seen in the top view. The first semiconductor layer 120 and the second semiconductor layer 130 have the same height on the sectional view. The upper face of the first semiconductor layer 120 and the upper face of the second semiconductor layer 130 come in contact with the second insulation layer 140. The lower face of the first semiconductor layer 120 and the lower face of the second semiconductor layer 130 come in contact with the first insulation layer 110. The second insulation layer 140 can abut onto an insulation region 210. The first semiconductor layer 120 and the second semiconductor layer 130 may be present in the insulation region 210.

[0045] The metal layer 150 may be isolated from the isolation region 210. Also, the metal layer 150 may be in electrical communication with a device region 170.

[0046] The device 100 may further include an electrode 151 for external stimulation on the second insulation layer 140. As seen in the top view, the electrode 151 is located inside the closed loop. The electrode 151 is an exposed portion of the metal layer 150 by the third insulation layer 160. The metal layer 150 may be arranged in the device region 170 and connect elements therein. The exposed electrode 151 may be made of platinum. In particular, the metal layer 150 may be a stack of layers, with only the uppermost, exposed electrode 151 being formed of platinum. More details on the device region 170 will be provided later with reference to FIG. 7. The device region 170 can be present inside the closed loop, as seen in the top view.

[0047] The third insulation layer 160 covers the metal layer 150. The third insulation layer 160 may include at least one layer. Preferably, the third insulation layer 160 has a height of at least 1 m and not greater than 20 m. Further, the third insulation layer 160 is connected to the electrode 151 and may have a pad 180 for external stimulation. The pad 180 is electrically connected to the metal layer 150, passing through the third insulation layer 160. To this end, an electrical connection 154 may be arranged between the pad 180 and the metal layer 150. For instance, this electrical connection 154 may be formed of copper (Cu). The third insulation layer 160 may be SiO.sub.2. Preferably, the pad 180 is made of a material that does not react with body fluid. One example of such material is platinum.

[0048] The metal layer 150 can be obtained by the standard pad process in typical CMOS processes. If needed, however, the metal layer 150 can be made thinner.

[0049] As shown in FIG. 5, for example, if the first semiconductor layer 120 is p-type and the second semiconductor layer 130 is n-type, a PN junction is created between the first semiconductor layer 120 and the second semiconductor layer 130. As such, lateral faces of the first semiconductor layer 120 can be insulated. Without limiting to the example in FIG. 5, it is also possible that the first semiconductor layer 120 is n-type and the second semiconductor layer 130 is p-type. Still, the PN junction therebetween allows the corresponding semiconductor layer to withstand several tens of volts or even static electricity. Moreover, when diodes D.sub.1 and D.sub.2 are arranged facing each other as shown in FIG. 5 and voltage runs in reverse direction around the second semiconductor layer 130, current will not flow in any direction. Accordingly, the device region 170 is protected from an externally applied current.

[0050] FIG. 6A to FIG. 6G describe an exemplary embodiment of a manufacturing method of an implantable device 100 according to the present disclosure.

[0051] In order to manufacture the implantable device 100, a supporting substrate 111 having a first insulation layer 110 is prepared as shown in FIG. 6A. The supporting substrate 111 may be a silicon wafer, and the first insulation layer 110 may be an oxide layer obtained by oxidation of the silicon wafer.

[0052] Next, a first semiconductor layer 120 is arranged on the first insulation layer 110, as shown in FIG. 6B. The first semiconductor layer 120 can be bonded to the first insulation layer 110.

[0053] Referring now to FIG. 6C, a second semiconductor layer 130 is formed in the first semiconductor layer 120, forming a closed loop as seen in the top view. The second semiconductor layer 130 can be obtained by implanting impurities into the first semiconductor layer 120. Preferably, the second semiconductor layer 130 is formed within the first semiconductor layer 120 and serves to divide the first semiconductor layer 120 into inside and outside parts. Accordingly, in an insulation region 210, the first semiconductor layer 120 and the second semiconductor layer 130 are repeated at least once within the first semiconductor layer 120 and a PN junction is created to prevent electricity from flowing to a device region 170.

[0054] As shown in FIG. 6D, a second insulation layer 140 is then formed on the first semiconductor layer 120.

[0055] Referring next to FIG. 6E, a metal layer 150 including an electrode 151 is formed on the second insulation layer 140. For instance, the metal layer 150 may be adapted to connect elements in the device region 170.

[0056] A third insulation layer 160 is formed on the metal layer 150, as shown in FIG. 6F. Subsequent steps after the step shown in FIG. 6F in the process can be repeated multiple times. This will be described in further detail with reference to FIG. 8.

[0057] The steps shown in FIGS. 6E and 6F can be repeated several times even in general CMOS process. As such, a plurality of the metal layers 150 can be formed in-between the third insulation layer 160. However, since insulation of lateral faces of the device 100 degrades by an increasing number of the metal layer 150, it is not desirable to have a stack of multiple metal layers 150.

[0058] The supporting substrate 111 is removed, as shown in FIG. 6G. The supporting substrate 111 can be etched by an etching solution, for example.

[0059] FIGS. 7A and 7B show another exemplary embodiment of a manufacturing method of an implantable device according to the present disclosure.

[0060] The second insulation layer 140 is formed on the first semiconductor layer 120 as described above with reference to FIG. 6D. In this alternative embodiment, prior to the step in FIG. 6D, the device region 170 can be formed inside the closed loop as seen in the top view. The device region 170 can be designed for charging, communication, signal measurement or stimulation signaling of the implantable device 100. For example, since the implantable device 100 is insulated from outside, the device region 170 can be adapted to receive power and data wirelessly using a coil-form antenna, to wirelessly send data to an external device, to measure input electrical signals as well as types of light through a loop composed of photodiodes, and to stimulate cells through electric current, voltage or LED light.

[0061] FIG. 8 shows another exemplary embodiment of a manufacturing method of an implantable device according to the present disclosure.

[0062] In this alternative embodiment, the metal layer 150 is formed further inside than lateral faces 141 of the second insulation layer 140 in the step of FIG. 6E. That is to say, lateral faces 152 of the metal layer 150 are preferably not exposed to lateral faces 101 of the implantable device 100. Moreover, in the step of FIG. 6F, the third insulation layer 160 covers the metal layer 150 in such a way that an upper face 153 of the metal layer 150 is preferably not exposed but covered with the third insulation layer 160, while the electrode 151 of the metal layer 150 can be exposed.

[0063] The third insulation layer may be formed of a stack of multiple layers. This is done for better insulation from outside by multiplying the standard height used in typical CMOS processes. For instance, the third insulation layer 160 having a height of about 100 is usually formed at a time during the CMOS process. Alternatively, however, a plurality of third insulation layers 160 can be stacked, or the third insulation layer 160 having a micrometer thickness can be formed at a time.

[0064] FIG. 9 shows another exemplary embodiment of a manufacturing method of an implantable device according to the present disclosure.

[0065] In this alternative embodiment, in the step of FIG. 6F, the metal layer 150 is etched to expose its top face. Next, the pad 180 can be formed on the metal layer 150 and an electrical connection 154 may be arranged between the metal layer 150 and the pad 180 to electrically connect them, as shown in FIG. 9.

[0066] While FIG. 9 shows that the supporting substrate 111 is in a bonded state, the subsequent steps in FIG. 9 can still be conducted after the step of removing the supporting substrate 111 in FIG. 6G.

[0067] Set out below are a series of clauses that disclose features of further exemplary embodiments of the present disclosure, which may be claimed.

[0068] (1) An implantable device comprising: a first insulation layer; a second insulation layer arranged on the first insulation layer; a first semiconductor layer arranged between the first and second insulation layers; a second semiconductor layer doped into the first semiconductor layer, with the second semiconductor layer forming a closed loop as seen in a top view; a metal layer disposed on the second insulation layer, with the metal layer forming an electrode; a third insulation layer covering the metal layer; and an insulation region including the first and second semiconductor layers.

[0069] (2) There is also provided, the implantable device of clause (1) wherein: the metal layer is formed further inside the second semiconductor layer as seen in the top view.

[0070] (3) There is also provided, the implantable device of clause (1) further comprising: a device region arranged between insulation regions.

[0071] (4) There is also provided, the implantable device of clause (1) wherein: the third insulation layer is removed to expose the electrode.

[0072] (5) There is also provided, the implantable device of clause (1) wherein: the electrode is formed of platinum.

[0073] (6) There is also provided, the implantable device of clause (1) wherein: at least one of the first, second or third insulation layer is SiO.sub.2.

[0074] (7) There is also provided, the implantable device of clause (1) wherein: the first and second semiconductor layers have the same height as seen in a sectional view.

[0075] (8) There is also provided, the implantable device of clause (1) wherein: the insulation region has both a diode and an inverse diode.

[0076] (9) A manufacturing method of an implantable device, the method comprising: preparing a supporting substrate having a first insulation layer; arranging a first semiconductor layer on the first insulation layer; forming a second semiconductor layer within the first semiconductor layer to form a closed loop as seen in a top view; forming a second insulation layer within the first semiconductor layer; forming, on the second insulation layer, a metal layer having an electrode; forming a third insulation layer on the metal layer; and removing the supporting substrate.

[0077] (10) There is also provided, the manufacturing method of clause (9) further comprising: prior to forming a second insulation layer on the first semiconductor layer, forming a device region inside the closed loop as seen in the top view.

[0078] (11) There is also provided, the manufacturing method of clause (9) wherein: in forming, on the second insulation layer, a metal layer having an electrode, the metal layer is formed inside the second insulation layer as seen in the top view.

[0079] (12) There is also provided, the manufacturing method of clause (9) wherein: in forming a third insulation layer on the metal layer, the third insulation layer is formed of a stack of multiple layers.

[0080] The implantable device according to the present disclosure has an insulating function achieved in CMOS process.

[0081] The manufacturing method of an implantable device according to the present disclosure provides an insulating implantable device by forming the second semiconductor layer within the first semiconductor layer, instead of using a separate insulating material.