Area efficient floating field ring termination

Abstract

A high power semiconductor device with a floating field ring termination includes a wafer, wherein a plurality of floating field rings is formed in an edge termination region adjacent to a first main side surface of the wafer. At least in the termination region a drift layer, in which the floating field rings are formed, includes a surface layer and a bulk layer wherein the surface layer is formed adjacent to the first main side surface to separate the bulk layer from the first main side surface and has an average doping concentration which is less than 50% of the minimum doping concentration of the bulk layer. The drift layer includes a plurality of enhanced doping regions, wherein each one of the enhanced doping regions is in direct contact with a corresponding one of the floating field rings at least on a lateral side of this floating field ring, which faces towards the active region. The relatively low doped surface layer and the enhanced doping regions increase the electric field coupling from floating field ring to floating field ring, thus allowing an area efficient termination structure. Each enhanced doping region extends to at least the same depth as the one of the corresponding floating field ring.

Claims

1. A high power semiconductor device comprising a wafer (W), the wafer (W) having a first main side surface, a second main side surface, which is parallel to the first main side surface and extending in a lateral direction, an active region (AR) and a termination region (TR) laterally surrounding the active region (AR), wherein: the wafer (W)-comprises in the order from the first main side surface to the second main side surface: (a) a first semiconductor layer of a first conductivity type which is either n-type or p-type conductivity; (b) a second semiconductor layer of a second conductivity type which is different from the first conductivity type, wherein the second semiconductor layer is in direct contact with the first semiconductor layer to form a first pn-junction; and (c) a third semiconductor layer of the second conductivity type having a doping concentration higher than that of the second semiconductor layer, a first electrode is formed on the first main side surface to form a first contact with the first semiconductor layer, a second electrode is formed on the second main side surface to form a second contact, a plurality of floating field rings is formed in the termination region (TR) adjacent to the first main side surface of the wafer (W), wherein each one of the floating field rings is a first ring-shaped semiconductor region of the first conductivity type, which is laterally surrounding the active region (AR) and the first semiconductor layer and which forms a second pn-junction with the second semiconductor layer, and wherein the floating field rings are spaced from each other in the lateral direction and are separated from each other by the second semiconductor layer, in the termination region (TR) the second semiconductor layer comprises a surface layer and a bulk layer, wherein the surface layer is formed adjacent to the first main side surface and has an average doping concentration which is less than 50% of the minimum doping concentration of the bulk layer, wherein the second semiconductor layer comprising a plurality of enhanced doping regions, wherein: each one of the enhanced doping regions is formed in the termination region (TR) adjacent to the first main side surface of the wafer (W), and each one of the enhanced doping regions is a second ring-shaped semiconductor region of the second conductivity type, which is laterally surrounding the active region (AR)-and the first semiconductor layer, wherein each one of the enhanced doping regions is in direct contact with a corresponding one of the floating field rings at least on a lateral side of this floating field ring, which faces towards the active region (AR), each one of the enhanced doping regions has a peak doping concentration which is higher than the minimum doping concentration of the bulk layer, each one of the enhanced doping regions except an enhanced doping region next to the active region (AR) is separated by the surface layer from the next floating field region in a direction towards the active region (AR), the enhanced doping region next to the active region (AR is separated by the surface layer from the first semiconductor layer in a direction towards the active region (AR), and wherein each one of the enhanced doping regions extends from the first main side surface to a depth (d.sub.EDR; d.sub.EDR) which is at least the depth (d.sub.FFR) of the corresponding floating field ring.

2. The high power semiconductor device according to claim 1, wherein the average doping concentration of the surface layer is in a range between 10% and 50% of the minimum doping concentration of the bulk layer.

3. The high power semiconductor device according to claim 1, wherein the doping profile in a transition region at the interface between the surface layer and the bulk layer is step-like with a steep gradient of the doping concentration, which increases in the transition region by at least 100% from the surface layer to the bulk layer, wherein the transition region has a thickness of less than 0.1 m.

4. The high power semiconductor device according to claim 1, wherein the surface layer extends from the first main side surface to a depth (d.sub.SL) which is at least the same as a depth (d.sub.FFR) of the floating field rings.

5. The high power semiconductor device according to claim 1, wherein the surface layer extends from the first main side surface to a depth (d.sub.SL) which is more than the depth (d.sub.FFR) of the floating field rings, so that the floating field rings are embedded in the surface layer.

6. The high power semiconductor device according to claim 1, wherein the minimum doping concentration of the bulk layer is below 5.Math.10.sup.15 cm.sup.3.

7. The high power semiconductor device according to claim 1, wherein the peak doping concentration of each one of the enhanced doping regions is in a range between 1.Math.10.sup.16 cm.sup.3 and 1.Math.10.sup.18 cm.sup.3.

8. The high power semiconductor device according to claim 1, wherein each one of the enhanced doping regions envelops at least a part of a bottom surface of the corresponding floating field ring.

9. The high power semiconductor device according to claim 1, wherein each one of the enhanced doping regions has a lateral width (w.sub.EDR; W.sub.EDR) adjacent to the first main side surface, which is smaller than the lateral width (w.sub.FFR)of a neighbouring floating field ring adjacent to the first main side surface and which is, for each one of the enhanced doping regions except an enhanced doping region next to the active region, smaller than the distance between this enhanced doping region and the next floating field region separated from this enhanced doping region by the surface layer in a direction towards the active region, and which is, for the enhanced doping region next to the active region, smaller than the distance between this enhanced doping region and the first semiconductor layer separated from this enhanced doping region by the surface layer in the direction towards the active region (AR).

10. The high power semiconductor device according to claim 1, comprising a plurality of extension regions, each extension region being formed as a third ring-shaped semiconductor region of the first conductivity type having a peak doping concentration lower than that of the floating field rings, each one of extension regions being formed on the lateral side of a corresponding floating ring to surround the corresponding floating field ring and to be in direct contact with the corresponding floating field ring, each one of the extension regions extending from the first main side surface to a depth (d.sub.ER) which is deeper than the depth (d.sub.FFR) of the corresponding floating field ring.

11. The high power semiconductor device according to claim 1, wherein the first to third semiconductor layers and the floating field rings are made of silicon carbide.

12. The high power semiconductor device according to claim 1, wherein the surface layer separates the bulk layer from the first main side surface at least in an area between an innermost floating field ring and the active area and between each pair of neighbouring floating field rings.

13. The high power semiconductor device according to claim 1, wherein the average doping concentration of the surface layer is in a range between 20% and 40% of the minimum doping concentration of the bulk layer.

14. The high power semiconductor device according to claim 2, wherein the doping profile in a transition region at the interface between the surface layer and the bulk layer is step-like with a steep gradient of the doping concentration, which increases in the transition region by at least 100% from the surface layer to the bulk layer, wherein the transition region has a thickness of less than 0.1 m.

15. The high power semiconductor device according to claim 13, wherein the doping profile in a transition region at the interface between the surface layer and the bulk layer is step-like with a steep gradient of the doping concentration, which increases in the transition region by at least 100% from the surface layer to the bulk layer, wherein the transition region has a thickness of less than 0.1 m.

16. The high power semiconductor device according to claim 2, wherein the surface layer extends from the first main side surface to a depth (d.sub.SL) which is at least the same as a depth (d.sub.FFR) of the floating field rings.

17. The high power semiconductor device according to claim 3, wherein the surface layer extends from the first main side surface to a depth (d.sub.SL) which is at least the same as a depth (d.sub.FFR) of the floating field rings.

18. The high power semiconductor device according to claim 2, wherein the surface layer extends from the first main side surface to a depth (d.sub.SL) which is more than the depth (d.sub.FFR) of the floating field rings, so that the floating field rings are embedded in the surface layer.

19. The high power semiconductor device according to claim 3, wherein the surface layer extends from the first main side surface to a depth (d.sub.SL) which is more than the depth (d.sub.FFR) of the floating field rings, so that the floating field rings are embedded in the surface layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Detailed embodiments of the invention will be explained below with reference to the accompanying figures, in which:

(2) FIG. 1 is a partial cross-sectional view of a high power semiconductor device according to a first embodiment;

(3) FIG. 2 is an enlarged portion of the partial cross-sectional view of FIG. 1, wherein one of the plurality of floating field rings is shown in cross-section;

(4) FIG. 3 is a partial cross-sectional view of a high power semiconductor device according to a second embodiment, wherein one of a plurality of floating field rings is shown in cross-section;

(5) FIG. 4 is a partial cross-sectional view of a high power semiconductor device according to a third embodiment, wherein one of a plurality of floating field rings is shown in cross-section;

(6) FIG. 5 is a partial cross-sectional view of a high power semiconductor device according to a fourth embodiment, wherein one of a plurality of floating field rings is shown in cross-section;

(7) FIG. 6 is a partial cross-sectional view of a high power semiconductor device according to a fifth embodiment, wherein one of a plurality of floating field rings is shown in cross-section; and

(8) FIG. 7 is a partial cross-sectional view of a high power semiconductor device according to a sixth embodiment, wherein one of a plurality of floating field rings is shown in cross-section.

(9) The reference signs used in the figures and their meanings are summarized in the list of reference signs. Generally, similar elements have the same reference signs throughout the specification. The described embodiments are meant as examples and shall not limit the scope of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(10) FIG. 1 is a partial cross-sectional view of a high power semiconductor device 1 according to a first embodiment. The high power semiconductor device 1 is a silicon carbide (SiC) based pin diode. It comprises a 4H-SiC wafer W having a first main side surface 2 and a second main side surface 3, which is parallel to the first main side surface 2 and extending in a lateral direction. The wafer W has an active region AR and a termination region TR laterally surrounding the active region AR. In the order from the first main side surface 2 to the second main side surface 3, the wafer W comprises a p-doped anode layer 4 (first semiconductor layer in the claims), an n-doped drift layer 5 (second semiconductor layer in the claims), and an n.sup.+-doped substrate layer 6 (third semiconductor layer in the claims) having a doping concentration higher than that of the n-doped drift layer 5. Exemplarily the doping concentration of the substrate layer is 5.Math.10.sup.18 cm.sup.3 or more. The doping concentration of the anode layer 4 is exemplarily 5.Math.10.sup.16 cm.sup.3 or more. The drift layer 5 is in direct contact with the anode layer 4 to form a main pn-junction (first pn-junction in the claims). An anode electrode 7 (first electrode in the claims) is formed on the first main side surface 2 to form an ohmic contact with the anode layer 4. On the second main side surface 3 of the wafer W there is formed a cathode electrode 8 (second electrode in the claims) to form an ohmic contact with the substrate layer 6. Depending on the voltage class of the power semiconductor device the thickness of the drift layer 5 may exemplarily vary in a range between 30 to 400 m.

(11) A plurality of p.sup.+-doped floating field rings 10 (i.e. of the first conductivity type) is formed in the termination region TR adjacent to the first main side surface 2 of the wafer W. Each one of the floating field rings 10 is ring-shaped and laterally surrounds the active region AR and the anode layer 4. The field rings 10 are self-contained rings, which enclose in a plane parallel to the first main surface 2 the active region AR and such floating rings, which are arranged closer to the active region. Also, each floating field ring 10 is in direct contact with the drift layer 5 to form a pn-junction (second pn-junction in the claims). Exemplarily, the floating field rings 10 have a peak doping concentration in a range between 1.Math.10.sup.17 cm.sup.3 and 1.Math.10.sup.19 cm.sup.3, exemplarily between 1.Math.10.sup.18 cm.sup.3 and 1.Math.10.sup.19 cm.sup.3.

(12) As can be seen from FIG. 1, in the termination region TR the drift layer 5 comprises a surface layer 5a and a bulk layer 5b, wherein the surface layer 5a is formed adjacent to the first main side surface 2 of the wafer W to separate the bulk layer 5b from the first main side surface 2. Exemplarily the surface layer 5a separates the bulk layer 5b from the first main side surface 2 at least in an area between an innermost floating field ring and the anode layer 4, i.e. the active area AR, and between each pair of neighbouring floating field rings 10. The surface layer 5a differs from the bulk layer 5b in that it has a lower doping concentration than the bulk layer 5b. Specifically, the surface layer 5a has an average doping concentration which is less than 50% of the minimum doping concentration of the bulk layer 5b. Exemplarily, the average doping concentration of the surface layer 5a is less than 30% of the minimum doping concentration of the bulk layer 5b, more exemplarily less than 20% of the minimum doping concentration of the bulk layer 5b. Exemplarily the average doping concentration of the surface layer 5a may be in a range between 10% and 50% of the minimum doping concentration of the bulk layer 5b, more exemplarily in a range between 20% and 40%. The bulk layer 5b may have a minimum doping concentration of 1.Math.10.sup.16 cm.sup.3 or below, exemplarily of 5.Math.10.sup.15 cm.sup.3 or below, more exemplarily in a range between 1.Math.10.sup.14 cm.sup.3 and 1.Math.10.sup.16 cm.sup.3, and more exemplarily in a range between 5.Math.10.sup.14 cm.sup.3 and 5.Math.10.sup.15 cm.sup.3. The surface layer 5b may be formed by epitaxy. In this case the doping profile in a transition region at the interface between the surface layer 5a and the bulk layer 5b can be step-like with a steep gradient of the doping concentration, which increases in the transition region by at least 100% from the surface layer 5a to the bulk layer 5b, wherein the transition region has a thickness of less than 0.1 m. In the high power semiconductor device 1 according to the first embodiment a depth d.sub.SL of the surface layer 5a is greater than a depth d.sub.FFR of the floating field rings 10. Accordingly, in the first embodiment the floating field rings 10, which have all the same depth d.sub.FFR, are embedded in the surface layer 5a.

(13) In the first embodiment shown in FIG. 1 the first (i.e. the innermost) floating field ring 10 is spaced from the anode layer 7 in a lateral direction by a distance d.sub.0. Therein, the distance d.sub.0 is the minimum distance between the anode layer 4 and the first floating field ring 10 in a plane parallel and adjacent to the first main side surface 2. The distance do is constant along the whole first floating field ring 10. In FIG. 1, the distance between the second floating field ring 10 and the first floating field ring 10 in the lateral direction is d.sub.1, the distance between the third floating ring 10 and the second floating field ring 10 is d.sub.2, and the distance between fourth floating field ring 10 and the third floating field ring 10 is d.sub.3. The distance do is smaller than any distance d.sub.1, d.sub.2, d.sub.3 between neighbouring floating field rings 10, and the distances d.sub.1, d.sub.2, d.sub.3 between neighbouring floating field rings 10 increase from inside to outside (i.e. they increase with increasing distance from the active region AR). The distance do may be in a range from 20% to 60% of the maximum distance between the outermost pair of neighbouring floating field rings 10. Exemplarily the distance do is at least 2 m, more exemplarily at least 3 m. Neighbouring floating field rings 10 are separated from each other by the surface layer 5a and by a corresponding one of the enhanced doping regions 15. Likewise the first floating field ring 10 is separated from the anode layer 4 by the surface layer 5a and the corresponding enhanced doping region 15. A lateral width w.sub.FFR of the floating field rings 10 in a plane parallel and adjacent to the first main side surface 2 may be the same for all floating field rings 10 but it can also vary from ring to ring.

(14) In the first embodiment, the drift layer 5 further comprises a plurality of n-doped enhanced doping regions 15. Each one of the enhanced doping regions 15 is formed in the termination region TR adjacent to the first main side surface 2 of the wafer W as a ring-shaped semiconductor region, which is laterally surrounding the active region AR and the anode layer 7, wherein each one of the enhanced doping regions 15 is in direct contact with a corresponding one of the floating field rings 10 on a lateral side, which faces towards the active region AR (i.e. on the left side of the floating field rings 10 in FIGS. 1 and 2), to form a pn-junction with the corresponding one of the floating field rings 10. On the other side each one of the floating field rings 10 is in direct contact with a corresponding one of the enhanced doping regions 15.

(15) Each one of the enhanced doping regions 15 has a peak doping concentration which is higher than the minimum doping concentration of the bulk layer 5b. Exemplarily each enhanced doping region 15 has a local doping concentration which is everywhere in the enhanced doping regions 15 higher than the minimum doping concentration of the bulk layer 5b. Exemplarily the doping concentration of the bulk layer 5b is constant and the local doping concentration of the enhanced doping regions 15 is everywhere in the enhanced doping regions 15 higher than the constant doping concentration of the bulk layer 5b. Exemplarily the peak doping concentration of each one of the enhanced doping regions 15 is in a range between 1.Math.10.sup.16 cm.sup.3 and 1.Math.10.sup.18 cm.sup.3. The enhanced doping region 15 next to the active region AR is separated by the surface layer 5a from the anode layer 4 in a direction towards the active region AR. The remaining enhanced doping regions 15 (i.e. all enhanced doping regions 15 except the one next to the active region AR) are separated by the surface layer 5a from the next floating field region 10 in a direction towards the active region AR, respectively.

(16) Each one of the enhanced doping regions 15 envelops a part of a bottom surface of the corresponding one of the floating field rings 10. Accordingly, each one of the enhanced doping regions 15 overlaps with the corresponding one of the floating field rings 10 in an orthogonal projection onto a plane parallel to the first main side surface 2.

(17) Each one of the enhanced doping regions 15 has a lateral width w.sub.EDR in a plane parallel and adjacent to the first main side surface 2, which is smaller than a lateral width w.sub.FFR of a neighbouring floating field ring 10 in the plane parallel and adjacent to the first main side surface 2, and which is smaller than a separation distance between this enhanced doping region 15, 15, 15, 15 and the next floating field region 10 or the anode layer 4 separated from this enhanced doping region 15, 15, 15, 15 by the surface layer 5a in a direction towards the active region AR. Therein, the separation distance between the enhanced region 15 of the first floating field ring 10 and the anode layer 4 is calculated by d.sub.0-2.sub.EDR. Likewise the separation distance between the enhanced region 15 of the second floating ring 10 and the first floating ring 10 is calculated by d.sub.1-w.sub.EDR, the separation distance between the enhanced region 15 of the third floating ring 10 and the second floating ring 10 is calculated by d.sub.2-w.sub.EDR, and so on. Exemplarily, the lateral width w.sub.EDR of the enhanced doping regions 15, 15, 15, 15 is in a range between 0.3 m to 3 m, more exemplarily in a range between 0.5 and 2 m. Exemplarily the lateral width w.sub.EDR of the enhanced doping region 15, 15, 15, 15 between two each pair of two neighbouring floating field rings 10 is less than half of the distance between these two neighbouring floating field rings 10, more exemplarily less than a third of the distance between these two neighbouring floating field rings 10.

(18) On the termination region TR there is formed a passivation layer 20 on the first main side surface 2 of the wafer W.

(19) The number of floating field rings 10 in the edge termination structure may vary dependent on the voltage class of the high power semiconductor device 1 and depending on the depth d.sub.FFR of the floating field rings 10. The total number of floating field rings 10 may be up to 200.

(20) In the following there is explained a second embodiment of the high power semiconductor device with reference to FIG. 3. Due to the many similarities of the second embodiment with the first embodiment only differences of the second embodiment to the first embodiment are discussed. The remaining features are the same as in the first embodiment and for an explanation thereof it is referred to the first embodiment discussed above with reference to FIGS. 1 and 2. The enhanced doping regions 15 in the high power semiconductor device according to the second embodiment differ from the enhanced doping regions 15 in the first embodiment in that the enhanced doping regions 15 have a depth d.sub.EDR, which is identical to the depth d.sub.FFR of the floating field rings 10. Accordingly, in contrast to the enhanced doping regions 15 in the first embodiment, the enhanced doping regions 15 do not cover the bottom surface of the floating field rings 10, respectively.

(21) In the following there is explained a third embodiment of the high power semiconductor device with reference to FIG. 4. Due to the many similarities of the third embodiment with the first embodiment only differences of the third embodiment to the first embodiment are discussed. The remaining features are the same as in the first embodiment and for an explanation thereof it is referred to the first embodiment discussed above with reference to FIGS. 1 and 2. The high power semiconductor device according to the third embodiment differs from that of the first embodiment in that the doping profile in a transition region from the enhanced doping regions 15 to the surface layer 5a and from the enhanced doping regions 15 to the floating field rings 10 are step-like. This is attained by a manufacturing method, in which the enhanced doping regions 15 are formed by filling a trench instead of forming the enhanced doping regions 15 by implantation or diffusion of an n-type dopant. Further, in the third embodiment the lateral width of the enhanced doping regions 15 is substantially constant from the first main side surface to the bottom. Exemplarily, the width varies by less than 10% from the first main side surface 2 to the bottom side of the enhanced doping regions 15 opposite to the first main side surface 2. The enhanced doping regions 15 in the third embodiment require less area compared to the implanted/diffused enhanced doping regions 15 of the first embodiment since the abrupt doping or step-like doping profile allows to employ a relatively small lateral width w.sub.EDR of the enhanced doping region 15. Also, the abrupt step-like transition from the enhanced doping region 15 to the p-type floating field ring 10 can further improve the electric field coupling from floating field ring 10 to floating field ring 10.

(22) In the following there is explained a fourth embodiment of the high power semiconductor device with reference to FIG. 5. Due to the many similarities of the fourth embodiment with the first embodiment only differences of the fourth embodiment to the first embodiment are discussed. The remaining features are the same as in the first embodiment and for an explanation thereof it is referred to the first embodiment discussed above with reference to FIGS. 1 and 2. The high power semiconductor device according to the fourth embodiment differs from that of the first embodiment in that the enhanced doping regions 15 envelop not only a (relatively small) part of a bottom surface of the corresponding one of the floating field rings 10 but a main part of or the whole bottom surface of the floating field rings 10. This can further enhance the electric field coupling from floating field ring 10 to floating field ring 10.

(23) In the following there is explained a fifth embodiment of the high power semiconductor device with reference to FIG. 6. Due to the many similarities of the fifth embodiment with the first embodiment only differences of the fifth embodiment to the first embodiment are discussed. The remaining features are the same as in the first embodiment and for an explanation thereof it is referred to the first embodiment discussed above with reference to FIGS. 1 and 2. The high power semiconductor device according to the fifth embodiment differs from that of the fourth embodiment in that there is further provided a p-type extension region 30 on the lateral side of the floating field ring 10, which faces away from the active region, i.e. on a side of the floating field ring 10 opposite to the side, on which the enhanced doped region 15 is located. The extension region 30 is in direct contact with the floating ring 10 and has a doping concentration lower than that of the floating field ring 10. It extends from the first main side surface 2 to a depth d.sub.ER, which is larger than that of the floating field ring 10. The extension region 30 has the advantageous effect that it can reduce the maximum electric field peak.

(24) In FIG. 7 there is shown a sixth embodiment of the high power semiconductor device. It differs from the before explained fifth embodiment only in that it employs the enhanced doping regions 15 of the fourth embodiment shown in FIG. 5.

(25) It will be apparent for persons skilled in the art that modifications of the above described embodiments are possible without departing from the idea of the invention as defined by the appended claims.

(26) In the above embodiments the surface layer 5a extended from the first main side surface 2 to a depth d.sub.SL larger than the depth d.sub.FFR of the floating field rings 10. In an exemplary example, which is not part of the invention, a significant improvement of the electric field coupling from floating field ring 10 to floating field ring 10 can still be achieved in case that depth d.sub.SL of the surface layer 5a is at least 80% of the depth d.sub.FFR of the floating field rings 10. Exemplarily, the surface layer 5a may extend from the first main side surface 2 to a depth d.sub.SL which is at least the same as a depth d.sub.FFR of the floating field rings 10.

(27) In the above embodiments the material of the semiconductor wafer W, and in particular the material of the anode layer 4, the material of the drift layer 5 and the material of the substrate layer 6 was described to be 4H-SiC. However, it is also possible to use other semiconductor materials such as silicon or group-III-nitrides, such as gallium nitride or aluminum nitride. If the semiconductor material is silicon, the peak doping concentration of the enhanced doping regions is exemplarily in a range between 1.Math.10.sup.15 cm.sup.3 and 1.Math.10.sup.17 cm.sup.3.

(28) In the above embodiments the high power semiconductor device was described to be a high power diode (pin diode). However, the described edge termination structure may be employed also for any other high power semiconductor device such as a junction gate field-effect transistor (JFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a bipolar junction transistor (BJT), or a thyristor. In case of some high power semiconductor devices, such as in the case of an IGBT, the first semiconductor layer is not an anode layer as in the above explained embodiments, but a cathode layer, the first electrode is not an anode electrode as in the above explained embodiments but a cathode electrode, and the second electrode is not a cathode electrode as in the above explained embodiments but an anode electrode.

(29) Further, some high power semiconductor devices may comprise additional semiconductor layers, such as in an IGBT, where a p+-doped substrate layer is inserted between an n+-doped buffer layer (corresponding to the third semiconductor layer in the claims) and an anode electrode (corresponding to the second electrode in the claims).

(30) All above embodiments included the enhanced doping region 15, 15, 15, 15 which has the depth d.sub.EDR, d.sub.EDR which is at last as deep as the depth d.sub.FFR of the floating field rings 10. In an exemplary example, which is not part of the invention, an improvement of the area efficiency can also be achieved with more shallow enhanced doping regions.

(31) The above embodiments were explained with specific conductivity types. The conductivity types of the semiconductor layers in the above described embodiments might be switched, so that all layers which were described as p-type layers would be n-type layers and all layers which were described as n-type layers would be p-type layers.

(32) It should be noted that the term comprising does not exclude other elements or steps and that the indefinite article a or an does not exclude the plural. Also elements described in association with different embodiments may be combined.

LIST OF REFERENCE SIGNS

(33) 1 high power semiconductor device

(34) 2 first main side surface

(35) 3 second main side surface

(36) 4 (p-doped) anode layer

(37) 5 (n-doped) drift layer

(38) 5a surface layer

(39) 5b bulk layer

(40) 6 (n.sup.+-doped) substrate layer

(41) 7 anode electrode

(42) 8 cathode electrode

(43) 10 (p.sup.+-doped) floating field ring

(44) 15, 15, 15, 15 enhanced doping region

(45) 20 passivation layer

(46) AR active region

(47) d.sub.0, d.sub.1, d.sub.2, d.sub.3 distance

(48) d.sub.EDR, d.sub.EDR depth of enhanced doping region

(49) d.sub.ER depth of extension region

(50) d.sub.FFR depth of floating field rings

(51) d.sub.SL depth of the surface layer

(52) TR termination region

(53) w.sub.EDR, w.sub.EDR lateral width of enhanced doping regions

(54) w.sub.FFR lateral width of the floating rings

(55) W wafer