Semiconductor Structure with an Epitaxial Layer Stack for Fabricating Back-side Contacts

Abstract

An example includes a semiconductor structure including a semiconductor layer, front-side logic devices arranged in a front-side of the semiconductor layer, four epitaxial layers on a back-side of the semiconductor layer, where the four epitaxial layers include a first epitaxial layer of a first conductivity type, a second epitaxial layer of a second conductivity type, a third epitaxial layer of the second conductivity type, and a fourth epitaxial layer of the first conductivity type, a plurality of back-side contacts exposed at a back-side surface of the fourth epitaxial layer, where the plurality of back-side contacts include a set of first terminal contacts extending into and contacting the fourth epitaxial layer, a set of second terminal contacts extending into and contacting the second epitaxial layer, a set of first gate contacts extending into the third epitaxial layer, and a set of second gate contacts extending into the first epitaxial layer.

Claims

1. A semiconductor structure comprising: a semiconductor layer; one or more front-side logic devices that are at least partly arranged in a front-side of the semiconductor layer; at least four epitaxial layers arranged on a back-side of the semiconductor layer, wherein the four epitaxial layers comprise a first epitaxial layer of a first conductivity type, a second epitaxial layer of a second conductivity type provided on the first epitaxial layer, a third epitaxial layer of the second conductivity type provided on the second epitaxial layer, and a fourth epitaxial layer of the first conductivity type provided on the third epitaxial layer; a plurality of back-side contacts that are exposed at a back-side surface of the fourth epitaxial layer, wherein the plurality of back-side contacts comprise: a set of first terminal contacts extending into and electrically contacting the fourth epitaxial layer; a set of second terminal contacts extending into and electrically contacting the second epitaxial layer; a set of first gate contacts extending into the third epitaxial layer; and a set of second gate contacts extending into the first epitaxial layer.

2. The semiconductor structure according to claim 1, wherein: the set of second terminal contacts is electrically isolated from the third epitaxial layer and the fourth epitaxial layer; the set of first gate contacts is electrically isolated from the third epitaxial layer and the fourth epitaxial layer; and the set of second gate contacts is electrically isolated from the first epitaxial layer, the second epitaxial layer, the third epitaxial layer, and the fourth epitaxial layer.

3. The semiconductor structure according to claim 1, further comprising: a first-conductivity-type MOS device formed by a first gate contact of the set of first gate contacts configured as a first gate of the first-conductivity-type MOS device and two first terminal contacts of the set of first terminal contacts configured as a first source and a first drain of the first-conductivity-type MOS device.

4. The semiconductor structure according to claim 3, wherein: the first-conductivity-type MOS device further comprises a ring-shaped first gate contact surrounding the first drain and a ring-shaped first source surrounding the ring-shaped first gate contact.

5. The semiconductor structure according to claim 3, wherein: the first-conductivity-type MOS device further comprises a first bulk contact formed by a second terminal contact of the set of second terminal contacts and a first top contact formed by a first terminal contact of the set of first terminal contacts.

6. The semiconductor structure according to claim 1, further comprising: a second-conductivity-type MOS device formed by a second gate contact of the set of second gate contacts configured as a second gate of the second-conductivity type MOS device and two second terminal contacts of the set of second terminal contacts configured as a second source and a second drain of the second-conductivity-type MOS device.

7. The semiconductor structure according to claim 6, wherein: the second-conductivity-type MOS device comprises a ring-shaped second gate contact surrounding the second drain and a ring-shaped second source surrounding the ring-shaped second gate contact.

8. The semiconductor structure according to claim 6, wherein: the second-conductivity-type MOS device further comprises a second bulk contact formed by a second terminal contact of the set of second terminal contacts and a second top contact formed by a first terminal contact of the set of first terminal contacts.

9. The semiconductor structure according to claim 6, wherein the back-side surface of the fourth epitaxial layer is divided into one or more first-conductivity type areas and one or more second-conductivity-type areas by a plurality of intersecting isolation structures, wherein each of the one or more first-conductivity type areas comprises one first-conductivity-type MOS device and each of the one or more second-conductivity-type areas comprises one second-conductivity-type MOS device.

10. The semiconductor structure according to claim 6, further comprising: two shallow trench isolations (STIs) extending in parallel along a first direction; two isolation gates extending in parallel along a second direction, which is perpendicular to the first direction, and intersecting with the two STIs; and a first-conductivity-type area or a second-conductivity-type area formed within the two STIs and two isolation gates.

11. The semiconductor structure according to claim 1, further comprising: one or more isolation structures extending into the first epitaxial layer and being either an isolation gates formed by second gate contact of the set of second gate contacts or being a shallow trench isolation.

12. The semiconductor structure according to claim 11, comprising a first-conductivity-type MOS device and a second-conductivity-type MOS device that are separated from each other by at least one of the isolation structures.

13. The semiconductor structure according to claim 1, wherein: the fourth epitaxial layer has a higher doping concentration of first conductivity type dopants than the first epitaxial layer; and/or the second epitaxial layer has a higher doping concentration of second conductivity type dopants than the third epitaxial layer.

14. The semiconductor structure according to claim 1, wherein the one or more front-side logic devices comprise at least one of a CMOS device and a nanosheet device.

15. The semiconductor structure according to claim 1, wherein a first gate contact of the set of first gate contacts and/or a second gate contact of the set of second gate contacts has a triangular tip or a round tip formed, respectively, within the third epitaxial layer and/or the first epitaxial layer.

16. A device comprising: a semiconductor structure according to claim 1; and one or more back-side semiconductor devices that are coupled to the plurality of back-side contacts of the semiconductor structure.

17. A method for fabricating a semiconductor structure, the method comprising: forming a semiconductor layer and four epitaxial layers on a back-side of the semiconductor layer; forming one or more front-side logic devices that are at least partly arranged in a front-side of the semiconductor layer; wherein the four epitaxial layers comprise a first epitaxial layer of a first conductivity type, a second epitaxial layer of a second conductivity type provided on the first epitaxial layer, a third epitaxial layer of the second conductivity type provided on the second epitaxial layer, and a fourth epitaxial layer of the first conductivity type provided on the third epitaxial layer; forming a plurality of back-side contacts that are exposed at a back-side surface of the fourth epitaxial layer, the plurality of back-side contacts comprising: a set of first terminal contacts extending into and electrically contacting the fourth epitaxial layer; a set of second terminal contacts extending into and electrically contacting the second epitaxial layer; a set of first gate contacts extending into the third epitaxial layer; and a set of second gate contacts extending into the first epitaxial layer.

18. The method according to claim 17, wherein forming the semiconductor layer and the four epitaxial layers on the back-side of the semiconductor layer comprises: providing a semiconductor substrate; forming an etch stop layer on the semiconductor substrate; forming the four epitaxial layers, starting with the fourth epitaxial layer, on the etch stop layer; forming the semiconductor layer on the first epitaxial layer; thinning the semiconductor substrate to the etch stop layer; and removing the etch stop layer.

19. The method according to claim 18, wherein: each of the four epitaxial layers comprises silicon; and/or the etch stop layer is formed on the semiconductor substrate and comprises silicon germanium.

20. The method according to claim 17, wherein forming the semiconductor layer and the four epitaxial layers on the back-side of the semiconductor layer comprises: providing a semiconductor substrate; forming the four epitaxial layers, starting with the fourth epitaxial layer, on the semiconductor substrate; forming the semiconductor layer on the first epitaxial layer; and thinning the semiconductor substrate to the fourth epitaxial layer, which serves as an etch stop layer.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0050] The above, as well as additional, features will be better understood through the following illustrative and non-limiting detailed description of example embodiments, with reference to the appended drawings.

[0051] FIG. 1A shows a fabrication of a conventional device including front-side logical devices and back-side semiconductor devices, according to an example.

[0052] FIG. 1B shows a fabrication of a conventional device including front-side logical devices and back-side semiconductor devices, according to an example.

[0053] FIG. 1C shows a fabrication of a conventional device including front-side logical devices and back-side semiconductor devices, according to an example.

[0054] FIG. 2 shows a cross-section of a semiconductor structure, which includes one or more front-side logic devices and a plurality of back-side contacts, according to an example.

[0055] FIG. 3 shows a top-view of a semiconductor structure, for example, of the semiconductor structure shown in FIG. 2 and/or the semiconductor structure shown in FIG. 4, according to an example.

[0056] FIG. 4 shows a cross-section of a semiconductor structure, which includes one or more front-side logic devices and a plurality of back-side contacts, according to an example.

[0057] FIG. 5 shows a flow-diagram of a method, which may be used to fabricate a semiconductor structure, according to an example.

[0058] FIG. 6 shows a step of a method for fabricating a semiconductor structure, according to an example.

[0059] FIG. 7A shows further steps of the method shown in FIG. 6, according to an example.

[0060] FIG. 7B shows further steps of the method shown in FIG. 6, according to an example.

[0061] FIG. 8A shows further steps of the detailed method shown in FIG. 6 and in FIG. 7, according to an example.

[0062] FIG. 8B shows further steps of the detailed method shown in FIG. 6 and in FIG. 7, according to an example.

[0063] FIG. 9A shows further steps of the method shown in the FIGS. 6-8, according to an example.

[0064] FIG. 9B shows further steps of the method shown in the FIGS. 6-8, according to an example.

[0065] FIG. 10 shows a cross-section of a semiconductor structure, which results from the detailed method shown in the FIGS. 6-9, according to an example.

[0066] FIG. 11 shows a cross-section of a semiconductor structure, which includes one or more gate contacts with a triangular tip, according to an example.

[0067] FIG. 12 shows a cross-section of a semiconductor structure, which has layers of reversed conductivity types, according to an example.

[0068] FIG. 13 shows a top-view of a semiconductor structure, which has a surrounded drain architecture, according to an example.

[0069] All the figures are schematic, not necessarily to scale, and generally only show parts which are necessary to elucidate example embodiments, wherein other parts may be omitted or merely suggested.

DETAILED DESCRIPTION

[0070] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. That which is encompassed by the claims may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example. Furthermore, like numbers refer to the same or similar elements or components throughout.

[0071] FIG. 2 shows a semiconductor structure 20 according to an embodiment of this disclosure. The semiconductor structure 20 of FIG. 2 includes one or more front-side logic devices 22 and a plurality of back-side contacts 24, which may comprise one or more terminal contacts and one or more gate contacts. The back-side contacts 24 may be configured to couple to semiconductor back-side devices (not shown in FIG. 2), which may be further processed on the semiconductor structure 20 back-side, or which may be coupled to the semiconductor structure 20 from its back-side. These further semiconductor back-side devices may, for example, be connected via the back-side contacts 24 to the one or more front-side logic devices 22. Further, these semiconductor back-side devices may be part of a PDN for the one or more front-side logic devices 22. The arrow in FIG. 2 indicates that a bias from the back-side to the front-side is possible.

[0072] Notably, “back-side” and “front-side” are used as terms relative to each other in this disclosure. Typically, any structures and devices at the front-side are those that are processed first in a semiconductor fabrication process, while any structures and devices at the back-side are those that are processed after the front-side structures and devices, particularly, late in the semiconductor fabrication process.

[0073] In particular, the semiconductor structure 20 of FIG. 2 comprises a semiconductor layer 21, which may be a silicon layer or a silicon-based layer. The semiconductor layer 21 may further be an epitaxial layer (i.e., a layer grown with epitaxy). The semiconductor layer 21 may thereby be of the first conductivity type or of the second conductivity type, i.e., it may be P-doped or N-doped.

[0074] The one or more front-side logic devices 22 are at least partly arranged in a front-side of the semiconductor layer 21. As shown in FIG. 2, the front-side logic devices 22 may be provided on a front-side surface of the semiconductor layer 21—specifically, they may be arranged partly in a dielectric layer that may be provided on the semiconductor layer 21—and may extend partly into the front-side of the semiconductor layer 21. The front-side logic devices 22 may, for instance, include one or more CMOS devices, and/or one or more FinFET devices, and/or one or more nanosheet devices.

[0075] Further, the semiconductor structure 20 comprises at least four epitaxial layers 23 (e.g., 23a, 23b, 23c, and 23d) (it may particularly comprise more than four epitaxial layers 23, e.g., five, six or even more such epitaxial layers 23), which are arranged on a back-side of the semiconductor layer 21. These four or more epitaxial layers 23 may be formed in-situ and/or epitaxially. Further, these epitaxial layers 23 may form an epitaxial layer stack, which is arranged on the semiconductor layer 21.

[0076] The at least four epitaxial layers 23 comprise a first epitaxial layer 23a of a first conductivity type, a second epitaxial layer 23b of a second conductivity type provided directly on the first epitaxial layer 23a, a third epitaxial layer 23c of the second conductivity type provided directly on the second epitaxial layer 23b, and a fourth epitaxial layer 23d of the first conductivity type provided directly on the third epitaxial layer 23c.

[0077] The plurality of back-side contacts 24 are furthermore exposed at a back-side surface of the fourth epitaxial layer 23d, i.e., they are accessible via the back-side surface, and may be formed in the epitaxial layer stack of the four or more epitaxial layers 23. Thereby, different back-side contacts 24 may extend into different epitaxial layers 23 of the stack (while being isolated from epitaxial layers 23, through which they extend). That means, different back-side contacts 24 may be processed into different depths of the epitaxial layer stack.

[0078] The plurality of back-side contacts 24 comprises different types of back-side contacts 24. In particular, the plurality of back-side contacts 24 comprises a set of first terminal contacts 24a, wherein each first terminal contact 24a extends into and electrically contacts the fourth epitaxial layer 23d. Further, the plurality of back-side contacts 24 comprises a set of second terminal contacts 24b, wherein each second terminal contact 24b extends into and electrically contacts the second epitaxial layer 23b. The set of the second terminal contacts 24b may thereby extend through and may be electrically isolated from, respectively, the third epitaxial layer 23c and the fourth epitaxial layer 23d. Notably, a set of terminal contacts 24a or 24b may respectively comprise one or more of the terminal contacts 24a or 24b.

[0079] Further, the plurality of back-side devices 24 comprises a set of first gate contacts 24c, where each first gate contact 24c extends into the third epitaxial layer 23c. The set of the first gate contacts 24c may extend through the fourth epitaxial layer 23d, and may be electrically isolated from the third epitaxial layer 23c and the fourth epitaxial layer 23d, respectively. Further, the plurality of back-side devices 24 comprises a set of second gate contacts 24d, wherein each second gate contact 24d extends into the first epitaxial layer 23a. The set of second gate contacts 24d may extend through the second epitaxial layer 23b, the third epitaxial layer 23c, and the fourth epitaxial layer 23d. Further, the set of second gate contacts 24d may be electrically isolated from the first, the second, the third, and the fourth epitaxial layers 23a, 23b, 23c, 23d. Notably, a set of gate contacts 24c or 24d may respectively comprise one or more of the gate contacts 24c or 24d.

[0080] For instance, as an example of the semiconductor structure 20 of FIG. 2, if the first conductivity type is the P-type, the four epitaxial layers 23 may be doped to be respectively P−, N+, N−, P+ layers (from first epitaxial layer 23a to fourth epitaxial layer 23d). If, however, the first conductivity type is N-type, the four epitaxial layers 23 may be doped to be respectively N−, P+, P−, N+ layers (from first epitaxial layer 23a to fourth epitaxial layer 23d). If there are more than four epitaxial layers 23, the above-described doping/layer sequence for the four epitaxial layers 23a-23d may be periodically repeated. That is, for more than four epitaxial layers 23, the layer sequence would be, for example, P−, N+, N−, P+, P−, N+, N−, P+ for eight epitaxial layers (wherein the last four layers P−, N+, N−, P+ are the first epitaxial layer 23a to fourth epitaxial layer 23d), or would be P−, N+, N−, P+, P−, N+, N−, P+, P−, N+, N−, P+ for twelve epitaxial layers (wherein the last four layers P−, N+, N−, P+ are the first epitaxial layer 23a to fourth epitaxial layer 23d), and so on.

[0081] Notably, there is no requirement that the number of epitaxial layers 23 is a multiple of four. That is, e.g. according to the above layer (doping) sequences, also five, six, or seven epitaxial layers 23 are possible, wherein in this case four layers of the five or more epitaxial layers 23 are the first epitaxial layer 23a to fourth epitaxial layer 23d (e.g., P−, N+, N−, P+).

[0082] Moreover, in any implementation of the at least four epitaxial layers 23, it is also possible that any of the first epitaxial layer 23a to the fourth epitaxial layer 23d has a non-constant or graded doping profile. For example, in this case the doping concentrations for any epitaxial P+, P−, N+, or N− layer may respectively vary within 10.sup.19 to 10.sup.21 cm.sup.−3 for N+ and P+ layers (for example, in a graded manner), and within 10.sup.16 to 10.sup.19 cm.sup.−3 for N− and P− layers (for example, in a graded manner).

[0083] Further, in any implementation of the at least four epitaxial layers, it is also possible that any of the first epitaxial layer 23a to the fourth epitaxial layer 23d comprises a first sublayer having a higher doping concentration and a second sublayer having a lower doping concentration than the first sublayer, wherein the first sublayer is arranged directly on top of the second sublayer, or vice versa. For instance, the second epitaxial layer 23b may comprise a first N− sublayer and a second N+ sublayer, i.e., it may be referred to as an N−/N+ layer. In this example, the at least four epitaxial layers 23 may form a doping/layer sequence of P−, N−/N+, N−, P+ (from first epitaxial layer 23a to fourth epitaxial layer 23d). With reversed conductivity types, the layer sequence in this example would be N−, P−/P+, P−, N+ (from first epitaxial layer 23a to fourth epitaxial layer 23d). The N-/N+ or P−/P+ layer may reduce a hot carrier effect, band-to-band tunneling, and a parasitic capacitance. The first sublayer and the second sublayer of any epitaxial layer 23 may have different thicknesses. For example, the first sublayer may be thinner than the second sublayer. In the above example of the second epitaxial layer 23b being an N−/N+ (or P−/P+) layer, the first N− (or P−) sublayer may have a thickness of 3-6 nm, while the second N+ (or P+) sublayer has a thickness of 10 nm or larger.

[0084] Moreover, each epitaxial P+ layer or P−/P+ layer of the at least four epitaxial layers 23 may define a PMOS level, and each epitaxial N+ layer or N−/N+ layer of the at least for epitaxial layers 23 may define an NMOS level. It is also possible to have a different V.sub.th level (threshold voltage) through a different channel doping in each vertical level of the epitaxial layers 23.

[0085] The epitaxial layer stack, in particular, the fourth epitaxial layer 23d, may be exposed at the back-side of the semiconductor structure 20. This may, for instance, be achieved by performing substrate thinning as explained further below. Thus, the back-side contacts 24 may be formed in the four epitaxial layers 23, and may be exposed at the back-side surface of the fourth epitaxial layer 23d.

[0086] Each back-side contact 24 may be provided with one of several different functions. For example, one or more PMOS devices and/or NMOS devices may be formed by the back-side contacts 24. Each PMOS or NMOS device may thereby comprise a source, a drain, and a gate. However, the back-side contacts 24 may also be used to form isolation gates, e.g., to be arranged between different MOS devices for isolating those MOS devices from each other.

[0087] FIG. 3 shows a semiconductor structure 20 according to an embodiment of this disclosure, which builds on the embodiment shown in FIG. 2. Same elements in these figures are labeled with the same reference signs and may be implemented likewise.

[0088] In particular, FIG. 3 shows the semiconductor structure 20 in a top-view. FIG. 3 shows specifically that the semiconductor structure 20 may comprise one or more first-conductivity type MOS devices (for example, PMOS devices in this figure), and or one or more second-conductivity MOS devices (for example, NMOS devices in this figure). These MOS devices of the different conductivity types may be arranged in one or more MOS rows and/or in one or more MOS columns. Thereby, adjacent MOS devices may be separated from each other by at least one isolation structure. The semiconductor structure 20 may comprise a plurality of such isolation structures. As shown in FIG. 3, each such isolation structure may be realized by an isolation gate 30a (also referred to as dummy gate), or by a STI 30b (grey bars in FIG. 3).

[0089] In the embodiment of FIG. 3, different rows of MOS devices may be separated from each other by one or more STIs 30b, and different MOS devices within each row of MOS devices may be separated from each other by at least one dummy gate 30a. This separation scheme can, however, be adapted or intermixed, so that generally one or more isolation gates 30a and/or STIs 30b may be used to separate different MOS devices from each other.

[0090] Each PMOS device in the embodiment of FIG. 3 is formed by one first gate contact 24c, which is configured as a PMOS gate (“Active gate” in FIG. 2; first gate 31), and further by two first terminal contacts 24a, which are respectively configured as PMOS source (“S” in FIG. 2; first source 32) and PMOS drain (“D” in FIG. 2; first drain 33). Further, each NMOS device is formed by one second gate contact 24d, which is configured as an NMOS gate (“Active gate” in FIG. 2; second gate 34), and is further formed by two second terminal contacts 24b, which are respectively configured as NMOS source (“S” in FIG.2; second source 35) and NMOS drain (“D” in FIG. 2; second drain 36).

[0091] Furthermore, each PMOS device may further comprise one or more first bulk contacts 37 (“B” in FIG. 3), each being formed by one second terminal contact 24b. In addition, each PMOS device may comprise one or more first top contacts 38 (“T” in FIG. 2), each being is formed by one first terminal contact 24a. Likewise, each NMOS device may comprise one or more second bulk contacts 37, each being formed by one second terminal contact 24b, and may comprise one or more second top contacts 38, each being formed by one first terminal contact 24a.

[0092] Moreover, in the embodiment of FIG. 3, the back-side surface of the semiconductor structure 20 (which is visible in the top-view) may be divided into one or more areas (also referred to as islands), which are separated from each other by the isolating structures (e.g., isolation gates 30a and STIs 30b), respectively. Each area may comprise a MOS device, for instance, each first-conductivity type area may comprise one of the PMOS devices and each second-conductivity type area may comprise one of the NMOS devices, or vice versa.

[0093] In the embodiment of FIG. 3, as an example, two STIs 30b extend in parallel along a first direction (the horizontal direction in the figure), and two isolation gates 30a extend in parallel along a second direction (the vertical direction in the figure), wherein they intersect with the two STIs 30b. Between these four isolation structures (e.g., isolation gates 30a and STIs 30b), a MOS device may be arranged. For instance, it may be a PMOS device, wherein in this case an NMOS device may be arranged in the neighboring area realized by the two STIS 30b and an additional dummy gate 30a.

[0094] In FIG. 3, also two cuts through the semiconductor structure 20 are indicated by dashed lines, namely labelled CUT 1 and CUT 2. Of those, CUT 1 may lead to the cross-section of the semiconductor structure 20 shown in FIG. 2.

[0095] That is, also in the semiconductor structure 20 shown in FIG. 2, at least one PMOS source 32 and at least one PMOS drain 33 may be formed by the first terminal contacts 24a, which respectively reach the fourth epitaxial layer 23d. Further, at least one PMOS gate 31 may be formed by the first gate contact 24c, which reaches the third epitaxial layer 23c and is arranged between the first terminal contacts 24a that may form the PMOS source 32 and the PMOS drain 33. Moreover, at least one NMOS source 35 and at least one NMOS drain 36 may be formed by the second terminal contacts 24b, which reach the second epitaxial layer 23b. And consequently, at least one NMOS gate 34 may be formed by one of the second gate contact 24d, which reaches the first epitaxial layer 23a and is arranged between the second terminal contacts 24b that may form the NMOS source 35 and NMOS drain 36.

[0096] Further in FIG. 2, at least three additional isolation gates 30a may be formed by the shown remaining second gate contacts 24d, wherein each isolation gate 30a extends into the first epitaxial layer 23a. The semiconductor structure 20 of FIG. 2 may also include one or more STIs 30b (not shown in FIG. 2). As shown in FIG. 3, these isolation structures (e.g., isolation gates 30a and STIs 30b) may intersect each other (e.g., perpendicularly), to define the separated and isolated areas on the back-side surface of the semiconductor structure 20.

[0097] FIG. 4 shows a semiconductor structure 20 according to an embodiment of this disclosure. The semiconductor structure 20 shown in FIG. 4 is based on the semiconductor structures 20 shown, respectively, in FIG. 2 and FIG. 3. Same elements in these figures are labeled with the same reference signs and may be implemented likewise.

[0098] Notably, the semiconductor structure 20 of FIG. 4 may be the same as that shown in FIG. 3. In particular, the CUT 2 shown in FIG. 3 may lead to the cross-section of the semiconductor structure 20 shown in FIG. 4. Therefore, the semiconductor structure 20 of FIG. 4 may also be the same semiconductor structure 20 as shown in FIG. 2, however, different cross-sections (CUT 1 vs. CUT 2 in FIG. 3) are illustrated in this case.

[0099] The semiconductor structure 20 of FIG. 4 may comprise again the one or more front-side logic devices 22, which may comprise one or more CMOS devices and/or one or more FinFET devices. Furthermore, the semiconductor structure 20 comprises the at least four epitaxial layers 23, and the various back-side contacts 24 that are fabricated into these four or more epitaxial layers 23.

[0100] According to the CUT 2 shown in FIG. 3, the semiconductor structure 20 shown in FIG. 4 includes at least two STIs 30b, at least one NMOS source 35 formed by a second terminal contact 24b, at least two bulk contacts 37 formed each by a second terminal contact 24b, and at least two top contacts 38 formed each by a first terminal contact 24a.

[0101] Notably, in the semiconductor structure 20 shown in the FIGS. 2-4, the semiconductor layer 21 may be a doped semiconductor layer, for instance, it may be a P-type or an N-type semiconductor substrate, which may be made of silicon or a silicon-based semiconductor material. Furthermore, the four or more epitaxial layers 23 may comprise two or more P-type epitaxial layers and two or more N-type epitaxial layers. In case of four epitaxial layers 23, there are two P-type epitaxial layers (in particular, P+and P−) and two N-type epitaxial layers (in particular, N+ and N−).

[0102] FIG. 5 shows a general method 50 according to an embodiment of this disclosure. The method 50 is suitable for fabricating the semiconductor structure 20 shown and explained in the previous figures.

[0103] The method 50 comprises a first step 51 of forming the semiconductor layer 21, for instance, an epitaxial silicon layer or silicon-based layer. Further, the method 50 comprises a second step 52 of forming the at least four epitaxial layers 23 on a back-side of the semiconductor layer 21. In particular, these four epitaxial layers 23 may be realized as shown in FIG. 2 or in FIG. 4. For example, the four epitaxial layers 23 comprise the first epitaxial layer 23a of the first conductivity type, the second epitaxial layer 23b of the second conductivity type, which is formed directly on the first epitaxial layer 23a, the third epitaxial layer 23c of the second conductivity type, which is formed directly on the second epitaxial layer 23b, and the fourth epitaxial layer 23d of the first conductivity type, which is formed directly on the third epitaxial layer 23c. The method 50 further comprises a step 53 of forming the one or more front-side logic devices 22, for instance, the one or more CMOS devices and/or FinFET devices. These front-side logic devices 22 are at least partly arranged in a front-side of the semiconductor layer 21.

[0104] Further, the method 50 comprises a step 54 of forming the plurality of back-side contacts 24, for instance, as shown in the previous FIGS. 2-4. These back-side contacts 24 are exposed at a back-side surface of the fourth epitaxial layer 23d, and comprise the set of first terminal contacts 24a, the set of second terminal contacts 24b, the set of first gate contacts 24c, and the set of second gate contacts 24d, which are described above.

[0105] FIGS. 6-9 show a method 50 according to a detailed embodiment of the disclosure, which builds on the method 50 shown in FIG. 5. The method 50 shown in these figures comprises the steps of the method 50 shown in FIG. 5. Same steps and elements in all these figures are labelled with the same reference signs, and may be implemented likewise.

[0106] FIG. 6 shows the first two steps 51 and 52 of the method 50. A semiconductor substrate 60 (e.g., a silicon or silicon-based substrate) is provided, and the at least four epitaxial layers 23 and the semiconductor layer 21 are formed on the silicon substrate 60. In particular, as indicated by the direction of fabrication (left-side arrow) in FIG. 6, an etch stop layer 61 may be first formed on the semiconductor substrate 60. Then the four or more epitaxial layers 23 (four layers are exemplarily shown) may be formed directly on the etch stop layer 61.

[0107] Thereby, the fourth epitaxial layer 23d is formed first and directly in this case on the etch stop layer 61. Then the third epitaxial layer 23c, the second epitaxial layer 23b, and the first epitaxial layer 23a are formed, in this order and one directly on the other, directly on the fourth epitaxial layer 23d. Subsequently, the semiconductor layer 21 may be formed directly on the first epitaxial layer 23a. If there are more than four epitaxial layers, other epitaxial layers may be formed directly on the first epitaxial layer 23a, and the semiconductor layer 21 may then be formed directly on these other epitaxial layers. The at least four epitaxial layers 23 are formed on a back-side of the semiconductor layer 21, and the exposed upper surface of the semiconductor layer 21 represents, accordingly, the front-side surface of the semiconductor layer 21.

[0108] FIG. 7A shows the step 53 of the method 50, in which the one or more front-side logic devices 22 are fabricated on the front-side of the semiconductor layer 21, as described previously. The one or more front-side logic devices 22 are at least partly arranged in the front-side of the semiconductor layer 21.

[0109] FIG. 7B is turned upside down compared to FIG. 7A and shows that a thinning step 70 may be carried out in the method 50. In particular, the semiconductor substrate 60 may be thinned 70 all the way down to the etch stop layer 61, and the etch stop layer 61 may be removed as well. Notably, it is also possible that there is no dedicated etch stop layer 61 provided. In this case, the fourth epitaxial layer 23d may also act as an etch stop layer during the step of substrate thinning 70. Furthermore, during the substrate thinning 70, the intermediate semiconductor structure may be stabilized on a carrier substrate 71 (e.g., a carrier wafer).

[0110] FIG. 8 and FIG. 9 further show details of the step 54 of the method 50, namely, the forming of the plurality of back-side contacts 24. In particular, FIG. 8A shows that a plurality of trenches 80 (may also be referred to as openings) are etched into the at least four epitaxial layers 23, wherein one trench 80 is related to each back-side contact 24 or STI 30b that is to be formed in the semiconductor structure 20. Accordingly, the trenches 80 may each have a different depth, and may accordingly extend into a different epitaxial layer 23 of the stack. Thereby, the trenches 80 may extend through different epitaxial layers 23 of the stack.

[0111] FIG. 8B shows further that then a dielectric material 81 (or another insulating material) may be deposited onto the surface of the fourth epitaxial layer 23d and into the inner surfaces of the respective trenches 80, which were formed in FIG. 8A. That is, both the sidewall surfaces of the trenches 80 and the bottom surfaces of the trenches 80 may be covered by the deposited material 81.

[0112] FIG. 9A shows further that the deposited material 81 may then be partly removed again, for instance, by etching. In particular, the deposited material 81 may be removed from the top surface of the fourth epitaxial layer 23d, and may also be removed from the bottom surface of all those trenches 80, which relate to first terminal contacts 24a or second terminal contacts 24b, so that later an electric (Ohmic or Schottky) connection is possible to the respective epitaxial layer 23, into which that terminal contact 24a or 24b extends. For those other trenches 80, which relate to a first gate contact 24c or a second gate contact 24d, the deposited material is not removed from the bottom surface of the trench 80, so that a gate contact may be formed in the respective epitaxial layer 23, into which that gate contact 24c or 24d extends (the dielectric material 81 may in this case be used as a gate dielectric). Notably, the dielectric material 81 may also remain on all the sidewalls of the trenches 80, in order to form liners, which may later isolate the back-side contacts 24 of the respective trenches 80 from the epitaxial layers 23, thorough which the back-side contacts 24 extend.

[0113] FIG. 9B shows further that then a contact material 90 may be deposited into each trench 80, which relates to a back-side device 24. This contact material 90 may comprise a metal, like aluminum, copper, tungsten, or the like. Furthermore, a dielectric material 91 may be deposited into each trench 80, which relates to an STI 30b.

[0114] FIG. 10 shows a semiconductor structure 20, which may be obtained by the method 50 shown in the previous FIGS. 6-9. The semiconductor structure 20 is based further on the previously shown semiconductor structures 20, for instance, those of FIGS. 2-4, respectively.

[0115] The semiconductor structure 20 of FIG. 10 comprises first terminal contacts 24a, which may form at least one PMOS source 32 and at least one PMOS drain 33, and second terminal contacts 24b, which may form at least one NMOS source 35 and at least one NMOS drain 36. Furthermore, the semiconductor structure 20 comprises at least one first gate contact 24c, which may form at least one PMOS gate 31, and at least one second gate contact 24d, which may form at least one NMOS gate 34. Further, the semiconductor structure 20 may comprise second gate contacts 24d, which may form one or more isolation gates 30a. In addition, the semiconductor structure 20 may also comprise one or more STIs 30b, and at least one top contact 38, which may respectively be formed by first terminal contacts 24a. Further, the semiconductor structure 20 may comprise at least one bulk contact 37, which may be formed by second terminal contacts 24b.

[0116] FIG. 11 shows a further semiconductor structure 20, which builds on the embodiment shown in FIG. 10. Same elements in FIG. 10 and FIG. 11 are labelled with the same reference signs and may be implemented likewise.

[0117] The difference between FIG. 10 and FIG. 11 is that FIG. 11 shows a version of the semiconductor structure 20, wherein at least the second gate contacts 24d have a triangular tip 110, wherein each triangular tip 110 is respectively formed in the first epitaxial layer 23a. Instead of having a triangular tip 110, these second gate contacts 24d may also have a round tip. Furthermore, it is also possible that the first gate contacts 24c have a triangular tip 110 or a round tip, which is in this case formed in the third epitaxial layer 23c.

[0118] FIG. 12 shows a further semiconductor structure 20 according to an embodiment of this disclosure. In particular, FIG. 12 shows that P-type and N-type doping may be reversed. That is, while the first conductivity type may be P-type, exemplarily shown in the previous figures, it may now be N-type in the semiconductor structure 20 of FIG. 12. Apart from this, the semiconductor structure 20 of FIG. 12 comprises the same features, particularly the same back-side contacts 24 of the semiconductor structure 20 shown in the previous figures. However, also here the conductivity type is switched.

[0119] In particular, FIG. 12 shows a PMOS source 35 implemented by a first terminal contact 24a and a PMOS drain 36 implemented by a first terminal contact 24a. Further, it shows a PMOS gate 34 implemented by a first gate contact 24c. Further, it shows an NMOS drain 32 and a NMOS source 33 implemented by second terminal contacts 24b. Further, it shows an NMOS gate 31 implemented by a second gate contact 24d. The semiconductor structure 20 may also comprise top contacts 38 implemented by first terminal contacts 24a, and bulk contacts 37 implemented by second terminal contacts 24b.

[0120] FIG. 13 shows a semiconductor structure 20 in a top-view according to an embodiment of this disclosure. The semiconductor structure 20 is based on the previously shown semiconductor structures 20, and same elements in the figures are again labelled with the same reference signs.

[0121] In particular, the semiconductor structure 20 shown in FIG. 13 comprises a ring-shaped first gate contact 24c (could also be a ring-shaped second gate contact 24d), which surrounds a first drain 33 (or a second drain 36). Further, the semiconductor structure 20 comprises a ring-shaped first source 32 (or a ring-shaped second source 35), which surrounds the ring-shaped first gate contact 24c (or ring-shaped second gate contact 24d). As shown in FIG. 13, within the ring-shaped source or ring-shaped gate, there may be arranged further bulk contacts 37 or top contacts 38. By the arrangement shown in FIG. 13, a surrounded drain architecture may be realized.

[0122] While some embodiments have been illustrated and described in detail in the appended drawings and the foregoing description, such illustration and description are to be considered illustrative and not restrictive. Other variations to the disclosed embodiments can be understood and effected in practicing the claims, from a study of the drawings, the disclosure, and the appended claims. The mere fact that certain measures or features are recited in mutually different dependent claims does not indicate that a combination of these measures or features cannot be used. Any reference signs in the claims should not be construed as limiting the scope.