Vertical bidirectional insulated gate turn-off device

Abstract

A vertical bidirectional insulated gate turn-off (IGTO) device includes a top half formed over a top surface of a substrate and a bottom half formed over the bottom surface of the substrate. A top electrode is formed over the top half, and a bottom electrode is formed over the bottom half. The layered structure forms vertical NPN and PNP transistors. Each half includes trenched gates. When a first polarity voltage is applied across the electrodes, one of the halves may be turned on by biasing its gates to conduct current between the top and bottom electrodes. When a voltage of an opposite polarity is applied across the electrodes, the other one of the halves may be turned on by biasing its gates to conduct current between the two electrodes. In one embodiment, biasing the gates increases the beta of the NPN transistor to turn on the device.

Claims

1. A bidirectional insulated gate turn-off device formed as a die comprising: a substrate having a first surface and an opposing second surface; a first gate-controlled portion formed over the first surface of the substrate, the first gate-controlled portion comprising: a first semiconductor layer of a first conductivity type formed over the first surface; a second semiconductor layer of a second conductivity type formed over the first semiconductor layer; a third semiconductor layer of the first conductivity type formed over the second semiconductor layer; a first plurality of insulated gate regions within trenches formed at least within the second semiconductor layer, wherein the first plurality of insulated gate regions within the trenches terminates within the second semiconductor layer; and a first electrode electrically contacting the second semiconductor layer and the third semiconductor layer; a second gate-controlled portion formed over the second surface of the substrate, the second gate-controlled portion comprising: a fourth semiconductor layer of the first conductivity type formed over the second surface; a fifth semiconductor layer of the second conductivity type formed over the fourth semiconductor layer; a sixth semiconductor layer of the first conductivity type formed over the fifth semiconductor layer; a second plurality of insulated gate regions within trenches formed at least within the fifth semiconductor layer, wherein the second plurality of insulated gate regions within the trenches terminates within the fifth semiconductor layer; and a second electrode electrically contacting the fifth semiconductor layer and the sixth semiconductor layer, wherein conduction between the first electrode and the second electrode, while a voltage of a first polarity is coupled across the first electrode and the second electrode, is achieved by applying a gate voltage to the first plurality of insulated gate regions; and wherein conduction between the first electrode and the second electrode, while a voltage of a second polarity, opposite to the first polarity, is coupled across the first electrode and the second electrode, is achieved by applying the gate voltage to the second plurality of insulated gate regions.

2. The device of claim 1 wherein the substrate is of the second conductivity type.

3. The device of claim 1 wherein the substrate is of the first conductivity type.

4. The device of claim 1 wherein a vertical structure of NPN and PNP transistors is formed within the device.

5. The device of claim 4 wherein a first voltage applied to the first plurality of insulated gate regions increases a beta of a first one of the NPN and PNP transistors to conduct current in a first direction between the first electrode and the second electrode.

6. The device of claim 5 wherein a second voltage applied to the second plurality of insulated gate regions increases a beta of a second one of the NPN and PNP transistors to conduct current in a second direction between the first electrode and the second electrode.

7. The device of claim 1 wherein the first conductivity type is an n-type and the second conductivity type is a p-type.

8. The device of claim 1 wherein the second semiconductor layer is a well, and the fifth semiconductor layer is a well.

9. The device of claim 1 wherein the third semiconductor layer is more highly doped than the first semiconductor layer, and the sixth semiconductor layer is more highly doped than the fourth semiconductor layer.

10. The device of claim 1 wherein the second gate-controlled portion is a mirror image of the first gate-controlled portion.

11. The device of claim 1 wherein the third semiconductor layer is between some of the insulated gate regions in the first plurality of insulated gate regions but not between all of the insulated gate regions in the first plurality of insulated gate regions, and wherein the sixth semiconductor layer is between some of the insulated gate regions in the second plurality of insulated gate regions but not between all of the insulated gate regions in the second plurality of insulated gate regions.

12. The device of claim 11 wherein areas where the third semiconductor layer is between the insulated gate regions in the first plurality of insulated gate regions oppose areas where the sixth semiconductor layer is not between the insulated gate regions in the second plurality of insulated gate regions, and wherein areas where the sixth semiconductor layer is between the insulated gate regions in the second plurality of insulated gate regions oppose areas where the third semiconductor layer is not between the insulated gate regions in the first plurality of insulated gate regions.

13. The device of claim 12 wherein there are no insulated gate regions in the first plurality of insulated gate regions that oppose the areas where the sixth semiconductor layer is between the insulated gate regions in the second plurality of insulated gate regions, and wherein there are no insulated gate regions in the second plurality of insulated gate regions that oppose the areas where the third semiconductor layer is between the insulated gate regions in the first plurality of insulated gate regions.

14. The device of claim 1 wherein the first electrode acts as an anode electrode and the second electrode acts as a cathode electrode when a voltage applied across the first electrode and the second electrode is of a first polarity, and wherein the first electrode acts as a cathode electrode and the second electrode acts as an anode electrode when the voltage applied across the first electrode and the second electrode is of a second polarity.

15. The device of claim 1 wherein the first plurality of insulated gate regions are aligned with the second plurality of insulated gate regions.

16. The device of claim 1 wherein the first plurality of insulated gate regions are not aligned with the second plurality of insulated gate regions.

17. The device of claim 1 wherein the first electrode electrically contacts the second semiconductor layer via a highly doped region of the second conductivity type formed in the second semiconductor layer, and wherein the second electrode electrically contacts the fifth semiconductor layer via a highly doped region of the second conductivity type formed in the fifth semiconductor layer.

18. The device of claim 1 wherein the second semiconductor layer is a first well region formed by diffusing dopants of the second conductivity type into the first semiconductor layer, and wherein the fifth semiconductor layer is a second well region formed by diffusing dopants of the second conductivity type into the fourth semiconductor layer.

19. The device of claim 1 further comprising: a first vertical p-channel MOSFET formed in the first gate-controlled portion; and a second vertical p-channel MOSFET formed in the second gate-controlled portion, wherein the first vertical p-channel MOSFET and the second vertical p-channel MOSFET aid in device turn-off when the first plurality of insulated gate regions or the second plurality of insulated gate regions is taken sufficiently negative.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a cross-sectional view of an edge of a prior art IGTO device that only conducts in a single direction.

(2) FIG. 2 is a cross-sectional view of a portion of an integrated, vertical bidirectional IGTO device, in accordance with one embodiment of the invention, where a top half and a bottom half are mirror images with a center p+ substrate.

(3) FIG. 3 is a cross-sectional view of a portion of an integrated, vertical bidirectional IGTO device, in accordance with another embodiment of the invention, where a top half and a bottom half are mirror images with a center n substrate.

(4) FIG. 4 is a cross-sectional view of a portion of an integrated, vertical bidirectional IGTO device, in accordance with another embodiment of the invention, where there are gaps in the n+ layer between certain trenched gates so electrons are not injected in those regions, and where the regions that do not inject electron face regions that do inject electrons.

(5) FIG. 5 is a cross-sectional view of a portion of an integrated, vertical bidirectional IGTO device, in accordance with another embodiment of the invention, where regions that do not inject electrons do not contain trenched gates or n+ regions.

(6) FIG. 6 is a perspective view of a top semiconductor surface of a non-singulated wafer during processing of the bidirectional IGTO device, showing the active area (inner cells) and a termination area for individual IGTO devices formed in the wafer.

(7) FIG. 7 illustrates a prior art structure from the inventors' U.S. Pat. Re47,072.

(8) Elements that are similar or identical in the various figures are labeled with the same numeral.

DETAILED DESCRIPTION

(9) FIG. 2 illustrates a portion of an integrated, vertical bidirectional IGTO device 60 in accordance with one embodiment of the invention. Elements labelled the same in FIGS. 1 and 2 may be similar or equivalent.

(10) Gate electrodes 62 and 62A for the upper and lower halves of the IGTO device 60 may be the same as the gate electrode 44 in FIG. 1, where somewhere on the die, such as near the edges, a metal gate electrode contacts a trench filled with the conductive gate material (e.g., doped polysilicon), and that conductive gate material is part of an interconnected mesh of vertical gates.

(11) In one embodiment, the gate trenches 64 (filled with conductive material 38) are formed as parallel trenches that are electrically connected together at both ends by a perpendicular trench acting as a bus for applying the gate voltage to all the gates. A metal gate electrode (such as electrode 44 in FIG. 1) is electrically connected to the bus trench along an edge of the die.

(12) In another embodiment, the gate trenches form closed squares or hexagons in an interconnected mesh.

(13) A thin gate oxide layer 39 insulates the gate material 38 from the p-well 36.

(14) An n+ layer 40 overlies the p-well 36 and extends between the trenches 64.

(15) A metal top electrode 66 can be a cathode or anode electrode, depending on the polarity of the voltage. The electrode 66 contacts the n+ layer between the dielectric regions 46. At certain locations, outside of the cross-section, there is an opening in the n+ layer 40 where the top electrode 66 contacts the p-well 36. This electrical connection is represented by the schematic connection 68. A p+ contact region may be formed in the p-well 36 for ohmic contact with the top electrode 66.

(16) The p-well 36 is formed in/over an n-epi layer 50. The p-well 36 may be formed by diffusion into the n-epi layer 50 or doped in-situ while being grown. (If doped in-situ, a termination trench may be used.) In either case, the p-well 36 is referred to herein as a layer over the n-epi layer 50 since it extends across the die except for the termination region around the perimeter of the die.

(17) The n-epi layer 50 is formed over an optional, more highly doped n-buffer layer 70. The n-buffer layer 70 and the upper semiconductor layers are epitaxially grown over the p+ substrate 72.

(18) The relative dopant concentrations in the various semiconductor layers are shown on the right side of FIG. 2.

(19) A substantially mirror image structure is formed on the opposite surface of the p+ substrate 72. The bottom half components are labeled with the same element numbers as the top half but with the suffix A. Some misalignment in the opposing structures is acceptable and is shown in FIG. 2.

(20) The bottom half may be formed by flipping the wafer after every process step, or may be formed after the top half is formed.

(21) One method for forming the top half is described below, and the bottom half is formed to have identical characteristics.

(22) The starting p+ substrate 72 may have a dopant concentration of 110.sup.18 to 210.sup.19 cm.sup.3. The thickness may range between 100-725 microns depending on the maximum operating voltage of the device, such as between 600-1200 volts.

(23) To reduce the injection of holes into the n epi layer 50 from the p+ substrate 72 when the device is off, the n-type buffer layer 70 is grown with a dopant concentration higher than that of the n epi layer 50. The n-type buffer layer 70 may be grown to a thickness of 3-10 microns thick and has a dopant concentration between about 10.sup.16 to 510.sup.18 cm.sup.3.

(24) The n epi layer 50 is grown to a thickness of 40-70 microns (for a 600V device) and has a doping concentration between about 510.sup.13 to 510.sup.14 cm.sup.3. This dopant concentration can be obtained by in-situ doping during epi growth.

(25) The p-well 36 is then formed by masking and boron dopant implantation. The peak doping in the p-well 36 can be, for example, 10.sup.16-10.sup.18 cm.sup.3. The depth of the p-well 36 depends on the maximum voltage of the device and may be between 1.0-12 microns, but deeper than the trench.

(26) In one embodiment, the n+ layer 40 is formed by an implant of arsenic or phosphorus at an energy of 10-150 keV and an area dose of 510.sup.13 to 10.sup.16 cm.sup.2, to create a dopant concentration exceeding 10.sup.19 cm.sup.3. In one embodiment, the n+ layer 40 has a depth of 0.05-2.0 microns. A deeper, lower doped, n-type layer may additionally be formed adjacent to the n+ layer 40/40A to improve the breakdown voltage.

(27) Either before or after the implant which forms the shallow n+ layer 40, trenches 64 are etched in the active areas using RIE. In one embodiment, the trenches 64 can be, for example, 1-10 microns deep. The minimum lateral trench widths are constrained by lithographic and etching limitations. Trench widths 1 micron or less are preferred.

(28) After the trenches 64 are etched, a gate oxide layer 39 is grown on the sidewalls and bottoms of the trenches 64 to, for example, 0.05-0.15 microns thick. Conductive material 38, such as heavily doped polysilicon or undoped polysilicon that is subsequently doped, fills the trenches 64 and is planarized to form the gate regions in all the cells.

(29) A contact mask opens the dielectric (e.g., oxide) layer 46 above the selected regions on the top surface to be contacted by metal electrodes.

(30) Various metal layers are then deposited to form the gate electrodes 62/62A and the top and bottom electrodes 66/66A.

(31) In one embodiment, the epi layers are deposited on both surfaces of the substrate 72 before subsequent processing occurs. This process flow requires starting wafers polished on both surfaces.

(32) The operation of the bidirectional IGTO device 60 is the same as described with respect to FIG. 1, except that the top half and bottom half may be independently controlled to conduct current in either direction depending on the voltage polarities applied to the top and bottom electrodes 66 and 66A. Turn-on of either half may be accomplished with a gate voltage of 2-8 volts.

(33) In one embodiment, the bidirectional IGTO device 60 switches an AC current, where the gate control coincides with the particular polarity of the voltage. The IGTO device 60 is particularly useful as a high power AC motor control.

(34) FIG. 3 illustrates an IGTO device 80 that is identical to the device of FIG. 2 except that all layers are formed over both surfaces of an n-substrate 82 rather than over a p+ substrate. The relative doping profiles are shown on the right side of FIG. 3. A deeper n-type region may also be included adjacent to the n+ layers 40/40A.

(35) In all embodiments, the trenches of both halves are preferably aligned for maximum efficiency. However, some misalignment due to mask tolerances is acceptable, and shown in FIGS. 2 and 3, since carriers spread as they flow away from the locations where the electrodes 66/66A contact the n+ layer 40/40A.

(36) In another embodiment, two wafers are bonded together to form the top and bottom halves of the bidirectional IGTO device. The bond may be by a conductive adhesive or electrostatic bonding may be used. The bonded wafers are then singulated.

(37) In the embodiments shown, the trenches only extend into the p-well 36 and not into the n-epi layer 50.

(38) FIG. 4 shows a device 83 similar to FIG. 3 except that the n+ layers 40 and 40A are omitted between some trenches to form gaps 84 and 84A where the p-well 36/36A contacts the associated electrode 66/66A. P+ regions 85/85A in the p-well 36/36A surface provide lower contact resistance to the p-well 36/36A. The areas with the n+ layer 40/40A between the trenches 64/64A inject electrons (depending on the polarity of the voltage applied to the electrodes 66 and 66A). The gaps 84/84A do not inject electrons. The gaps 84/84A that do not inject electrons on one surface face the n+ layers 40/40A that do inject electrons on the opposite surface. The number of gaps 84/84A (non-injecting areas) approximately equals the number of n+ layer 40/40A regions (injecting areas) for symmetrical performance of the device. This structure improves efficiency by creating shorter vertical paths for current flow, and the gaps 84/84A form more efficient collectors for the vertical PNP transistor.

(39) Assuming a positive voltage is applied to the top electrode 66, a negative voltage is applied to the bottom electrode 66A, and the device is turned on, electrons will be injected from the bottom n+ layer 40A between the trenches 64A, and the electrons will create a vertical current through the upper p-well 36 to be conducted by the upper electrode 66 where it contacts the p-well 36. The opposite current flows when the polarities are reversed and the other gates are properly biased.

(40) FIG. 5 illustrates a device 90 similar to FIG. 4 except that the regions that do not inject electrons do not contain any trenches or n+ layer regions. This variation increases the effective collector area for the PNP transistor (where the p-well 36/36A contacts the electrode 66/66A) to further improve efficiency.

(41) FIG. 6 is a perspective view of the semiconductor surface of a non-singulated wafer 90 showing scribe lines 92 around each IGTO device die. The dies include a central active area 94 and a peripheral termination region 96. The termination region 96 includes guard rings, such as shown in FIG. 1.

(42) FIG. 7 illustrates a prior art IGTO device from the inventors' U.S. Pat. Re47,072, incorporated herein by reference. Such a structure may be made bi-directional by fabricating the IGTO device on both sides of the substrate. Any of the techniques described herein may be used to modify the bi-directional structure to improve its performance, such as the techniques described with respect to FIGS. 4 and 5. The IGTO device of FIG. 7 allows the device to be turned off after latch-up with a much less negative gate voltage, compared to the prior art described in U.S. Pat. Re47,072. The cells are formed to have upper p+ regions on both sides of the n+ source region that extend vertically below the n+ source region, and an n layer is formed between the p-well and the upper p+ regions. The n+ source regions and the upper p+ regions are shorted by the cathode electrode. The p+ regions, the n layer, and the p-well form a vertical p-channel MOSFET, where the n-layer adjacent the vertical gate forms the body. The p-channel MOSFET turns on with a slightly negative gate voltage (a threshold voltage) relative to the cathode electrode (the p+ region acts as a source for the p-channel MOSFET). Turning on the p-channel MOSFET shorts (to an extent) the base-emitter of the wide-base vertical NPN transistor to turn it off and to thereby turn off the IGTO device, even when there is latch-up. In the event there is no latch-up, the p-channel MOSFET is not required to help turn off the device, so simply shorting the gate to the cathode electrode will shut off the device.

(43) The IGTO devices in any of the figures may have the polarities of the materials reversed.

(44) While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications as fall within the true spirit and scope of this invention.