Flat no-lead packages with electroplated edges

Abstract

A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals. A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the back side of the terminals each include a contact region which lacks the plating layer.

Claims

1. A packaged semiconductor flat no-lead device (packaged semiconductor device), comprising: a flat no-lead lead frame having a semiconductor die including bond pads thereon mounted on a die pad of said lead frame with bond wires between said bond pads and terminals of said lead frame, and plastic encapsulation except on a back side of said lead frame to expose said die pad to provide an exposed thermal die pad and to expose a back side of said terminals and side walls of said terminals; a stack of plating layers on said back side and on said exposed side walls of said terminals, said stack of plating layers includes nickel, palladium, and gold; wherein said exposed thermal die pad and said back side of said terminals each include a contact region which lacks said stack of plating layers.

2. The packaged semiconductor device of claim 1, wherein said plastic encapsulation is at a first width on a top portion of said packaged semiconductor device and at a second width at a bottom of said packaged semiconductor device, and wherein said first width is greater than said second width to provide a side wall step along an edge of said plastic encapsulation.

3. The packaged semiconductor device of claim 1, wherein said lead frame includes a quad-flat no-lead (QFN) or a dual-flat no-lead (DFN).

4. The packaged semiconductor device of claim 1, wherein said lead frame includes copper or a copper alloy.

5. The packaged semiconductor device of claim 1, wherein said contact region is 0.8 mil (0.0206 mm) to 5 mil (0.127 mm) in diameter.

6. The packaged semiconductor device of claim 5, wherein said contact region is 1 to 2 mils.

7. The packaged semiconductor device of claim 1, wherein said semiconductor die is mounted on the die pad with die attach material.

8. The packaged semiconductor device of claim 7, wherein said die attach material is epoxy.

9. A packaged semiconductor flat no-lead device (packaged semiconductor device), comprising: a flat no-lead lead frame having a semiconductor die including bond pads thereon mounted on a die pad of said lead frame with bond wires between said bond pads and terminals of said lead frame, and plastic encapsulation except on a back side of said lead frame to expose said die pad to provide an exposed thermal die pad and to expose a back side of said terminals and side walls of said terminals; a single plating layer on said back side and on said exposed side walls of said terminals; wherein said exposed thermal die pad and said back side of said terminals each include a contact region which lacks said single plating layer.

10. The packaged semiconductor device of claim 9, wherein said plastic encapsulation is at a first width on a top portion of said packaged semiconductor device and at a second width at a bottom of said packaged semiconductor device, and wherein said first width is greater than said second width to provide a side wall step along an edge of said plastic encapsulation.

11. The packaged semiconductor device of claim 9, wherein said lead frame includes a quad-flat no-lead (QFN) or a dual-flat no-lead (DFN).

12. The packaged semiconductor device of claim 9, wherein said lead frame includes copper or a copper alloy.

13. The packaged semiconductor device of claim 9, wherein said contact region is 0.8 mil (0.0206 mm) to 5 mil (0.127 mm) in diameter.

14. The packaged semiconductor device of claim 13, wherein said contact region is 1 to 2 mils.

15. The packaged semiconductor device of claim 9, wherein said semiconductor die is mounted on the die pad with die attach material.

16. The packaged semiconductor device of claim 15, wherein said die attach material is epoxy.

17. A packaged semiconductor flat no-lead device (packaged semiconductor device), comprising: a flat no-lead lead frame having a semiconductor die including bond pads thereon mounted on a die pad of said lead frame with bond wires between said bond pads and terminals of said lead frame, and plastic encapsulation except on a back side of said lead frame to expose said die pad to provide an exposed thermal die pad and to expose a back side of said terminals and side walls of said terminals; a stack of two plating layers on said back side and on said exposed side walls of said terminals; wherein said exposed thermal die pad and said back side of said terminals each include a contact region which lacks said stack of two plating layers.

18. The packaged semiconductor device of claim 17, wherein said plastic encapsulation is at a first width on a top portion of said packaged semiconductor device and at a second width at a bottom of said packaged semiconductor device, and wherein said first width is greater than said second width to provide a side wall step along an edge of said plastic encapsulation.

19. The packaged semiconductor device of claim 17, wherein said lead frame includes a quad-flat no-lead (QFN) or a dual-flat no-lead (DFN).

20. The packaged semiconductor device of claim 17, wherein said contact region is 0.8 mil (0.0206 mm) to 5 mil (0.127 mm) in diameter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, wherein:

(2) FIG. 1 is a flow chart that shows steps in an example method for forming electroplated terminal finishes including electroplated edges for flat no-lead packages, according to an example embodiment.

(3) FIG. 2A is a backside and a cross section view of a panel of in-process flat no-lead packages after plastic encapsulation, and FIG. 2B is a cross section view of a single unit from the panel, according to an example embodiment.

(4) FIGS. 3A and 3B is a backside and a cross section view of a panel of in-process flat no-lead packages after backside partial sawing, respectfully, according to an example embodiment.

(5) FIG. 4 is a cross section view of a panel of in-process flat no-lead packages after backside wirebonding, according to an example embodiment.

(6) FIG. 5A is a cross section view of a panel of in-process flat no-lead packages after electroplating the terminals along with their edges, according to an example embodiment.

(7) FIG. 5B Is a cross section view of a panel of in-process flat no-lead packages after electroplating the terminals along with their edges with 2 plating layers, according to an example embodiment.

(8) FIG. 6 is a cross section view of a panel of in-process flat no-lead packages depicting the shearing off the wirebonds without damaging the plating layer on the terminals, and the resulting wirebond contact regions on the exposed thermal die pad (exposed thermal pad) and back side of the terminals which lack the plating layer, according to an example embodiment.

(9) FIG. 7A is a cross section view of a panel of in-process flat no-lead packages depicting the result after finishing with a smaller saw that runs all the way through the plastic encapsulation to provide package singulation with 3 singulated package units shown.

(10) FIG. 7B is a cross section view of a panel of one of the singulated package units shown in FIG. 7A Inverted 180 degrees.

DETAILED DESCRIPTION

(11) Example embodiments are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some Illustrated acts or events may not be required to implement a methodology in accordance with this disclosure.

(12) Also, the terms coupled to or couples with (and the like) as used herein without further qualification are intended to describe either an Indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection can be through a direct electrical connection where there are only parasitics in the pathway, or through an indirect electrical connection via Intervening items Including other devices and connections. For indirect coupling, the intervening item generally does not modify the information of a signal but may adjust its current level, voltage level, and/or power level.

(13) FIG. 1 is a flow chart that shows steps in an example method 100 for forming electroplated terminal finishes Including electroplated edges for packaged flat no-lead packages, according to an example embodiment Step 101 comprises providing a lead frame sheet (or lead frame panel) including a plurality of joined flat no-lead lead frames (lead frames) each having a semiconductor die Including bond pads thereon mounted on a die pad with bond wires between the bond pads and terminals of the lead frames.

(14) The lead frames typically comprise copper or a copper alloy. Plastic encapsulation is Included except on a back side of the lead frame sheet to expose a back side of the die pad to provide an exposed thermal pad and to expose a back side of the terminals. The lead frames can comprise quad-flat no-lead (QFN) or dual-flat no-lead (DFN). FIGS. 2A and 2B show a backside view of a panel 200 showing six (6) in-process flat no-lead packages after plastic encapsulation showing the plastic 211, and the exposed die pad 205 and exposed terminals 208, and FIG. 2B shows a cross section view of a single unit 250 from the panel, according to an example embodiment. Saw lanes for step 102 described below are shown as 213. The semiconductor die is shown as 225 and the die attach material (e.g., an epoxy) as 226. Bond wires 229 are shown connecting bond pads on the top surface of semiconductor die 225 to the terminals 208.

(15) Step 102 comprises partial sawing in the saw lanes beginning from the back side through the terminals ending with saw lines having a line width terminating within the plastic encapsulation to provide exposed side walls of the terminals and exposed side walls of the plastic encapsulation. The partial sawing can comprise mechanical sawing or laser sawing. FIGS. 3A and 3B show backside and a cross section view, respectively, of a panel 300 of in-process flat no-lead packages after backside partial sawing using the saw lanes 213 shown in FIG. 2A to form saw lines 310, according to an example embodiment.

(16) Step 103 comprises shorting together (e.g., using a jig (essentially a bed of nails), jumper, or wire bonding) all the exposed thermal pad(s) and exposed back side of the terminals to form electrically Interconnected metal surfaces (Interconnected surfaces). FIG. 4 is a cross section view of a panel 400 of in-process flat no-lead packages after backside wirebonding, according to an example embodiment. Wirebonds to provide the electrically interconnected surfaces are shown as bond wires 429.

(17) Step 104 comprises electroplating the interconnected surfaces with a solder wetable metal or metal alloy plating layer on the back side and on the exposed side walls of the terminals. Electroplating as known in the art is a process that uses electrical current from a power supply to reduce dissolved metal cations in a plating solution so that they form a metal coating on the desired surface to be plated that is configured as a cathode. FIG. 5A is a cross section view of a panel 500 of in-process flat no-lead packages after electroplating a plating layer 520 on the terminals being the exposed die pads 205 and exposed terminals 208, according to an example embodiment.

(18) Although the plating layer 520 is shown as a single layer, the plating layer can comprise a stack of different plating layers, such as the stack of plating layers in one particular embodiment being NiPdAu (3 layers). FIG. 5B is a cross section view of a panel of in-process flat no-lead packages after electroplating the terminals along with their edges with 2 plating layers shown 520b on 520a, according to an example embodiment. Because of the bond wires 429 or other shorting structures being present during the electroplating the exposed thermal pad 205 and back side of the terminals 208 each Include a contact region (see contact region 615 shown in FIG. 6) having an area of about that of the bond wire which lacks the plating layer. The contact region is generally 0.8 mil (0.0206 mm) to 5 mil (0.127 mm) in diameter, and is typically 1 to 2 mils in diameter.

(19) Step 105 comprises decouping the interconnected surfaces. When the shorting together comprises using bond wires, the decoupling can comprise using a metal brush for shearing off the bond wires. In the case of a jig, the jig is lifted up to remove the contacts of its nails or probes with the terminals. FIG. 6 is a cross section view of a panel 600 of in-process flat no-lead packages depicting the shearing off the bond wires 429 without damaging plating layer 520 on the terminals, according to an example embodiment. The exposed thermal pad 205 and back side of the terminals 208 can be seen to each include a contact region 615 which lacks the plating layer 520.

(20) Step 106 comprises a second sawing in the saw lanes to finish sawing beginning from the bottom of the saw lines through the plastic encapsulation 211 to provide singulation to form a plurality of packaged semiconductor devices. FIG. 7A is a cross section view of a panel 700 of in-process flat no-lead packages depicting the result after finishing with a smaller saw that runs all the way through the plastic encapsulation 211 to provide package singulation with 3 singulated package units shown. FIG. 7B is a cross section view of a panel of one of the singulated package units shown in FIG. 7A Identified as 750 inverted 180 degrees to have its top side up.

(21) Advantages of disclosed methods and packaged semiconductor devices therefrom include the elimination of tin whiskering. Side wetting is also provided to enable a visual solder inspection Instead of having to conventionally rely on an x-ray inspection for electrolytic processes.

(22) Disclosed embodiments can be integrated into a variety of assembly flows to form a variety of different semiconductor Integrated circuit (IC) devices and related products. The assembly can comprise single semiconductor die or multiple semiconductor die, such as package on package (PoP) configurations comprising a plurality of stacked semiconductor die. A variety of package substrates may be used. The semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the semiconductor die can be formed from a variety of processes including bipolar, insulated-gate bipolar transistor (IGBT), CMOS, BiCMOS and MEMS.

(23) Those skilled in the art to which this disclosure relates will appreciate that many other embodiments and variations of embodiments are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of this disclosure.