Chip Assembly and Method of Manufacturing Thereof

Abstract

A chip assembly includes a carrier and a metal grid array having an opening. The metal grid array is attached to the carrier by an attachment material. The metal grid array and the carrier define a cavity which is formed by the opening and the carrier. The chip assembly further includes an electronic chip mounted in the cavity.

Claims

1. A method of manufacturing a chip assembly, the method comprising: providing a carrier; providing a continuous layer of an attachment material on the carrier, the attachment material comprising a solder material or a sinter material; providing a metal grid array comprising an opening; attaching the metal grid array to the carrier by the attachment material such that the metal grid array and the carrier define a cavity which is formed by the opening and the carrier; and mounting an electronic chip in the cavity by the attachment material such that the continuous layer of attachment material extends below the metal grid array and the electronic chip.

2. The method of claim 1, wherein the attachment material comprises silver, copper, tin, antimony and/or indium and/or alloys thereof as the sinter material, or at least one of a lead-tin solder, nickel-gold solder, tin-silver solder, tin-indium-solder, tin-silver-copper-solder, palladium-gold solder, nickel-palladium-gold-silver solder as the solder material.

3. The method of claim. 1, wherein the metal grid array is a stamped metal foil, and wherein the opening is formed by stamping.

4. The method of claim 1, wherein the carrier is a leadframe or a direct copper bonding substrate.

5. The method of claim. 1, wherein the metal grid array comprises copper with a coating layer of nickel or nickel phosphor.

6. The method of claim 1, wherein mounting the electronic chip comprises: providing a die attachment liquid or a die attachment film in the cavity; and placing the electronic chip in the die attachment liquid or onto the die attachment film.

7. The method of claim 1, wherein mounting the electronic chip comprises pressing the electronic chip and the carrier towards each other at a temperature in a range between 200 C. and 400 C.

8. The method of claim 1, wherein mounting the electronic chip comprises pressing both, the electronic chip and the metal grid array, and the carrier towards each other at a temperature in a range between 200 C and 400 C.

9. The method of claim 1, wherein the electronic chip comprises a mounting surface facing in a direction towards the carrier.

10. The method of claim 1, further comprising aligning the carrier and the metal grid array with respect to each other.

11. The method of claim 1, further comprising arranging a laminate over the electronic chip.

12. The method of claim 1, wherein the metal grid array comprises a plurality of openings, wherein the metal grid array and the carrier define a plurality of cavities, and wherein the method further comprises: singulating the plurality of cavities after mounting a separate electronic chip in each cavity of the plurality of cavities.

13. A chip assembly, comprising: a carrier; a metal grid array comprising an opening and being attached to the carrier by an attachment material, the metal grid array and the carrier defining a cavity which is formed by the opening and the carrier, the attachment material comprising a solder material or a sinter material; and an electronic chip mounted in the cavity by the attachment material, the attachment material forming a continuous layer under the metal grid array and the chip.

14. The chip assembly of claim 13, wherein the attachment material is in a lateral space between the metal grid array and the chip.

15. The chip assembly of claim 13, wherein the carrier is one of a leadframe, a printed circuit board and a direct copper bonding substrate.

16. The chip assembly of claim 13, wherein the metal grid array is a stamped metal foil.

17. The chip assembly of claim 13, wherein the electronic chip is a power semiconductor device comprising at least one outer metallization layer.

18. The chip assembly of claim 13, wherein the attachment material comprises a diffusion solder material.

19. The chip assembly of claim 13, wherein at least one of the carrier and the metal grid comprises copper with a coating layer of nickel or nickel phosphor.

20. The chip assembly of claim 13, wherein: the electronic chip comprises a front surface facing away from the carrier; the metal grid array comprises a front surface facing away from the carrier; and the front surface of the electronic chip and the front surface of the metal grid array are level with respect to each other.

21. The chip assembly of claim 13, further comprising a laminate arranged over the electronic chip.

22. The chip assembly of claim 13, wherein at least one of the carrier and the metal grid array comprises at least one alignment element for alignment and/or fixation of the carrier and the metal grid array with respect to each other.

23. The chip assembly of claim 22, wherein the at least one alignment element incudes at least one of an alignment pin, a protrusion, a groove, and a hole.

24. The chip assembly of claim 13, wherein the metal grid array comprises a plurality of openings, wherein the metal grid array and the carrier define a plurality of cavities, and wherein a separate electronic chip is mounted in each cavity of the plurality of cavities.

25. A method of manufacturing a chip assembly, the method comprising: providing a carrier; providing a metal grid array comprising an opening; attaching the metal grid array to the carrier by an attachment material which comprises a solder material or a sinter material, the metal grid array and the carrier defining a cavity which is formed by the opening and the carrier; and mounting an electronic chip in the cavity.

26. The method of claim 25, wherein the metal grid array comprises a layer of the attachment material, and wherein providing the metal grid array comprises providing the metal grid array with the layer of attachment material thereon.

27. The method of claim 25, wherein the electronic chip has a further attachment material on the electronic chip, and wherein mounting the electronic chip in the cavity comprises mounting the electronic chip with further attachment material in the cavity.

28. The method of claim 25, wherein the metal grid array comprises a plurality of openings, wherein the metal grid array and the carrier define a plurality of cavities, and wherein the method further comprises: singulating the plurality of cavities after mounting a separate electronic chip in each cavity of the plurality of cavities.

29. A chip assembly, comprising: a carrier; a metal grid array comprising as opening and being attached to the carrier by as attachment material, the attachment material comprising a solder material or a sinter material, the metal grid array and the carrier defining a cavity which is formed by the opening and the carrier; and as electronic chip mounted in the cavity.

30. The chip assembly of claim 29, wherein the metal grid array comprises a plurality of openings, wherein the metal grid array and the carrier define a plurality of cavities, and wherein a separate electronic chip is mounted in each cavity of the plurality of cavities.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0047] The accompanying drawings are included to provide a further understanding of exemplary embodiments of the herein disclosed subject matter and constitute a part of the specification. In particular, the accompanying drawings illustrate exemplary combinations of embodiments of the herein disclosed subject matter.

[0048] In the drawings:

[0049] FIG. 1 to FIG. 6 illustrate respective cross-sectional views of structures obtained during manufacturing of a chip assembly shown in FIG. 6, according to embodiments of the herein disclosed subject matter.

[0050] FIG. 7 illustrates a part of the chip assembly of FIG. 6 in greater detail.

[0051] FIG. 8 shows the chip assembly in an alternative manufacturing state according to embodiments of the herein disclosed subject matter.

[0052] FIG. 9 to FIG. 11 illustrate cross-sectional views of structures obtained during manufacturing of a chip assembly which are alternative to the manufacturing illustrated in FIG. 2 to FIG. 4

DETAILED DESCRIPTION

[0053] The illustration in the drawing is schematic and not necessarily drawn to scale,

[0054] Before exemplary embodiments will be described in more detail referring to the Figures, some general considerations will be summarized based on which exemplary embodiments have been developed.

[0055] FIG. 1 to FIG. 6 illustrate cross-sectional views of structures obtained during manufacturing of a chap assembly shown in FIG. 6, according to embodiments of the herein disclosed subject matter.

[0056] FIG. 1 illustrates a part of a chip assembly 100 according to embodiments of the herein disclosed subject matter.

[0057] In accordance with an embodiment, a carrier 102 of chip assembly 100 is provided and a layer of an attachment material 104, e.g. a tin layer, a layer of tin alloy, silver, silver alloy, gold, or gold alloy, e.g. a layer of a gold-tin alloy or a gold-silver alloy, is provided on the carrier 102. In accordance with an embodiment, the carrier 102 is a lead frame, e.g. a copper lead frame which according to an embodiment may be coated (or partially coated) with a coating material such as nickel or nickel phosphor. In other embodiments, the substrate 102 is a DCB substrate or a PCB. In accordance with an embodiment, the layer of attachment material 104 is provided on the carrier 102 by plating.

[0058] FIG. 2 shows the chip assembly 100 in a further manufacturing stage according to embodiments of the herein disclosed subject matter.

[0059] In accordance with an embodiment, a metal grid array 106 is provided over the carrier 102. According to an embodiment, the metal grid array 106 is provided on the layer of attachment material 104. According to an embodiment, the attachment material 104 is provided on the carrier 102 as a homogeneous layer. The attachment material can be applied by any suitable process e.g. a wet chemical method, electroplating, electroless plating, physical vapor deposition, chemical vapor deposition, etc.

[0060] Alternatively (not shown in FIG. 2), the attachment material 104 may also be provided on the metal grid array 106. However, this has the disadvantage that a further attachment material may be needed on the carrier in the region of the opening of the metal grid array. In accordance with an embodiment, the metal grid array 106 is a metal foil and comprises a plurality of openings 108. In accordance with an embodiment, the metal grid array 106 is a stamped copper foil.

[0061] FIG. 3 shows the chip assembly 100 in a further manufacturing stage according to embodiments of the herein disclosed subject matter.

[0062] In accordance with an embodiment, the metal grid array 106 is attached to the carrier 102 by the attachment material 104. Further, the attachment material 104 is also provided on a bottom 110 of a cavity 112 which is defined by the carrier 102 and the metal grid array 106. In accordance with an embodiment, the bottom. 110 is formed by the carrier 102. According to an embodiment, the carrier 102 and the metal grid array 106 are part of a chip base 113.

[0063] Further in accordance with an embodiment, a die attach liquid 114 is provided on the attachment material 104 on the bottom 110 of the cavity 112.

[0064] FIG. 4 shows the chip assembly 100 in a further manufacturing state according to embodiments of the herein disclosed subject matter.

[0065] In accordance with an embodiment, a plurality of electronic chips 116, two of which are shown in. FIG. 4, are placed on the die attach liquid 114 in the associated cavity 112.

[0066] FIG. 5 shows the chip assembly 100 in a further manufacturing stage according to embodiments of the herein disclosed subject matter.

[0067] In accordance with an embodiment, an electronic chip 116 part of a plurality of electronic chips has been placed in each of the cavities 112 which are defined by the carrier 102 and the metal grid array 106.

[0068] In accordance with an embodiment, the chip assembly 100 is placed in a press tool 118 between a first press part 120 and a second press part 122. According to an embodiment, a force indicated by arrows 124 is imposed on the chip assembly 100, the force having a value of at least I newton per square millimeter (N/mm.sup.2). According to an embodiment, the force is in a range between 1 N/mm .sup.2 and 100 N/mm.sup.2, e.g. in a range between 1 N/mm .sup.2 and 20 N/mm.sup.2. In accordance with a further embodiment, the chip assembly 100 is subjected to a high temperature, i.e. heat, indicated by arrows 126 in FIG. 5, e.g. in a reflow oven, the temperature of which exceeds the melting temperature of the applied attachment material 104 According to an embodiment the attachment of the (at least one) chip and the metal grid array on the carrier results in a positive substance jointing (German: stoffschlssige Verbindung).

[0069] According to an embodiment, by heating, 126, the chip assembly to a first temperature the die attach liquid 114 is evaporated from the cavity 112, in particular is evaporated without any residuals in the cavity. In further embodiment, no die attach liquid or the like is used. In other words, in an embodiment, the chip is placed directly on the attachment material (without any further material in-between).

[0070] According to an embodiment, the attachment material is provided also in a lateral space between the metal grid array and the chip. For example, according to an embodiment, by exerting pressure on the chip and hence on the attachment material, a part of the attachment material is pressed into the space between the metal grid array and the chip. A homogeneous thickness of the attachment material and/or a homogeneous pressure on the chip may be seen from an equal distribution of attachment material on a surface of the metal grid array and/or the chip (e.g. from an equal distribution of attachment material in the vicinity of the corners of the opening.

[0071] Further, in accordance with an embodiment the temperature of the chip assembly 100 is raised to a second temperature suitable to attach the chips 116 to the carrier 102 and/or the metal grid array 106 by the attachment material 104. For example, if the if the attachment material 104 is a sinter material, comprising e.g. at least one of silver (Ag), tin (Sn), and copper (Cu), the second temperature is chosen such that sintering process takes place and is completed within a desired time period. If for example the attachment material 104 is a soft solder material, the second temperature is chosen such that the soft solder material liquifies. If for example the attachment material 104 is a diffusion solder material, the second temperature is chosen such that the diffusion solder material forms the desired intermetallic phase within a desired time period.

[0072] FIG. 6 shows the chip assembly 100 in a further manufacturing stage according to embodiments of the herein disclosed subject matter.

[0073] In particular, depending on the attachment material used, at least after cooling down the chip assembly 100 to room temperature the chip assembly 100 comprises the plurality of electronic chips 116 located in the cavities 112 defined by the first part 102 and the second part 106 and attached to the chip base 113.

[0074] FIG. 7 shows a part of the chip assembly 100 of FIG. 6 in greater detail.

[0075] According to an embodiment, the electronic chip 116 is a power semiconductor device which comprises a first load electrode 130 and a second load electrode 132. For example, according to an embodiment the power semiconductor device is a diode. According to the another embodiment, the power semiconductor devices a transistor which further comprises a gate electrode (not shown in FIG. 7) for controlling an electrical conductivity between the first and second load electrode 130, 132.

[0076] According to an embodiment, a laminate 134 is provided over the chip assembly 100 so as to form a package. The laminate 134 may comprise a stack of at least one electrically insulating layer 136 and at least one electrically conductive layer 138, e.g. as shown in FIG. 7. According to an embodiment, the laminate 134, e.g. an insulating layer thereof (e.g. the insulating layer 136) comprises a trough hole 140 extending to the load electrode 130, 132. By providing the electrically conductive layer 138 of the laminate (e.g. a copper layer), the through hole 140 is filled with the material of the conductive layer, thus establishing an electrical contact between the electrically conductive layer 138 and the load electrode 130, 132. According to an embodiment, the electrically conductive layer 138 is provided by plating. According to another embodiment, the laminate 134 is a preformed intermediate element which comprises the at least one electrically insulating layer 136 and at least one electrically conductive layer 138 when being applied to the electronic chip 116 and the chip base 113. In such a case, the filling of the through hole with conductive material is separate from the providing of the electrically conductive layer.

[0077] According to an embodiment, the attachment material 104 may extend into a lateral space 128 between the electronic chip 116 and the chip base 113. In other words, in an embodiment, the attachment material 104 extends into a space 128 between the electronic chip 116 and the metal grid array 106.

[0078] Further FIG. 7 indicates possible singulation lines along which the chip assembly 100 can be singulated. According to an embodiment, the singulation lines 142 extend through the metal grid array 106, e.g. as shown in FIG. 7.

[0079] FIG. 8 shows the chip assembly 100 in an alternative manufacturing state according to embodiments of the herein disclosed subject matter.

[0080] According to an embodiment, no die attach liquid is used, i.e. in the associated cavity 112 the electronic chips 116 are placed directly on the attachment material 104, without an intermediate material in-between. Apart from this feature, FIG. 8 corresponds to FIG. 4.

[0081] FIG. 9 to FIG. 11 illustrate cross-sectional views of structures obtained during manufacturing of a chip assembly which are alternative to the manufacturing illustrated in FIG. 2 to FIG. 4.

[0082] In particular, the method of manufacturing illustrated by FIG. 9 to FIG. 11 differ from FIG. 2 to FIG. 4 in particular in that the layer of an attachment material 104 is provided on the metal grid array 106. Further, in accordance with an embodiment, the attachment material 104 is provided on the electronic chips 116 to allow attachment of the electronic chips on the carrier 102 in the cavities 112.

[0083] The structure illustrated in FIG. 11 may be further processed as illustrated by and described with regard to FIGS. 5 and 6.

[0084] Terms such as first, second, and the like, are used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.

[0085] As used herein, the terms having, containing, including, comprising and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles a, an and the are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0086] It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.

[0087] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Accordingly, the appended claims are intended to include within their scope such processes, processes, machines, manufacture, compositions of matter, means, methods, or steps.

[0088] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.