Device and method for detecting electric potentials

Abstract

A device for detecting electric potentials of the body of a patient has measuring electrode inputs (Y.sub.1, . . . , Y.sub.n) connected with and a plurality of outputs (A.sub.1, . . . , A.sub.n) via amplifiers (Op.sub.1, . . . , Op.sub.n). A summing unit (13) is connected with the outputs and outputs a mean value of the signals (E.sub.1, . . . , E.sub.n) output by the amplifiers. Common mode signals are removed from the signals (E.sub.1, . . . , E.sub.n) by a subtracting unit (19) which subtracts the output of the summing unit, amplified by an amplification factor (1/), from at least a portion of the output of the subtracting unit. The output of the subtracting unit is connected with the inputs of the amplifiers. The subtracting unit amplification factor (1/) and an amplification () of the amplifiers for the output of the subtracting unit are adapted, such that the reciprocal value of the amplification factor (1/) corresponds to the amplifiers amplification ().

Claims

1. A device for detecting the electric potentials of the body of a patient, the device comprising: a plurality of device inputs for connection with measuring electrodes, which measuring electrodes may be placed on the body of a patient; a plurality of amplifiers; a plurality of device outputs, each of the device inputs being connected with one of the device outputs via one of the amplifiers; a summing unit having a summing unit input connected with each of the outputs, the summing unit providing a summing unit output that is a mean value of the signals by the amplifiers; and a subtracting unit connected to the summing unit, the subtracting unit subtracting an output of the summing unit, amplified by an amplification factor, from at least a portion of an output of the subtracting unit, wherein: the output of the subtracting unit is connected with inputs of the amplifiers having an amplifier amplification; and the amplification factor is a reciprocal value of the amplifier amplification.

2. A device in accordance with claim 1, wherein the subtracting unit is configured, such that the output of the summing unit, amplified by an amplification factor, is subtracted from the output of the subtracting unit multiplied by an attenuation factor, which attenuation factor is less than one.

3. A device in accordance with claim 1, wherein: the subtracting unit is comprised of an analog amplifier circuit comprised of an inverting adder and an inverter; and an output of the inverter is connected with the input of the inverting adder and connected with the inputs of the amplifiers.

4. A device in accordance with claim 1, further comprising an impedance converter connected between the output of the subtracting unit and an input of the subtracting unit.

5. A device in accordance with claim 1, wherein the subtracting unit further comprises a low-pass filter at a subtracting unit input, connected to the summing unit, and a low pass filter at a subtracting unit input, connected to the output of the subtracting unit.

6. A device in accordance with claim 1, further comprising: an analog-digital converter; and digital-analog converters, wherein: the summing unit is formed by a digital signal processor; outputs of the amplifiers are connected with inputs of the digital signal processor via the analog-digital converters; the subtracting unit is configured as an analog amplifier circuit; and an output of the digital signal processor is connected with the subtracting unit via the digital-analog converter.

7. A device in accordance with claim 1, further comprising: analog-digital converters; and a digital-analog converter, wherein: the summing unit and the subtracting unit are formed by a digital signal processor; outputs of the amplifiers are connected with inputs of the digital signal processor via the analog-digital converters; and an output of the digital signal processor is connected with the inputs of the amplifiers via the digital-analog converter.

8. A method for detecting electric potentials from signals of a plurality of measuring electrodes, the method comprising: amplifying the signals of the measuring electrodes with amplifiers; forming a mean value signal of signals of outputs of the amplifiers; producing a reference signal by subtracting the mean value signal, amplified by an amplification factor, from at least a portion of the reference signal; feeding the reference signal to inputs of the amplifiers, wherein: the reference signal is amplified by an amplification by the amplifiers; and the amplification of the amplifiers for the reference signal is the reciprocal value of the amplification factor.

9. A method in accordance with claim 8, wherein the reference signal is attenuated before the subtraction by a factor, wherein the factor is less than one.

10. A method in accordance with claim 8, wherein the reference signal and the mean value signal are filtered by a low-pass filter before the subtraction.

11. A device for detecting electric potentials of a body of a patient, the device comprising: a plurality of electrode inputs configured to connect with measuring electrodes; a plurality of amplifiers, each of said plurality of amplifiers being configured to receive a separate electric potential from the body of the patient, said each amplifier also being configured to receive a reference voltage, said each amplifier also being configured to amplify the reference voltage by an amplification factor, said each amplifier also having an amplifier output forming a respective device output; a summing unit connected with each of said amplifier outputs, said summing unit generating a mean value of signals generated by said plurality of amplifiers; a subtracting unit generating the reference voltage and transmitting the reference voltage to said each amplifier, said subtracting unit receiving the mean value from the summing unit, said subtracting unit amplifying the mean value by a reciprocal of the amplification factor to create a correction factor, said subtracting unit subtracting the correction factor from a previous reference voltage to generate a new reference voltage, said subtracting unit transmitting the new reference voltage to said each amplifier to replace the previous reference voltage, said subtracting unit recursively operating to replace the new reference voltage with the previous reference voltage.

12. A device in accordance with claim 11, wherein: the subtracting unit is comprised of an analog amplifier circuit comprised of an inverting adder and an inverter; and an output of the inverter is connected with the input of the inverting adder and connected with the inputs of the amplifiers.

13. A device in accordance with claim 11, further comprising an impedance converter connected between an output and an input of the subtracting unit.

14. A device in accordance with claim 11, wherein the subtracting unit further comprises a low-pass filter connected to an output of the summing unit, and a low pass filter connected to a reference signal input of the subtracting unit.

15. A device in accordance with claim 11, further comprising: an analog-digital converter; and a digital-analog converters, wherein: the summing unit is formed by a digital signal processor; outputs of the amplifiers are connected with inputs of the digital signal processor via the analog-digital converters; the subtracting unit is configured as an analog amplifier circuit; and an output of the digital signal processor is connected with the subtracting unit via the digital-analog converter.

16. A device in accordance with claim 11, further comprising: analog-digital converters; and a digital-analog converter, wherein: the summing unit and the subtracting unit are formed by a digital signal processor; outputs of the amplifiers are connected with inputs of the digital signal processor via the analog-digital converters; and an output of the digital signal processor is connected with the inputs of the amplifiers via the digital-analog converter.

17. A device in accordance with claim 11, wherein; said subtracting unit is configured to amplify the previous reference voltage by an attenuation factor being less than one.

18. A device in accordance with claim 11, wherein; each said respective device output providing a signal from a respective one of the measuring electrodes without common mode components.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic view showing a device according to the state of the art;

(2) FIG. 2 is a schematic circuit diagram showing principles of the present invention;

(3) FIG. 3 is a circuit diagram of a first exemplary embodiment of a device according to the present invention;

(4) FIG. 4 is a circuit diagram of a second exemplary embodiment of a device according to the present invention;

(5) FIG. 5 is a circuit diagram of a third exemplary embodiment of a device according to the present invention; and

(6) FIG. 6 is a circuit diagram of a fourth exemplary embodiment of a device according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

(7) Referring to the drawings, at first, the basic problem in the detection of small voltage signals, for example, on the body 1 of a patient, shown only schematically here, is disclosed in FIG. 1. It is shown thereby that both the patient 1 and the measuring device 3 are galvanically separated from the surrounding area ground 5, which is also absolutely necessary for the sake of safety. The result of this is that both the body 1 of the patient and the measuring device 3 are capacitively coupled to the surrounding area, so that a potential is formed at both. The ground 7 of the measuring device 3 is connected with the body 1 of the patient via an electrode 9. This leads to a current i.sub.a between the body 1 of the patient and the measuring device 3 because of the impedance Z.sub.a of the electrode 9. This in turn results in a common mode signal V.sub.cm, which is detected at the actual measuring electrodes 11 and is amplified in the amplifiers Op.sub.i and thus is also contained in the output signals thereof.

(8) By contrast, the present invention adds a reference signal V.sub.r to the signals V.sub.i-V.sub.j which are detected at the measuring electrodes 11. The reference signal V.sub.r is adapted such that the reference signal V.sub.r compensates the common mode signal, so that the signals E.sub.i-E.sub.j at the outputs A.sub.i-A.sub.j of the amplifiers Op.sub.i-Op.sub.j no longer contain any common mode signal component. This is first only schematically shown in FIG. 2.

(9) A circuit diagram of the first exemplary embodiment of the device according to the present invention is shown in FIG. 3. A summing unit 13 outputs a mean value, at summing unit output 15, of the output signals E.sub.1, . . . , E.sub.n of the amplifiers Op.sub.1, . . . , Op.sub.n, is arranged downstream of the amplifiers Op.sub.1, . . . , Op.sub.n. The summing unit 13 is connected to the amplifiers Op.sub.1, . . . , Op.sub.n, which amplify the input signals V.sub.1, . . . , V.sub.n, present at the inputs Y.sub.1, . . . , Y.sub.n. In this case, the summing unit 13 is designed as an analog circuitry device with an operational amplifier 17. The output signals E.sub.1, . . . , E.sub.n are fed to the non-inverting input of the operational amplifier 17 via suitably selected resistances R.sub.v.

(10) The mean value signal generated in the summing unit 13 is fed to a first input of a subtracting unit 19, which is likewise designed as an analog circuitry device in this exemplary embodiment. The subtracting unit 19 comprises an inverting adder 21 as well as an inverter 23, both of which have a correspondingly connected operational amplifier 25, 27.

(11) Besides receiving an input of the mean value signal generated in the summing unit 13, the output signal of the subtracting unit 19 is fed to the input of the subtracting unit 19 via an impedance converter 29, whereby the output signal of the subtracting unit 19 is not amplified or attenuated as a result of the two resistances R.sub.R of the inverting adder 21 being almost identical. However, in a preferred embodiment, these resistances may be selected to be slightly different in order to achieve a slight attenuation of the output signal of the subtracting unit 19, which portion of the output signal of the subtracting unit, or attenuated output signal is again fed to its input, i.e., the output signal is multiplied by a factor s less than one.

(12) The mean value signal generated by the summing unit 13 is amplified in the subtracting unit 19 by an amplification factor up, which is established by the ratio R.sub.R/R.sub.M. The signal output by the inverting adder 21 is then still inverted by the inverter 23 arranged downstream, so that the subtracting unit 19 then outputs a reference signal V.sub.r to the subtracting unit output. The reference signal V.sub.r is fed to the inverting inputs of the amplifiers Op.sub.1, . . . , Op.sub.n at their inverting inputs. This reference signal V.sub.r is then amplified in the amplifiers Op.sub.1, . . . , Op.sub.n in the known manner by an amplification =R.sub.1/R.sub.2.

(13) According to the present invention, the resistances R.sub.1, R.sub.2, R.sub.R and R.sub.M are selected, such that

(14) $R_M=R_R.Math.\frac{R_1}{R_2}$
applies.

(15) It is consequently fulfilled that the amplification factor 1/ corresponds to the reciprocal value of the amplification . Thus, the considerations which were already explained above apply, by the reference signal V.sub.r being precisely recursively optimized thereby, by the mean value signal amplified by the amplification factor 1/ being subtracted from an at first preset reference signal, whereby this amplification factor precisely corresponds to the reciprocal value of the amplification, with which the reference signal is amplified in the amplifiers at the input of the measuring device. Consequently, it is achieved that the output signal E.sub.1, . . . , E.sub.n output at the outputs A.sub.1, . . . , A.sub.n is free from common mode components.

(16) A circuit diagram of the second exemplary embodiment of a measuring device according to the present invention is shown in FIG. 4. The second exemplary embodiment differs from the first exemplary embodiment only in that the inputs of the subtracting unit 19 and thus in this case the inputs of the inverting adder 21 have low-pass filters 31, 33, so that components of high frequency, which are contained in the mean value signal output by the summing unit 13 as well as that of the output of the subtracting unit 19, are suppressed.

(17) Besides, provisions are made in this second exemplary embodiment for the input of the subtracting unit 19 or of the inverting adder 21, which is connected with the output of the subtracting unit 19, to be formed by two resistances, R.sub.R1, R.sub.R2, such that the output signal of the subtracting unit 19 and thus the reference V.sub.r is attenuated, since the resistances R.sub.R1 and R.sub.R2 are selected, such that their sum is slightly greater than R.sub.R. Thus, an attenuation of the reference signal is achieved in order to ensure that the device operates in an overall stable manner.

(18) A circuit diagram of the third exemplary embodiment s shown in FIG. 5. The summing unit 13 and the subtracting unit 19 are formed by a digital signal processor 35, in which the functions of the summing unit 13 and those of the subtracting unit 19 are executed by software. However, in this case, the programming is selected, such that the mean value generated by the summing unit 13 is amplified by the amplification factor 1/ before it is subtracted from a reference value, whereby this amplification factor likewise corresponds to the reciprocal value of the amplification, with which the reference signal fed to the amplifiers Op.sub.1, . . . , Op.sub.n is amplified. The outputs A.sub.1, . . . , A.sub.n are connected with the digital signal processor 35 via analog-digital converters 37 in this third exemplary embodiment. Furthermore, a digital-analog converter 39 is provided, with which the reference signal V.sub.r is converted from a digital signal into an analog signal, in order to subsequently feed this signal to the Op.sub.1, . . . , Op.sub.n.

(19) A circuit diagram of the fourth exemplary embodiment is shown in FIG. 6. The summing unit 13 can be embodied alone by a digital signal processor 35, whose inputs are connected with the outputs A.sub.1, . . . , A.sub.n via an analog-digital converter 37. The mean value signal calculated in the signal processor 35 is again sent to the subtracting unit 19, which is designed as analog circuitry in this case, via a digital-analog converter 39. This subtracting unit 19 is designed corresponding to the second exemplary embodiment (see FIG. 4), which explanation is hereby referenced. In particular, the relationship of the resistances R.sub.1, R.sub.2, R.sub.M and R.sub.R is selected in such a way as this has already been described in connection with the first exemplary embodiment, so that

(20) $R_M=R_R.Math.\frac{R_1}{R_2}$
applies.

(21) Thus, all exemplary embodiments have in common that in the detection of electric potentials at the inputs Y.sub.1, . . . , Y.sub.2 of the measuring device, the signals are amplified by amplifiers Op.sub.1, . . . , Op.sub.n, whereby a mean value signal of the outputs A.sub.1, . . . , A.sub.n of the amplifiers Op.sub.1, . . . , Op.sub.n is thereby formed. A reference signal V.sub.r is subsequently generated recursively in such a way that the mean value previously generated, amplified by an amplification factor 1/, is subtracted from at least a portion of the reference signal V.sub.r and this recursively generated reference signal V.sub.r is fed to the inputs of the amplifiers Op.sub.1, . . . , Op.sub.n. In these amplifiers Op.sub.1, . . . , Op.sub.n, the reference signal is amplified by an amplification factor in relation to the outputs A.sub.1, . . . , A.sub.n. In this case, the measuring device is thereby designed, such that the amplification corresponds to the reciprocal value of the amplification factor 1/.

(22) The above-described exemplary embodiments of measuring devices are each connected with the advantage that, due to the design of the device, a reference signal V.sub.r is generated, which leads to a signal being generated at the outputs A.sub.1, . . . , A.sub.n, which is free from common mode components.

(23) While specific embodiments of the invention have been shown and described in detail to illustrate the application of the principles of the invention, it will be understood that the invention may be embodied otherwise without departing from such principles.