Method for gallium nitride on diamond semiconductor wafer production

Abstract

A GaN on diamond wafer and method for manufacturing the same is provided. The method comprising: disposing a GaN device or wafer on a substrate, having a nucleation layer disposed between the substrate and a GaN layer; affixing the device to a handling wafer; removing the substrate and substantially all the nucleation layer; and bonding the GaN layer to a diamond substrate.

Claims

1. A GaN on Diamond wafer, the system comprising: a diamond layer; a first layer of GaN bonded on said diamond layer at a low temperature, wherein said low temperature is below 400 degrees Celsius, said first layer of GaN being substantially free of a nucleation layer; a second GaN layer disposed on said first GaN layer; an AlGaN layer disposed on said second GaN layer, opposite said first GaN layer; and source, gate, drain, and passivation transistor elements disposed on said AlGaN layer; a handling wafer disposed on said source, gate, drain, and passivation transistor elements; wherein said handling wafer is removed from said source, gate, drain, and passivation transistor elements following said bonding of said layer of GaN on said diamond layer; and at least one of passive components and transmission lines fabricated directly on said diamond layer, mitigating coefficient of thermal expansion mismatch.

2. The wafer of claim 1 wherein said second GaN layer is not greater than 0.2 m thick.

3. The wafer of claim 1 wherein coefficient of thermal expansion mismatch between said GaN layer and said diamond layer is minimized.

4. The wafer of claim 1, further comprising GaN devices disposed on said layer of GaN prior to the bonding of said GaN layer to said diamond layer.

5. The method of claim 4 wherein said bonding comprises bonding said GaN layer to said diamond layer with a low-temperature, low thermal resistance bond.

6. The method of claim 1, wherein said low temperature is below 150 degrees Celsius.

7. A method for manufacturing a GaN on Diamond device, the method comprising: providing a substrate; disposing a first GaN layer, using a low temperature polymer-based adhesive, on said substrate, having a nucleation layer disposed between said substrate and said first GaN layer; disposing a second GaN layer on said first GaN layer; disposing an AlGaN layer on said second GaN layer; disposing source, gate, drain, and passivation transistor elements on said AlGaN layer; affixing said source, gate, drain, and passivation transistor elements to a handling wafer; removing said substrate and substantially all said nucleation layer; and bonding said GaN layer to a diamond layer; and fabricating passive components and transmission lines directly on said diamond layer, thereby mitigating coefficient of thermal expansion mismatch.

8. The method of claim 7 wherein said substrate material comprises Si.

9. The method of claim 7 further comprising thinning said GaN layer prior to bonding said GaN device to said diamond layer.

10. The method of claim 7, wherein: said substrate layer is about 600 m thick; said MN nucleation layer is 200-2000 ; said first GaN layer is 1-3 m thick; said second GaN layer is 0.2-1.0 m thick; said AlGaN layer is 100-300 thick; and said Diamond layer is 50-500 m thick.

11. The method of claim 9 wherein said bond comprises Van der Waal bonds.

12. The method of claim 7 further comprising annealing said GaN layer bonded to said diamond layer.

13. The method of claim 12 wherein said annealing is at up to 400 C.

14. The method of claim 7 further comprising removing not more than 90% of said GaN layer.

15. The method of claim 7 wherein said step of removing said substrate and said substantially all said nucleation layer comprises mechanical removal.

16. The method of claim 7, wherein said step of removing said substrate and said substantially all said nucleation layer further comprises etching and or mechanical polishing.

17. The method of claim 7 wherein said handling wafer is attached to said GaN device with polymer-based adhesive.

18. The method of claim 7 further comprising removing said handling wafer.

19. The method of claim 7 further comprising smoothing said diamond layer before bonding said GaN layer to said diamond substrate.

20. The method of claim 7, wherein: said substrate layer is 600 m thick; said MN nucleation layer is 500 thick; said first GaN layer is 1.5 m thick; said second GaN layer is 0.2 m thick; said AlGaN layer is 190 thick; said Diamond layer is 100 m thick; said Diamond layer is polished to a roughness of 0.5-3.0 nm RMS; and said first GaN layer is polished to less than 1 nm roughness.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a block diagram illustrating a known GaN on SiC HEMT.

(2) FIG. 2 is a block diagram illustrating a GaN on diamond HEMT configured in accordance with one embodiment of the present invention.

(3) FIG. 3A is a block diagram illustrating a GaN workpiece configured in accordance with a step in one embodiment of the present invention.

(4) FIG. 3B is a block diagram illustrating a removal of a substrate and nucleation layer from workpiece configured in accordance with a step in one embodiment of the present invention.

(5) FIG. 3C is a block diagram illustrating a GaN layer on a carrier configured in accordance with a step in one embodiment of the present invention.

(6) FIG. 3D is a block diagram illustrating a GaN bonded to a diamond substrate configured in accordance with a step in one embodiment of the present invention.

(7) FIG. 4A is a block diagram illustrating a GaN on workpiece configured in accordance with a step in one embodiment of the present invention.

(8) FIG. 4B is a block diagram illustrating a GaN on workpiece bonded to a handling wafer configured in accordance with a step in one embodiment of the present invention.

(9) FIG. 4C is a block diagram illustrating a removal of a substrate from workpiece configured in accordance with a step in one embodiment of the present invention.

(10) FIG. 4D is a block diagram illustrating etching of a GaN layer to remove thickness configured in accordance with a step in one embodiment of the present invention.

(11) FIG. 4E is a block diagram illustrating provision of a diamond substrate configured in accordance with a step in one embodiment of the present invention.

(12) FIG. 4F is a block diagram illustrating bonding of a diamond substrate to a GaN layer configured in accordance with a step in one embodiment of the present invention.

(13) FIG. 4G is a block diagram illustrating removal of a handling wafer from a GaN on diamond HEMT configured in accordance with a step in one embodiment of the present invention.

(14) FIG. 4H is a block diagram illustrating heating of a GaN on diamond HEMT configured in accordance with a step in one embodiment of the present invention.

DETAILED DESCRIPTION

(15) A GaN-on-Diamond approach configured according to one embodiment uses low temperature bonding techniques (below 400 C) to attach diamond substrates to GaN layers. Mechanical stress due to thermal expansion mismatch between GaN and diamond is minimized, leading to smaller wafer bow, easier and higher yield wafer processing and improved device lifetime. Such embodiments also describe a method to uniformly reduce GaN epitaxial layer thickness to further improve device thermal property for higher performance and reliability.

(16) As illustrated in FIG. 1, a traditional GaN on SiC HEMT includes a thick GaN layer 5 and a nucleation layer 7. Heat from a hotspot 9 on a conventional must travel through the GaN layer and the nucleation layer before it begins to dissipate in the SiC layer 3. As seen in FIG. 2, embodiments of the present invention provide a wafer which includes a thinner GaN layer in comparison. In such an embodiment, the final GaN-on-diamond wafer 10 does not have a nucleation layer.

(17) In contrast to conventional GaN-on-Diamond technology, embodiments of the present invention provide a process flow which starts with devices fabricated on flat GaN epitaxial layers formulated on SiC sapphire, or other suitable wafers using standard high yield GaN wafer processing technology. The sapphire substrates of such an embodiment are subsequently removed using an industry-standard pulsed laser, while embodiments utilizing Silicon or SiC substrates may be removed using chemical etching, mechanical polishing and combinations thereof. In such embodiments, an Aluminum Nitride (AlN) nucleation layer is removed, eliminating the thermal barrier presented by the high defect density layer. This takes full advantage of the heat spreading capability of the diamond.

(18) A method for the manufacture of a GaN-on-Diamond transistor according to embodiments of the present invention is illustrated in FIGS. 3A-3D. In FIG. 3A, a sapphire, Silicon, or silicon carbide (SiC) substrate 32 is provided having an AlN Nucleation layer 34 disposed upon it, and upon which a GaN layer 36, an AlInN etch stop 38, a second GaN layer 40, and an AlGaN layer disposed upon it 42. In one such embodiment, the starting AlN nucleation layer 34 may be 200-2000 thick, the first GaN layer 36 may be 1-3 m thick, the etch stop 38 may be 0.05-0.5 m thick, the second GaN layer 40 may be 0.2-1.0 m thick, and the AlGaN layer 42 may be 100-300 thick. An adhesive layer 41 may also be present. As noted above, the substrate 32 and AlN nucleation layer 34 are removed.

(19) As illustrated in FIG. 3C, the removal process, according to one embodiment of the present invention, may uniformly remove up to 90% of the mostly high defect density, poor thermal conductivity GaN layer in the path from a hot spot to diamond heat sink. Removal to achieve a very thin GaN layer 40 allows formation of GaN islands so the GaN/diamond interface occurs only in localized areas at the active devices, therefore minimizing CTE mismatch stress buildup across the GaN/diamond interface.

(20) In monolithic microwave integrated circuits (MMICs), passive components and transmission lines can be fabricated directly on the diamond substrate, mitigating CTE mismatch concerns.

(21) As illustrated in FIG. 3D, the GaN layer 40 is adhered to the diamond substrate 44, which in one embodiment is 50-500 m in thickness. Low-temperature (<150 C.) polymer-based adhesive bonding 46 is used in one embodiment of the present invention and significantly reduces the impact of CTE mismatch between diamond and GaN active layers (low CTET product) for improved reliability. In alternative embodiments, the bonding process may be van der Waal or covalent bonding.

(22) As illustrated in FIGS. 4A-4H, according to one embodiment, a GaN epitaxial layer on a suitable substrate (from a material such as Sapphire, Si, SiC) wafer 50 is low temperate bonded to a carrier 52, in some embodiments at a temperature before 400 C. or below 500 C. The carrier bond, in some embodiments, may be adhesive and according to some embodiments that adhesive may be organic. As illustrated in FIG. 4C, through the sapphire 32 and any nucleation layer is removed, leaving the GaN 54 and transistor 56 and the carrier 52. The GaN layer 54 is etched, in one embodiment, as in FIG. 4D, to remove thickness. In alternative embodiments the GaN layer 54 may be used without etching. GaN 54 may be polished and/or etched to approximately less than 1 nm roughness. A diamond layer 44 is then provided. The diamond layer 44 may be polished to a roughness of approximately 0.5-3.0 nm RMS. The diamond 44 of one embodiment of the present invention may also be approximately 1000-2500 W/mK diamond. The diamond layer 44 is then bound to the GaN layer 54. The bonding may take place at room temperature, and may comprise Van der Waal bonding. The bonding process may involve surface treatments in preparation of bonding. The carrier is then removed, as in FIG. 4G. The resulting wafer is then thermally annealed as in FIG. 4H. The thermal annealing may take place at up to approximately 400 C. to convert Van der Waal bonds to electro/covalent bonds.

(23) In one embodiment of the present invention, GaN devices can be fabricated before diamond bonding with high yield using conventional GaN processing technology. Since diamond bonding to GaN epitaxial layers is achieved at a lower temperature (e.g. between room temperature to approximately 400 C.), the mechanical stress generated in the GaN-on-Diamond structurewhich is proportional to the change in temperature during bonding temperatureis minimized, leading to low wafer bow and reduced tensile stress in the GaN epitaxial layers 54. The bonding can be made with a thin layer, high thermal conductivity bonding adhesive 46 (e.g., SiN, BN, or AlN) or through a GaN-GaN (attached on diamond) covalent bonding. Diamond substrates 44 can be mounted onto an optical-flat glass block with an adhesive such as high temperature organics or alloyed metal layers (e.g., AuGe) to provide a good flatness suitable for high yield binding to GaN. alternative embodiments of the present invention also propose a buried InAlN etch stop layer 36 in the GaN epitaxial layer 36, 40 to allow a uniform etch of GaN to thin the GaN channel layer (e.g., 0.2-1 um) after the removal of the substrate. The thin GaN layer 40 in the device, coupling with the diamond substrate 44 improves device thermal conductivity by 3-5 over conventional GaN on SiC HEMT with minimal impact from GaN/diamond CTE mismatch. The high performance GaN-on-sapphire or GaN-on-SiC epitaxial layer can be used as the starting epitaxial layer material for higher device performance.

(24) In summary, embodiments of the present invention propose a low temperature, low stress diamond bonding technique to combine high thermal conductivity diamond substrates with GaN epitaxial layers to produce a reliable device with 3-5 higher power handling capability compared to GaN-on-SiC. The resulting performance improvements will enable higher power RF sources in smaller footprints, and major reductions in system size, weight and power (SWaP) due to associated relaxation of prime power and cooling requirements.

(25) The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.