Charge-trapping layer with optimized number of charge-trapping sites for fast program and erase of a memory cell in a 3-dimensional NOR memory string array

Abstract

A thin-film memory transistor includes a source region, a drain region, a channel region, a gate electrode, and a charge-trapping layer provided between the channel region and the gate electrode and electrically isolated therefrom, wherein the charge-trapping layer has includes a number of charge-trapping sites that is 70% occupied or evacuated using a single voltage pulse of a predetermined width of 500 nanoseconds or less and a magnitude of 15.0 volts or less. The charge-trapping layer comprises silicon-rich nitride may have a refractive index of 2.05 or greater or comprises nano-crystals of germanium (Ge), zirconium oxide (ZrO.sub.2), or zinc oxide (ZnO). The thin-film memory transistor may be implemented, for example, in a 3-dimensional array of NOR memory strings formed above a planar surface of a semiconductor substrate.

Claims

1. A thin-film memory transistor, comprising a source region, a drain region, a channel region, a gate electrode, and a charge-trapping layer provided for charge storage between the channel region and the gate electrode and electrically isolated therefrom, wherein the charge-trapping layer comprises a silicon-rich nitride, with a thickness that is less than 1.0 nm and a trap-site area density of less than 2.7×10.sup.12 electrons per cm.sup.2.

2. The thin-film memory transistor of claim 1, wherein the charge-trapping sites are greater than 70% occupied or evacuated using a single voltage pulse of a predetermined width of 500 nanoseconds or less and a magnitude of 15.0 volts or less.

3. The thin-film memory transistor of claim 2, wherein the magnitude of the voltage pulse is between 8.0-15.0 volts.

4. The thin-film memory transistor of claim 2, wherein the single voltage pulse changes the threshold voltage of the thin-film memory transistor by 1.0-4.0 volts.

5. The thin-film memory transistor of claim 1, wherein the silicon-rich nitride has a refractive index of 2.05 or greater.

6. The thin-film memory transistor of claim 1, wherein the thin-film memory transistor is provided in a NOR memory string.

7. The thin-film memory transistor of claim 6, wherein the NOR memory string is one of a plurality of NOR memory strings arranged in a memory structure formed above a semiconductor substrate.

8. The thin-film memory transistor of claim 2, wherein the predetermined width is less than 100 nanoseconds.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a schematic cross-section of vertical-channel, polycrystalline thin-film transistor or memory cell 100 with source region 10, drain region 20, channel region 30, tunnel oxide layer 40, charge-trapping layer 50, blocking oxide layer 60, and gate conductor 70.

(2) FIG. 2 demonstrates that a greater magnitude in the voltage placed on the gate conductor to effectuate programming or erase of a memory cell shortens the program or erase time.

(3) FIG. 3 shows a collection of waveforms each representing threshold voltage V.sub.t of a memory cell after predetermined number of program and erase operations using a predetermined program or erase voltage over 10.sup.8 programming and erase cycles.

(4) FIG. 4 shows a distribution of memory cells in “programmed” and “erased” states in one memory system.

(5) FIG. 5 shows narrow distributions of threshold voltages in memory cells that are in the “programmed” and “erased” states, achieved by limiting the number of charge-trapping sites in their charge-trapping layers.

(6) To facilitate cross-references among the figures, like elements in the figures are assigned like reference numerals.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(7) In this detailed description, process steps described in one embodiment may be used in a different embodiment, even if those steps are not described in the different embodiment. When reference is made herein to a method having two or more defined steps, the defined steps can be carried out in any order or simultaneously (except where context or specific instruction excludes that possibility), and the method can include one or more other steps carried out before any of the defined steps, between two of the defined steps, or after all the defined steps (except where context excludes that possibility).

(8) According to one embodiment of the present invention, the distribution of threshold voltages of memory cells in a “programmed” or an “erased” state may be reduced by limiting the available number of charge-trapping sites needed to obtain a threshold voltage difference of ΔV.sub.t between memory cells of the “programmed” and “erased” states. FIG. 5 shows narrow distributions of threshold voltages in memory cells that are in the “programmed” (i.e., region 501b) and “erased” (i.e., region 501a) states, achieved by limiting the number of charge-trapping sites in their charge-trapping layers. When the number of charge-trapping sites is so small, such that a program pulse supplies sufficient electrons to completely or nearly completely fill the available charge-trapping sites (e.g., greater than 70% filled), the read-verify procedure is obviated for the program operation. Likewise, when the number of charge-trapping sites is so small, such that an erase pulse removes sufficient electrons to completely or nearly completely vacate the available charge-trapping sites, the read-verify procedure is obviated for the erase operation (e.g., greater than 70% evacuated). By eliminating the read-verify procedure, program and erase times for the memory system are much reduced.

(9) Another method to narrow the distributions of threshold voltages in the memory cells in the “programmed” or the “erased” state is to reduce difference ΔV.sub.t in the threshold voltages between the “programmed” state and the “erased” state in the memory cell. The widths of the distributions of memory cells in the “programmed” and the “erased” states are dependent, in part, on the value of threshold voltage difference ΔV.sub.t. A larger threshold voltage difference ΔV.sub.t results in wider distributions in memory cells in the “programmed” and the “erased” states. For example, the distributions of memory cells in the “programmed” and the “erased” states are narrower when highest voltage V.sub.e for the “erased” state and lowest threshold voltage V.sub.p for the “programmed” state are set at 1.0 volts and 2.0 volts (i.e., ΔV.sub.t equals 1.0 volts), respectively, than when they are set at 2.0 volts and 6.0 volts (i.e., ΔV.sub.t equals 1.0 volts).

(10) The present invention provides numerous ways for providing a charge-trapping layer with an optimal number of charge-trapping sites. For example, to achieve a 1.0-volt threshold difference ΔV.sub.t for a polysilicon thin-film transistor, a total electron area, density of 2.7×10.sup.12 e.sup.−/cm.sup.2 is required of the charge-trapping layer. The trap-site density for silicon-rich silicon nitride (SRN) with an refractive index of 2.20, for example, has been reported to be 2.5×10.sup.19 e.sup.−/cm.sup.3. (See, e.g., the article “Electron trap density distribution of Si-rich silicon nitride extracted using the modified negative charge density decay model of silicon-oxide-nitride-oxide-silicon structure at elevated temperature,” by T. H. Kim, et al., Applied Physics Letters 89, 063508-063511 (2006).) Therefore, for a 1.0 nm thick SRN charge-trapping layer, the trap-site area density is 2.5×10.sup.19 e.sup.−/cm.sup.3×1.0×10.sup.−7 cm) or 2.5×10.sup.12 e.sup.−/cm.sup.2. For reference, a 1.0 nm thick SRN film is a much thinner charge-trapping layer than those used in current state-of-the-art SRN films used in multi-level (MLC) NAND memory devices; such SRN films in MLC NAND devices are typically 7.0 nm or more thick. MLC NAND devices typically have multiple “programmed” and “erased” states, and require the read-verify procedure to attain any of the multiple “programmed” and “erased” states. The program and erase times of MLC NAND devices are therefore notoriously long (e.g., tens to hundreds of microseconds).

(11) In one embodiment, a memory cell in a NOR memory string—which is configured in the manner disclosed in the Related Application, incorporated by reference above—has a 1.0 nm thick SRN charge-trapping layer provided between a 1.0 nm thick tunneling oxide layer and a 1.0 nm thick blocking oxide layer. The Related Application teaches forming arrays of such NOR memory strings in a 3-dimensional memory structure above a planar surface of a semiconductor substrate. It is desired to program or erase the memory cell using a single pulse of 500 ns or less wide to effectuate threshold voltage difference ΔV.sub.t of 1.0 volts between “programmed” or “erased” states. In that memory cell the dominant program or erase mechanism is believed direct tunneling. Under such conditions, the magnitude of the required program or erased voltage to program or erase such a memory cell using a single pulse of 500 ns wide or narrower, preferably 100 ns or narrower, may be empirically determined, but estimated to be about 8.0-15.0 volts.

(12) According to another embodiment of the present invention, one method to achieve a advantageously small number of trap-sites in a charge-trapping layer of a memory cell is to reduce the trap-site density in the material of the charge-trapping layer (e.g., SRN). The trap-site density in SRN is dependent in part, for example, on its composition. SRN films may vary in refractive index between about 2.0 and about 2.4, for example, between (See, e.g., the article “Explanation of the charge-trapping properties of silicon nitride storage layers for NVM devices Part I: Experimental evidences from physical and electrical characterization,” by E. Vianello, et al., IEEE Transactions on Electron Devices 58, no. 8, pp. 2483-2489 (2011).) When the trap-site density is reduced to less than 2.5×10.sup.19 e.sup.−/cm.sup.3, a SRN charge-trapping layer that is greater than 1.0 nm thick may be used to achieve the 1.0-volt threshold difference ΔV.sub.t, discussed above.

(13) Alternatively, a charge-trapping layer with desirably small number of trap sites may be achieved using nano-crystals (also known as quantum dots) in the charge-trapping layer; suitable materials that contain nano-crystal include, for example, various charge-transporting layers (CTLs) used in many electronic devices. (See, e.g., the articles (i) “Charge-trap memory device fabrication by oxidation of Si.sub.1-x,Ge.sub.x” by Y.-C. King et al., IEEE Transactions on Electron Devices 48, no. 4, pp. 696-800 (2001); and (ii) “Nanoislands-based charge trapping memory: A scalability study,” by N. El-Atab, et al., IEEE Transactions on Nanotechnology 16, no. 6, pp. 1143-1145 (2017).) Nanocrystals of germanium (Ge), zirconium oxide (ZrO.sub.2), or zinc oxide (ZnO), or any suitable material, can be fabricated in a manner to control the area density in the resulting material, thereby allowing a good control of the trap-site area density.

(14) As the electric field across the tunnel oxide layer during the programming or erase operational for a charge-trapping layer of the present invention is significantly lower than under a conventional programming or erase operation, the endurance of the memory device is significantly enhanced.

(15) The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible. The present invention is set forth in the following claims.